GB2391777A

GB2391777A - A multi-carrier receiver comprising a Reed-Solomon decoder with an erasures input and a channel state indication input

Info

Publication number: GB2391777A
Application number: GB0323575A
Authority: GB
Inventors: Adrian Paul Robinson
Original assignee: British Broadcasting Corp
Current assignee: British Broadcasting Corp
Priority date: 2001-05-03
Filing date: 2002-05-01
Publication date: 2004-02-11
Anticipated expiration: 2022-05-01
Also published as: GB2391776B; GB0323575D0; GB2391777B; GB2391776A; GB0323574D0

Abstract

A receiver for many-carrier signals, preferably DVB-T signals, is disclosed. A channel state indication is obtained on a symbol-by-symbol basis 240, 302, representing aggregate channel state over a plurality of carriers. Erasures information is provided from a Viterbi decoder 124. The erasure information from the Viterbi decoder and a signal derived from the channel state indication are both provided as erasure inputs to a Reed-Solomon decoder 128 and one of the two erasure inputs is selected in combine/select means 322. An erasure is a byte which is known to contain at least one bit error, and is flagged as such.

Description

( 239 1 777

- 1 - IMPROVEMENTS IN DECODERS FOR MANY-CARRIER

SIGNALS, IN PARTICULAR IN DVB-T RECEIVERS

Backaround of the Invention

5 This invention relates to improvements in decoders for many-carrier signals, in particular in DVB-T receivers. The invention is described in the context of the reception of so-called DVB-T signals, that is signals in lo accordance with the Digital Video Broadcasting standard for Terrestrial television, as defined in European Telecommunication Standard ETS 300 744. The invention in its various aspects is not however necessarily limited to use with such signals, but may be usable with other coded many-carrier transmission systems, particularly though not exclusively those using orthogonal frequency-division multiplexing (OFDM).

The DVB-T standard specifies the use of two types of interleaving in the forward error corrector in the 20 transmitter. These comprise an outer convolutional interleaves and an inner interleaved. The effect of these interleavers is to spread the data in time, so that a short error burst does not affect bits which are adjacent in the original signal, but rather affects bits which are 25 spread out over a period of time. This reduces the instantaneous error rate to a level where the errors can be corrected by the error correction circuitry in the receiver. This works well for most types of transmission error.

30 However, we have found that it can fail when there is

( - 2 impulsive interference with bursts of interference which have a duration of greater than, say, lops. What happens then is that the interleaving spreads the errors in time but the error rate is still too high for the error 5 correction circuitry, and thus the errors persist for a longer duration than they would have done if there was no interleaving at all.

With a many-carrier system such as coded OFDM (COFDM), the interference is spread over many samples by lo the time domain/frequency domain transformation effected e.g. by a fast Fourier transform (FFT) circuit. The adverse effect just described is therefore more likely to arise than with a conventional single-carrier system.

The present invention is directed to various ways in i5 which this adverse effect of impulsive interference can be ameliorated. It would be possible to achieve some improvement by increasing the depth of the outer interleaving, so that instead of being spread over 12-15 packets the errors were 20 spread over say 105 packets. A larger memory is now required for the outer deinterleaver in the receiver and the system could still fail unless the interval between bursts of impulses were fairly long.

Another possibility would be to increase the :s redundancy in the ReedSolomon code in the outer coder of the DVB-T standard. Increasing the redundancy will, however, correspondingly decrease the data capacity, and would upset the convenient numerical relationship adopted in the standard which leads to a whole number of packets 30 in a super-frame.

Reference may be made to United States Patent US-A-5,687,164 and European Patent Applications EP-A-O 827 298, 0 827 299, and 0 827 300 which describe the use of a Viterbi decoder to decode a QAM signal.

as International Patent Application WO97/13378 describes obtaining channel state information from QPSK modulated symbols. United States Patent US-A-5,636,253 describes

- 3 - selecting for each symbol the nearest of the CAM points and calculating the difference from it, and multiplying it with a weighting coefficient. International Patent Application WO92/22162 describes a CAM system in which the 5 constellation is modified in accordance with channel quality. United States Patent US-A-5,134,635 describes a convolutional decoder which assigns bit metrics to at least one bit of a symbol, and uses soft-decision Viterbi decoding with channel state information.

c Summary of the Invention

The invention in its various aspects is defined in the independent claims below, to which reference may now be made. Advantageous features are set forth in the appendant claims.

15 A preferred embodiment of the invention is described in more detail below with reference to the drawings. The preferred embodiment takes the form of a decoder for many-carrier signals, particularly OFDM, such as is used in the DVB-T system. It has been proposed to use so information about channel quality to provide erasures signalling to a Reed-Solomon decoder. In accordance with this invention it is now proposed to detect the many-carrier or OFDM symbols which have been affected by an impairment that lasts for only a short time, of the 2s order of a symbol or less, and to apply this signal to the erasures signal input of a Reed- Solomon decoder.

The present invention can be used independently or together in various combinations with other features which form the subject of our applications 0210016.2 30 (publication No. 2,378,369) and 031357Y related hereto by division. These features may be summarized as follows:

- 4 (1) In a receiver for a many-carrier signal, a channel state indication is obtained by averaging over one symbol.

This can then be compared with an average over a few symbols, so as to detect impulsive interference and other 5 short-duration impairments. The indication of impulsive interference can then be employed in relation to the soft decisions fed to a Viterbi decoder. Preferably, however, the channel state indication is averaged over each one-quarter or onesixteenth or similar proportion of a lo symbol (rather than a full symbol period) and is compared with the corresponding averages over a few symbols. This provides substantial savings in memory requirements.

(2) In a receiver for a many-carrier signal, the receiver comprising a Viterbi decoder followed by a Reed-Solomon 15 decoder, erasures information from the Viterbi decoder is used in the Reed-Solomon decoder, making use of its errors and erasures decoding features. This increases the number of errors that can be corrected, without requiring a change to the Standard specifying the DVB-T signal.

20 (3) A control output is provided from a Viterbi decoder which is dependent upon the error rate over a small number of bytes. This can in particular be used in combination with the feature in the preceding paragraph (2).

(I) To assist the above operations, the symbol 25 deinterleaving in the outer deinterleaver of an OFDM receiver is preferably made deeper, over, e.g. four symbols, and a corresponding alteration is made at the transmitter.

- 5 - Brief Descrintion of the Drawings The invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which: 5 Figure 1 is a schematic block diagram of a known DVB-T transmitter; Figure 2 shows the construction of the punctured convolutional coder forming the inner coder of the transmitter of Figure 1; 10 Figure 3 is a schematic block diagram of a typical DVB-T receiver design; Figure 4 shows the metric assignment and Remapping circuit of the receiver of Figure 3 when constructed in accordance with our European Patent Application 15 EP-A-O 991 239;

Figure 5 is a block schematic diagram of part of a DVB-T receiver embodying the present invention in its various aspects; Figure 6 is a block diagram of an averages circuit 20 used in Figure 5; Figure 7 shows an improved Viterbi decoder used to signal erasures to the Reed-Solomon decoder in the circuitry of Figure 5; and Figure 8 illustrates the operation of an inner 25 interleaver with increased depth.

Detailed Descriotion of the Preferred Embodiment The preferred embodiment is implemented as a DVB-T receiver. To enable an understanding of the present invention a description of the principles of a DVB-T

30 transmitter and receiver are first described with reference to Figures 1 to 3. A channel state measurement system for use in DVB-T receivers and based on our European Patent Application EP-A-O 991 239 is then described with reference to Figure 4. Subsequently a

f - 6 - receiver embodying the invention in its various aspects is described with reference to Figures 5 et seq.

DVB-T Transmitter Figure 1 is a block diagram of a transmitter 10 for s use in the Digital Video Broadcasting standard for Terrestrial television (DVB-T) as defined in European Telecommunication Standard ETS 300 744 (hereinafter "the standard"). Reference should be made to that standard for further details; the following description is by way of a

lo summary for the purpose of illustrating the present

invention. The transmitter receives video (V), audio (A), and data (D) signals from appropriate signal sources via inputs 12 and these are applied to an MPEG-2 coder 14.

15 The MPEG-2 coder includes a separate video coder 16, audio coder 18 and data coder 20, which provide packetized elementary streams which are multiplexed in a programme multiplexer 22. Signals are obtained in this way for different programmer, that is to say broadcast channels, 20 and these are multiplexed into a transport stream in a transport stream multiplexer 24. Although considered as part of the transmitter for the purposes of this specification, the components up to the multiplexer 29

will normally be located at the studio complex. The 25 output of the transport stream multiplexer 24 consists of packets of 188 bytes and is applied to a randomiser 26 for energy dispersal, where the signal is combined with the output of a pseudo-random binary sequence (PRBS) generator received at a terminal 28. The randomiser more evenly 30 distributes the energy within the RF (radio frequency) channel. The MPEG-2 coding and multiplexing and the randomising are not further described as they are not relevant to an understanding of the present invention.

For further details of MPEG-2 reference may be made to 35 standard ISO/IEC 13818 "Coding of moving pictures and

( - 7 - associated audio". An introductory discussion may be found, for example, in "Digital Television" by Herve Benoit, 1997, ISBN 0340691905.

The signal is now applied to a channel coding section 5 30 which is generally known as the forward error corrector (FEC) and which comprises four main components, namely: an outer coder 32, an outer interleaved 34, an inner coder 3G, and lo an inner interleaved 38.

These will now be described. The two coding stages 32,36 provide a degree of redundancy to enable error correction at the receiver. The two interleaving stages 34,38 are necessary precursors for corresponding s deinterleavers at a receiver so as to break up bursts of errors so as to allow the error correction to be more effective. The outer coder 32 is a Reed-Solomon (RS) coder, which processes the signal in packets of 188 bytes and zo adds to each packet 16 error protection bytes. This allows the correction of up to 8 random erroneous bytes in a received word of 204 bytes. This is known as a (204, 188, t=8) Reed-Solomon code. This is achieved as a shortened code using an RS (255, 239, t-8) encoder but 25 with the first 51 bytes being set to zero.

The outer interleaver 34 effects a Forney convolutional interleaving operation on a byte-wise basis within the packet structure, and spreads burst errors introduced by the transmission channel over a longer time 30 so they are less likely to exceed the capacity of the RS coding. After the interleaved, the nth byte of a packet remains in the nth byte position, but it will usually be in a different packet. The bytes are spread successively over 12 packets, so the first byte of an input packet goes 3s into the first output packet, the second byte of the input packet is transmitted in the second output packet, and so

l - 8 on up to the twelfth. The next byte goes into the first packet again, and every twelfth byte after that. As a packet contains 204 bytes, and 204 = 12 x 17, after the outer interleaving a packet contains 17 bytes that come 5 from the same original packet.

The inner coder 36 is a punctured convolutional coder (PCC). The system allows for a range of punctured convolutional codes, based on a mother convolutional code of rate with 64 states. Figure 2 is a block diagram 0 illustrating a hardware implementation of the convolutional coder. The data input is applied to a series of six one-bit delays 40 and the seven resultant bits which are available are combined in different ways by two modulo-2 adders 42,44, as shown. These adders provide 15 the output of the inner coder in the form of an X or Gl output and a Y or G2 output, the letter G here standing for the generator sum. The X and Y outputs are combined into a single bit stream by a serialiser 45.

The puncturing is achieved by discarding selected 20 ones of the X and Y outputs in accordance with one of several possible puncturing patterns. Without puncturing, each input bit gives rise to two output bits. With puncturing one of the following is achieved: Every 2 input bits give 3 output bits 25 Every 3 input bits give 4 output bits Every 5 input bits give 6 output bits Every 7 input bits give 8 output bits This is set out in Table 2 in the standard; the punctured code rates are represented in the form 2/3, 3/4, 30 5/6 and 7/8. The puncturing takes place in the serialiser 45.

Returning to Figure l, the inner interleaver 38 in accordance with the standard is implemented as a two-stage process, namely bit-wise interleaving followed by symbol 35 interleaving. Both are block based. First, however, the incoming bit stream is divided into 2, 4 or 6 substreams, depending on whether QPSK (quadrature phase shift keying),

- 9 - 16-QAM (quadrature amplitude modulation), or 64-QAM is to be used, as described below. Each sub-stream is separately bit interleaved and all the streams are then symbol interleaved.

5 The bit interleaved uses a bit interleaving block size which corresponds to one-twelfth of an OFDM symbol of useful data in the 2k mode and 1/48 of an OFDM symbol in the 8k mode. These two modes are explained below.

The symbol interleaved maps the 2, 4 or 6-bit words 0 onto 1512 or 6048 active carriers, depending on whether the 2k or 8k mode is in use. The symbol interleaver acts so as to shuffle groups of 2, 4 or 6 bits around within the symbol. This it does by writing the symbol into memory and reading out the groups of 2, 4 or 6 bits in a 15 different and permuted order compared with the order in which they were written into the memory.

Finally the groups of 2, 4 or 6 bits are applied to a mapper 46 which quadrature modulates the bits according to QPSK, 16-QAM or 64-QAM modulation, depending on the mode 20 in use. (QPSK may also be represented as 4-QAM.) The constellations are shown in Figure 9 of the standard. It will be appreciated that this requires 1, 2 or 3 bits on the X axis and 1, 2 or 3 bits on the Y axis. Thus while reference has been made to 2, 4 or 6 bits in the shuffling 25 process, in fact the shuffling is applied to 1, 2 or 3 bits in the real part and 1, 2 or 3 bits in the imaginary part. So-called hierarchical transmission can be used in which a high-priority stream and a low-priority stream are 30 separately modulated.

The signal is now organized into frames in a frame adapter 48 and applied to an OFDM (orthogonal frequency-division multiplexer) coder 50. Each frame consists of 68 OFDM symbols. Each symbol is constituted 35 by 1705 carriers in 2k mode or 6817 carriers in 8k mode.

Using the 2k mode as an example, instead of transmitting 1705 bits sequentially on a single carrier, they are

( - 10 assembled and transmitted simultaneously on 1705 carriers.

This means that each bit can be transmitted for much longer, which, together with the use of a guard interval, avoids the effect of multipath interference and, at least 5 in 8k mode, allows the creation of a singlefrequency network. The duration of each symbol, the symbol period, is made up of an active or useful symbol period, and the guard interval. The spacing between adjacent carriers is lo the reciprocal of the active symbol period, thus satisfying the condition for orthogonality between the carriers. The guard interval is a predefined fraction of the active symbol period, and contains a cyclic continuation of the active symbol.

15 The predefined fractions are 1/4, 1/8, l/16 and 1/32.

The total symbol duration is of the order of 250 us for the 2k mode and 1 ms for the 8k mode.

The frame adapter 48 also operates to insert pilots into the signal. Some of the pilots can be used at the so receiver to determine reference amplitudes and phases for the received signals. The pilots include scattered pilots scattered amongst the 1705 or 6817 transmitted carriers, as well as continual fixed pilots. The pilots are modulated in accordance with a PRBS sequence. Some other :s carriers are used to signal parameters indicating the channel coding and modulation schemes that are being used, to provide synchronization, and so on.

The OFDM coder 50 consists essentially of an inverse fast Fourier transform (FFT) circuit 52, and a guard 30 interval inserter circuit 54. The construction of the OFDM coder will be known to those skilled in the art.

Reference is made to British Broadcasting Corporation Research and Development Report BBC RD 1396/8, P. Shelswell, "The COFDM Modulation System" with regard to 35 OFDM generally, and to a paper by Stott, J.H., 1997, "Explaining some of the Magic of COFDM", Proceedings of the 20th International Symposium, Montreux 1997, pages 341

( - 11 -

to 350, which describes how the various components of the forward error corrector co-operate with the OFDM coder to provide a very advantageous coding system.

Finally, the signal is applied to a digital to 5 analogue converter 56 and thence to a transmitter 'front end' 58, including the transmitter power amplifier, and is radiated at radio frequency from an antenna 60.

DVB-T Receiver - The receiver construction is not specified by the standard ETS 300 744, but typically includes components corresponding to those in the transmitter but in reverse order. A generalized DVE-T receiver 100 is illustrated in simplified form in the block diagram of Figure 3, with some elements which are not of particular relevance to the 15 present invention omitted. Reference may also be made to European Patent Application EP-A-0 877 526 for a description of an integrated circuit forming the main

component of a receiver.

In the receiver 100 an analogue RF signal is received 20 by an antenna 102 and applied to a tuner or down-converter 104, constituting the receiver front end, where it is reduced to baseband. The signal from the tuner is applied to an analogue-to-digital converter 106, the output of which forms the input to an OFDM decoder 108. The main 25 constituent of the OFDM decoder is a fast Fourier transform (FFT) circuit, to which the FFT in the transmitter is the inverse. The FFT receives the many-carrier transmitted signal with one bit per symbol period on each carrier and converts this back into a 30 single signal with many bits per symbol period. The existence of the guard interval, coupled with the relatively low symbol rate compared with the total bit rate being transmitted, renders the decoder highly resistant to multipath distortion or interference.

35 Appropriate synchronization is provided, as is well-known to those skilled in the art. In particular, a

- 12 synchronising circuit will receive inputs from the ADO 106 and the FFT 108, and will provide outputs to the FFT and, for automatic frequency control, to the tuner 104.

The output of the OFDM decoder 108 is then applied to 5 a channel equalizer 110. This estimates the channel frequency response, then divides the input signal by the estimated response, to output an equalised constellation.

Now the signal is applied to a circuit 112 which combines the functions of measurement of channel state, to and demodulation or demapping of the quadrature modulated constellations. The demodulation converts the signal back from QPSK, 16-QAM, or 64-QAM to a simple data stream, by selecting the nominal constellation points which are nearest to the actual constellation points received; these 15 may have suffered some distortion in the transmission channel. At the same time the circuit 112 estimates the likelihood or level of certainty that the decoded constellation points do in fact represent the points they have been interpreted as. As a result a likelihood or 20 confidence value is assigned to each of the decoded bits.

The output of the metric assignment and demapping circuit 112 is now applied to an error corrector block 120 which makes use of the redundancy which was introduced in the forward error corrector 30 in the transmitter. The 25 error corrector block 120 comprises: an inner deinterleaver 122, an inner decoder 124, in the form of a soft-decision Viterbi decoder, an outer deinterleaver 126, and 30 an outer decoder 128.

The inner deinterleaver 122 provides symbol-based deinterleaving which simply reverses that which was introduced in the inner interleaved 38 in the transmitter.

This tends to spread bursts of errors so that they are 35 better corrected by the Viterbi decoder 124. The inner deinterleaver first shuffles the groups of 2, 4 or 6 real and imaginary bits within a symbol (that is, 1, 2 or 3 of

- 13 each), and then provides bit-wise deinterleaving on a block-based basis. The bit deinterleaving is applied separately to the 2, 9 or 6 substreams.

Now the signal is applied to the Viterbi decoder 124.

The Viterbi decoder acts as a decoder for the coding introduced by the punctured convolutional coder 36 at the transmitter. The puncturing (when used) has caused the elimination of certain of the transmitted bits, and these are replaced by codes indicating a mid-value between zero lo and one at the input to the Viterbi decoder. This will be done by giving the bit a minimum likelihood value. If there is no minimum likelihood code exactly between zero and one, then the added bits are alternately given the minimum values for zero and for one. The Viterbi decoder makes use of the soft-decision inputs, that is inputs which represent a likelihood of a zero or of a one, and uses them together with historical information to determine whether the input to the convolutional encoder is more likely to have been a zero or a one.

So The signal from the Viterbi decoder is now applied to the outer deinterleaver 126 which is a convolutional deinterleaver operating bytewise within each packet. The deinterleaver 126 reverses the operation of the outer interleaves 34 at the transmitter. Again this serves to 2s spread any burst errors so that the outer coder 128 can better cope with them.

The outer decoder 128 is a Reed-Solomon decoder, itself well-known, which generates 188-byte packets from the 204-byte packets received. Up to eight random errors 30 per packet can be corrected.

From the Reed-Solomon outer decoder 128 which forms the final element of the error corrector block 120, the signal is applied to an energy dispersal removal stage 130. This receives a pseudo-random binary sequence at an as input 132 and uses this to reverse the action of the energy dispersal randomiser 26 at the transmitter. From here the signal passes to an MPEG-2 transport stream

( - 14 demultiplexer 134. A given programme is applied to an MPEG-2 decoder 136; other programmer are separated out as at 138. The MPEG-2 decoder 136 separately decodes the video, audio and data to provide elementary streams at an 5 output 140 corresponding to those at the inputs 12 on Figure 1.

Channel State Information in DVB-T Receivers We have previously proposed using channel state information in a DVB-T receiver in the manner described in our European Patent Application EP 0 991 239A. That application describes a system in which a measurement of channel state is obtained for each carrier of a COFDM signal and is used to vary the discrimination levels of the soft-decision quantiser which feeds the Viterbi 15 decoder. The channel state information is obtained from, say, a 64-QAM signal by quantising the input with a hard-decision quantifier and obtaining the modulus of the difference between the quantised and unquantised signal.

The channel state information is applied through a so symbol-delay recursive filter to a control circuit. The output of the control circuit directly controls the soft-decision quantisers by varying their discrimination levels which they use in determining the likelihood or confidence values.

Is In practice the received 64-QAM constellation values do not always fall exactly on the nominal constellation points, but because of noise, distortion and interference, form a cloud of values in the vicinity of each point. As described below, channel state information (CSI) can be 30 measured by determining how much the received values depart, on average, from the nominal positions.

Figure 4 shows the system of our application EP 0 991 239A. The part corresponding on Figure 3 to the channel equaliser 110, through the metric assignment and 35 demapping circuit 112 and the inner deinterleaver 122 to the Viterbi decoder 124 is shown. The metric assignment

( - 15 and Remapping circuit 112 is shown in more detail. In the circuit shown in Figure 4, an 11-bit input signal is received at an input 222 from the output of the channel equaliser 110 and is applied to three metric s characteristic generating circuits 224a, 224b, and 224c, which are referred to respectively as the bit 1 metric circuit, the bit 2 metric circuit, and the bit 3 metric circuit. The 9-bit output of each circuit 224 is connected to a respective adjustable quantiser 226, which lo provides a 3-bit soft decision output. The three 3-bit outputs are applied from the metric assignment and demapping circuit 112 via the inner deinterleaver 122 to a multiplexer (MPXR) 228 for the 3-bit soft decisions, which produces two 3-bit outputs to inputs X and Y respectively 15 of the Viterbi decoder 124. The Viterbi decoder 124 provides an output 232.

Thus, before the 3-bit quantisation in the quantisers 226, the input signal received from the channel equaliser 110 is processed in the metric circuits 224 by a set of So metric characteristics, which provide a measure of how far and in what sense the signal departs from the decision level for each bit.

The resulting signals are individually quantised in quantisers 226 to produce three-bit soft decisions, that 2s is, a confidence value is associated with each decision.

The confidence values are quantised relative to confidence value discrimination levels. After deinterleaving in the inner deinterleaver 122, the soft decisions are then multiplexed in multiplexer 228 appropriately for the 30 convolutional code being used for presentation to the X and Y inputs of the Viterbi decoder 124.

Figure 4 shows a circuit 240 which can be used for channel state measurement. The circuit 240 is also connected to input 222 for receiving the input signal, 35 which comprises time-multiplexed real and imaginary (in-phase and out-of-phase) carrier components for successive OFDM carriers. That is, the real and imaginary

- 16 components for each carrier are multiplexed, and the resultant multiplexes for the carriers are themselves multiplexed. During any one symbol period all the carriers are processed. The input signal is applied to a 'hard' 5 quantiser 249 and to the non-inverting input of a subtracter 246. The output of the quantiser 244 is connected to the inverting or subtractive input of the subtracter 246. The output of the subtracter is then connected through a rectifier or modulus circuit 248, lo which inverts negative values, to one input of a two-input AND-gate 250. The other input of the AND-gate 250 receives a flag indicating whether the carrier is a pilot of the DVB-T system, as referred to above, or rather is a data carrier carrying information. Operation is 15 suppressed for the pilot carriers. The output of the AND-gate 250 is applied both directly and through a delay 252 to an adding circuit 254, the output 256 of which forms the output of the channel state measurement circuit. The delay 252 demultiplexes the real and imaginary values so for each

carrier, and the adder 254 adds the real and imaginary parts of the signal value. The circuit 240 produces an output during a particular time period for each of the carriers the condition of which is to be monitored. 25 The method used in the equipment shown in circuit 240 to calculate the channel state consists, for each carrier, of first determining in the quantiser 244 the nearest nominal level for each component of the complex input signal, and then subtracting the thus-determined nearest 30 nominal level from the component of the complex input signal itself. This gives a measure of the deviation from the correct value, as introduced by the transmission channel. As noted, at this point the signal for each carrier is carried for convenience as time-multiplexed 3s real and imaginary components. The process of subtracting the nearest nominal level is simplified considerably by arranging that the nominal constellation positions are

- 17 aligned with transitions of the major bits of the binary-encoded words used to represent the real and imaginary components. The resulting difference signals from the subtracter 246 are rectified in the rectifier 248 5 to produce positive-going signals, and the contributions of the pilot carriers of the DVB-T system are suppressed by the AND-gate 250, as noted above. The real and imaginary values for each carrier are then demultiplexed by the delay 252 and are added together by the adder 2S4, lo to provide an approximation to the error magnitude for that carrier.

While the exact length of the error vector could be measured by evaluating the root-sum-of-squares of the real and imaginary errors, this is unnecessarily accurate and 5 using the sum of the real and imaginary errors provides a useful reduction in complexity.

Figure 4 also shows a symbol-recursive filter 260 for averaging the carrier error values as determined by the circuit 240. The filter 260 is connected to the output of 20 the circuit 240 and receives at an input 262 the measured channel state error values. In the example of the filter 260 shown, these values are applied to a symbol delay filter 264. The measured channel state values are filtered with a recursive low-pass filter incorporating a z5 full symbol period delay 272, a subtracter 266, attenuator 268, and adder 270, so that successive error values from each carrier position are averaged together. The signal is then clipped in circuit 274 to remove any negative values (caused by quantising errors) and to limit the 30 range of positive values, before being passed to the quantiser selection process. Our European Patent Application 0 991 239A describes the detailed construction of this example of the symbolrecursive filter 260 (see Figure 6 of that application).

35 The channel state information could be used simply to reject unusable carriers. However, performance can be improved by modifying the softdecision values according

- 18 to the level of impairment signalled by the channel state measurement. A control law can be developed by a combination of theory and practical optimization to relate the modified soft decisions to the channel state values.

5 This is illustrated in Figure 4, which shows a circuit 280 which implements a control law. The circuit 280 has an input 282 for receiving the output of circuit 260 which is applied to a logarithm circuit 284 which takes the logarithm of the input value to base two. The lo output of the circuit 284 is applied through an inverter 286 to the non- inverting input of a subtracter 288. The inverting input of the subtracter receives a correction signal which is dependent upon the particular type of modulation system being used. The output of the s subtracter 288 is multiplied by two in a multiplier 290, the output of which is applied to one input of a two-input adder 292 which also receives an offset adjustment. The output of the adder 292 is applied to a limiter or clipper 294, the output 296 of which constitutes the output of the 20 control law circuit 280.

The circuit 280 operates by first taking the base-two logarithm of the channel state signal in the logarithm circuit 284. Next, the log signal is bit-wise inverted by inverted 286, so that a large value now represents a 25 good-quality signal. A shift is then subtracted in subtracter 288 to take account of the different channel state sensitivities of different modulation systems. This occurs because of the differing spacing between points in the constellation for systems other than 64-QAM. Because 30 of the logarithm, the shift gives the effect of dividing the channel state measurement by a factor. The resulting signal is multiplied by two in multiplier 290 to give the effect of using the square of the channel state measurement. This converts the voltage carrier-to-noise 35 measurement into a power carrier-to-noise measurement. An adjustable offset, optimised empirically by measurement, is then added in adder 292 and the result clipped in

- 15 -

clipper 294 to take account of the range of control available for modifying the soft decisions.

The use of the logarithm circuit 284, which, notably, is not followed by any antilogarithm circuit, might be 5 thought to distort the processing, but in fact is found to lead to more efficient processing. The logarithm operation does not need to be conducted with high accuracy; a very lowgrade logarithm using only one binary digit for the mantissa can be employed.

JO The effective discrimination levels for the soft decisions in the Viterbi decoder are altered according to the measured channel state. That is to say, the hard decisions are fixed, and depend solely on which of a plurality of possible values is nearest to the received value. The confidence value associated with any decision and which makes it a soft decision is also quantized, and this quantisation is altered in dependence upon the channel state. The metric circuits 224 make the hard decisions, and the adjustable quantisers 226 do not alter JO those decisions but quantise and modulate the confidence values. The quantiser levels used to produce the soft decisions are altered in dependence upon the channel state. The circuit illustrated in Figure thus shows how 2s the circuits 240, 260, 280 are used to provide a system in which the channel state information is used in making the soft decisions in the decoder. The output of the circuit 280 is applied to control the adjustable quantisers 226 which produce respective soft decision outputs. These are 30 then applied to the inner deinterleaver 122, multiplexer 228, and Viterbi decoder 124.

The quantisers 226 may provide ten different quantising laws selected by the O to 9 states of the 4-bit quantiser control signal from circuit 280, with state 9 3s representing the finest quantiser to be used for the highest quality signals. The quantiser laws are produced approximately at gain steps of i2, so that the upper three

! - so -

bits of the control signal select five levels of bit shift, and clip the signals at the extremes of each range to produce a 5-bit signal. The soft decision value is then produced using the levels 12, 8, 4, 0, -4, -8 and 12 s for unity gain values, or levels 9, 6, 3, 0, -3, -6 and -9 to approximate for 1/2 gain values. Thus for a carrier signal of very low quality, which is either originally small (and therefore noisy) or obscured by interference, the quantisation levels are spread over a wide range so lo that the standardized signal levels will tend to fall in the 011 and 100 states, indicating low confidence in the values from this carrier to the Viterbi decoder.

In an alternative arrangement (not described in our aforementioned European Patent Application) the quantisers 15 226 provide fourteen different quantising laws, selected by the 12 to 15 and 0 to 9 states of the control signal 296. State 12 represents the coarsest quantiser to be used for the poorest quality signals, and state 9 represents the finest quantiser to be used for the highest 20 quality signals. In this case the operation of the clipper 294 in the control law circuit 280 is now to clip to the range -4 to 9 in two's complement. Then by discarding the sign bit, the unsigned numbers 12 to 15 and O to 9 are successively obtained. There are now seven 25 levels of bit shift.

( - 21 Preferred Embodiment of the Invention The various features of the preferred embodiment of the invention will now be described with reference to Figures 5 to 8 of the drawings.

5 Improved Channel State Indication In accordance with one aspect of the preferred embodiment we propose to improve the measure of channel state indication relative to that of Figure 9 so as to identify the degree of corruption of each OFDM symbol.

lo As was described with reference to Figure 4, the channel state indication is obtained by determining the distance from the received QAM or QPSK point to the nearest constellation point, and then in filter 260 averaging in time, that is over several symbols on one carrier. We now Is propose, instead of averaging in time, to average separately for each symbol along the frequency axis, that is for all the carriers in one symbol (or at least part of a symbol, the determination period).

This is illustrated in Figure 5 which shows how 20 Figure 4 is altered in accordance with this proposal.

Much of the circuit of Figure 5 is the same as Figure 4 and is identified by the same reference numerals, and is not therefore described again. The symbol-recursive filter 260, and the control law circuit 280 are not shown 25 in detail, save that the limiter or clipper 294 is shown separately from the rest of the control law circuit 280.

The output of the limiter or clipper 294 controls the discrimination values in the quantifiers, as before.

In the improved channel state measurement, it is 30 necessary to provide a delay of one symbol so that it is possible to make the measurement on a given symbol and to use the measurement in assigning metrics from that same symbol. To achieve this a one-symbol delay 300 is connected between the channel equalizer 110 and the metric 35 assignment and demapping circuit 112. The bit metric circuits 224 are connected to the output of the one-symbol

( - 22 -

delay 300 whereas the channel state measurement circuit 240 is connected at 301 to the output of the channel equaliser prior to the one-symbol delay 300.

The output of the channel state measurement circuit 5 240 is applied both to the symbol-recursive filter 260 and to a circuit 302 which sums the signal for all the carriers over a one-symbol period. The output of this accumulator 302 is then applied to a control law circuit 310, which comprises a logarithm circuit 312 which takes lo the logarithm of its input value to base two. The output of the circuit 312 is applied to a multiplier 314 which multiplies by two. This converts the voltage measurement into a power measurement. The output of the multiplier 314 is applied both through an averager 316 to the 15 non-inverting input of a subtracter 318 and directly to the inverting input of the subtracter.

The construction of the averager 316 is shown in Figure 6. The input from multiplier 314 is applied to the non-inverting input of a subtracter 360, the output of 20 which is applied to a divider (or multiplier) 362 which divides by 4 or 8, i.e. multiplies by or /. The output of the divider 362 is applied to one input of an adder 364, the output of which constitutes the output of the averager 316 and is supplied to the subtracter 318. The 25 output of the adder 364 is also applied to the input of a clocked symbol delay 366 which can provide a clocked delay of 1, 4 or 16 elements. The output of the symbol delay 366 is applied both to the other input of the adder 364 and to the inverting input of the subtracter 360.

30 Thus the averager 316 forms a decaying average of recent symbol-bysymbol measurements of channel state.

The decay time constant is either 4 or 8 symbols, set by the constant factor of or,/e in the element 362. As an alternative to the decaying average filter shown in Figure 3s 6, a running average filter could alternatively be used.

The averager 316 is clocked at a clock rate of 1, 9 or 16 times per symbol received at an input 368. This

( - 23 clock signal also resets (or clears) accumulator 302.

Assuming one clock pulse per symbol and one element in the delay 366, the accumulator 302 and averager 316 work together to average the channel state. Accumulator 302 5 averages over one symbol, or part of one symbol. Recent ones of these averages are then averaged in averager 316.

In 2k mode, the averaging in accumulator 302 can be over each quarter symbol, with 4 clock pulses per symbol and 4 elements in the delay. In 8k mode, the averaging in lo accumulator 302 can be over each one-sixteenth of a symbol, with 16 clock pulses per symbol and 16 elements in the delay. Other sub-divisions would also be possible.

If one of the latter two modes is adopted, the symbol delay 300 needs to become a one-quarter symbol delay in 2k Is mode or a one-sixteenth symbol delay in 8k mode. It will be appreciated that one-quarter of a 2k symbol and one-sixteenth of an 8k symbol represent the same amount of physical storage, and represent in each case a substantial saving in the storage requirement relative to a full 20 symbol. This saves memory in the compensating delay 300, while still achieving the desired effect of comparing the current symbol with the average of previous ones. A given one quarter or one-sixteenth of a symbol is compared in subtracter 318 with the corresponding fraction in previous 25 symbols. The timing is arranged such that the accumulator 302, averager 316 and subtracter 318 operate on the same part of a symbol at the same time, so that like is averaged with like in averager 316 and is then compared with like in subtracter 318.

3c The delay 300 requires 30,240 bits (3,780 bytes) of extra memory for the 2k mode and four times more than that for the 8k mode. In practice, averaging over a few hundred carriers (in the 2k mode) is likely to give sufficient noise reduction, and it is possible therefore as to sum for only one quarter of the available carriers.

This can give incorrect results if the channel has a non-uniform or tilted frequency response, because the

( - 24 average over a few hundred carriers might not be representative of the symbol as a whole.

If the delay 300 is not a whole symbol delay but rather is a fraction of a symbol delay, then the channel 5 state measurement circuit 240 needs an equal compensating delay. There are several ways in which this can be done, including the following: (i) include two channel state measurement blocks 240, with their inputs connected one to each side of the JO delay 300; (ii) insert the required delay after the logarithm circuit 284 (see Figure 4) in the control law circuit 280; (iii) provide a second access point to the full symbol 15 delay memory 272 (see Figure 4) in the symbolrecursive filter 260, to provide the required delay, and make that the output of the sybol-delay filter 264.

Reverting to the description of Figure 5, the output

of the subtracter 318 is then combined with the output of 20 the main control law circuit 280 (taken prior to the clipper 294) in an adder 320. The output of the adder 320 is then applied through the clipper 294 to control the discrimination levels of the quantisers 226. The output of the subtracter 318 is also supplied as a channel state 25 indication for use in connection with the outer decoder 128, as described below.

The control law circuit 310 operates to take the logarithm of the measurement, as in the control law circuit 280,and convert the voltage measurement to a power 30 measurement in the multiplier 319. Then the difference is taken in the subtracter 318 between the resultant measurement for the current symbol and the average of recent symbols. This difference is then added in the adder 320 to the carrier-by-carrier channel state

( - 25 indication provided by the circuits 240, 260 and 280.

Normally the result of the symbol-by-symbol measurement is similar from symbol to symbol so that the output of subtracter 31B is near to zero. Under these conditions 5 the symbol-by-symbol measurement has little effect on the control signal fed to the adjustable quantisers 226.

However, if a symbol is affected by impulsive interference, the measurement is higher than on other symbols, and the output of the subtracter 318 is strongly lo negative. This reduces the control signal fed to the adjustable quantisers 226 and hence reduces the degree of confidence of the soft decisions. In this way the confidence information includes information about impulsive interference.

5 Impulsive interference affects isolated symbols and so is not reflected in the output of the known measurement circuit of Figure 4 because the circuit has to include a filter like the symbol-recursive filter 260, which filters out changes occurring on isolated symbols. The improved 20 information provided by the arrangement shown in Figure 5 and described above improves the effectiveness of the Viterbi decoder in correcting errors, namely in this instance, errors arising from impulsive interference. To enable the improved channel state information to give a 25 benefit, deeper inner interleaving should also preferably be used with a depth of at least four symbols for the DVB-T option 64-QAM, rate 2/3. An example of deeper inner interleaving is described below.

Errors and erasures decoding in Reed-Solomon decoder 30 In accordance with another aspect of the present embodiment we propose the use of the errors and erasures feature of the Reed-Solomon decoder. This requires a slightly more complex decoder, but it increases the number of errors that can be corrected. An erasure is a byte 35 (8-bit word) which is known to contain one or more bit-errors and is flagged as such to the Reed-Solomon (RS)

- 26 decoder. The RS decoder can correct twice as many erasures as it can errors, where an error is a byte which contains one or more bit-errors not signalled to the RS decoder. In fact the error correction capacity of the RS 5 code per block or packet is: 2 r + e t where: r is the number of errors e is the number of erasures t is the number of check bytes.

0 Thus, a mixture of errors and erasures can also be corrected. Clearly, to do erasures decoding it is necessary to have 'erasures' information. Two ways of providing the erasures information will now be described.

Erasures sianallina from channel state As described above with reference to Figure 5, the channel state measurement circuit 240, the accumulator 302, and the control law circuit 310 provide a channel state indication for each received symbol on the OFDM 20 multiplex. The output of the subtracter 318 is sensitive to the occurrence of impulsive interference and this output can therefore be used to provide the erasures signalling to the outer or Reed-Solomon decoder 128. To this end the output of subtracter 318 is connected through 25 a combining or selecting circuit 322 to an input of the outer deinterleaver 126, the output of which is applied to the Reed-Solomon decoder 128. The construction of the ReedSolomon decoder is itself well-known and is not further described here; reference may be made to 30 "Error-Correcting Codes", Peterson W.W. and Weldon E.J., 2nd edition, MIT Press, Cambridge, Mass. U.S.A., 1972, see Chapter 9 which describes a Reed-Solomon decoder which does erasures decoding.

The erasures information applied to the outer 35 deinterleaver 126 can be taken from either of two sources, namely from the Viterbi decoder 124 (as described below)

- 27 or from the control law circuit 310, that is from subtracter 318. The latter is applied through a slicer (or threshold circuit) 370 which gives a one-bit signal indicating 'normal' or 'erased' and then through a delay 5 372 which allows for the delay of the inner deinterleaver 122 and the Viterbi decoder 124 and the delay 300. The output of delay 372 and the erasures output of the Viterbi decoder are applied to the combining or selecting circuit 322. Which of its inputs is used depends on the JO parameters of the COFDM system. For DVB-T, the erasures output of the Viterbi decoder is normally preferred, and in a dedicated receiver elements 322, 370 and 372 are replaced by a straight connection from the erasures output of the Viterbi decoder 124 to the outer deinterleaver 126.

However, if the combination of outer interleaving depth and Reed-Solomon code redundancy is strong enough, the channel state indication may be better. The best arrangement is determined empirically for any given system. 20 In a modification, if the erasures information is taken solely from the channel state indication, the delay in the inner deinterleaver is one symbol, and the symbol by-symbol channel state indication is not used in the quantiser control (adder 320 is omitted and the output of 25 subtracter 318 is applied solely to the slicer 370), then the delay 300 can be omitted, and the delay 372 consequently reduced.

In any event, each erasure flag is associated with a specific byte, and this association should be retained 30 through the outer deinterleaving process. Thus the erasure flags are inputted to, and pass through, the outer deinterleaver 126, and the deinterleaver needs to store 9 bits rather than 8 for each byte, the gth bit holding the associated erasure flag. The erasure flags can then be 35 used by the Reed-Solomon decoder 128.

- 28 Erasures sianallinq from Viterbi decoder As noted above, in addition to, or instead of, the signalling from the channel state measurement as just described, we have appreciated that the erasures 5 signalling can advantageously be obtained from the Viterbi decoder. This is illustrated in the block schematic diagram of Figure 7.

In Figure 7, the Viterbi decoder 124 is seen to receive from the multiplexer 228 a signal which is 10 separated or distributed into the X or G1 signal and the Y or G2 signal, corresponding to the similarly named signals in the inner coder at the transmitter described above and illustrated in Figure 2. The separation or distribution may take place in the multiplexer 228 as shown in Figure 5 15 or in a separate distributor 330 as shown in Figure 7.

The G1 and G2 signals are applied to the main Viterbi decoding engine 332, which is of a type known to those skilled in the art and is not therefore further described here. Reference may be made to "Error- Correction Coding 20 for Digital Communications", Clark G.C. and Cain J.B. , Plenum, New York, 1981, Chapter 6, for further details.

It is common in a Viterbi decoder to re-encode the decoded output of the decoding engine and to compare it with a suitably delayed version of the incoming hard decisions, 25 to give an estimate of the raw bit error rate (BER). This is achieved by a convolutional coder 334 connected to the output of the decoding engine 332, and two exclusive-OR gates 336,338. The first exclusive-OR gate 336 compares the G: outputs of the distributor 330 and the coder 334 30 and the second exclusive-OR gate 338 compares the G2 outputs of the distributor 330 and the coder 334. The distributor 330 also produces a node synchronization signal, which indicates the starting-time of each repeat of the puncturing pattern. This controls a puncturing 35 pattern generator 380 which is arranged to produce the pattern correctly-phased in relation to the output of the convolutional coder 334. These signals are fed to AND

( - 29 gates 382, 384 which blank out any error indications which may appear on punctured bits. The punctured bits were not actually transmitted and so do not give rise to errors to be counted; the GO and G2 signal (as the case may be) does 5 not carry valid information during a punctured convolutional code symbol. The errors in G. and G2 are counted in an error rate counter 340 which gives a measure of the BER, to give a long-term value for the BER.

Compensating delays 342,344 are provided for the Gl lo and G2 signals respectively to allow for the delay caused in the decoding engine 332, and a compensating delay 346 is connected to the output of the decoding engine 332 to allow for the delay caused in the convolutional coder 334 and a special error rate counter 350 (see below). The decoded data output from the delay 346 is applied to the outer deinterleaver 126, shown at the bottom of Figure 7.

The additional or special error rate counter 350 receives the outputs of the gates 382,384. The error rate counter 350 determines the error rate over a short stretch 20 of the decoded data, for example three bytes or 36 coded bits. A byte' e-worth of data outside the convolutional code (i. e. before the convolutional encoder or after the Viterbi decoder) corresponds to 12 bits'-worth of data inside the convolutional code, at rate 2/3 (i.e after the 25 convolutional encoder and before the Viterbi decoder).

The ratio of 8 to 12 is 2/3. The raw BER is necessarily counted on coded bits whilst the erasures information obtained from it is being attached to the decoded bits, after they have been grouped into bytes. Thus three bytes 30 here contain 36 bits. If the number of errors in the 36 bits is greater than a predetermined value, for example 9, then the middle of the three bytes is marked as an erasure. Thus the three-byte windows overlap so that the test is made for each byte. The fact that a byte is marked 35 as an erasure is signalled to the erasures input of the Reed-Solomon decoder, through the combining/selecting circuit 322 of Figure S if appropriate.

- 30 The window defining the short stretch of data can be of length other than three bytes. It should be centred as -

nearly as possible on the byte which is being tested but need not be a whole odd number of bytes or even a whole s number of bytes at all. The optimum number of bytes in the window is best determined empirically, as it is dependent upon factors such as the code rate. Preferably the window will be chosen so that (a) the probability of falsely detecting that the Viterbi decoder is failing when it is to in fact succeeding, and (b) the probability of falsely detecting that it is succeeding when it is in fact failing, are both small. 'Small' might here mean less than 1 in 1000. Typically the window may be in the range of 2 to 9 bytes or preferably 2 to 5 bytes.

15 Appropriate synchronizing to the bytes of the decoded data is achieved by a synchronization circuit 352. -

It will be appreciated that at code rates 3/4, 5/6 and 7/8, there is not a whole number of cycles of the puncturing pattern in a byte. Thus, different bytes have JO different numbers of coded bits corresponding to them. For i example, at rate 3/4, bytes may correspond to either 10 or 11 coded bits. This means that the special error rate counter 350 needs to receive information about the phase of the puncturing pattern. This can be derived either from 25 the node synchronizing signal from the distributor 330, or, perhaps preferably, from the pattern itself from the puncturing pattern generator 380. For simplicity, neither of these connections is shown on Figure 7. Then the counter 350 can set its counting period to be a given 30 number of coded bits, and the number of errors is counted over this counting period.

The use of erasures signalling obtained from the Viterbi decoder in this way improves the operation of the Reed-Solomon decoder and hence of the receiver as a whole -

3s in the presence of impulsive interference, and in the presence of any other type of channel impairment. The

l - 31 operation of the special error rate counter over a small number of bytes makes this particularly advantageous.

Improved Inner Interleaving/Deinterleavino As described above, the inner interleaved 3B at the 5 transmitter effects a two-stage interleaving operation, namely bit-wise interleaving followed by symbol interleaving. They are described in section 4.3 of the DVB-T standard and illustrated in Figures 7 and 8 thereof. We have appreciated that it would be desirable to increase lo the depth of

the inner interleaving such as to bring the Viterbi decoder into play at greater received error rates, and that it is not necessary to confine the symbol interleaving to a single symbol. The Viterbi decoder used as the inner coder is better suited to dealing with high 15 error rates than the Reed-Solomon decoder.

The symbol interleaving has increased depth so that the interleaving is now done over a block of size greater than one symbol and preferably equal to at least 4 symbols. The bit-wise interleaving stage is unchanged.

JO The symbol interleaving stage operates by writing groups of 2, A or 6 bits for the real and imaginary components of the signal into memory and reading them from memory in a different, permuted order. Corresponding alteration is made to the inner deinterleaver 122 at the receiver.

25 Figure 8 is a block diagram of an inner interleaved 400 with greater depth. The deinterleaver is essentially identical, see below. It uses a four-symbol memory 402 instead of a one-symbol memory. The memory 402 is addressed by the output of a controlled selector switch 30 404. The two inputs which the switch selects from are an address generator 406 for generating ascending sequences of length of four symbols and an address generator 408 for generating permuted sequences of length of four symbols.

A control circuit 410 controls the switch and also resets 35 the two address generators. The timing signals provided by

- 32 the control circuit 410 are clearly indicated on the figure. Increasing the block size by a factor of four will increase the memory requirement by a factor of four also.

For the 2k DVB-T mode, the amount of memory needed in the inner deinterleaver 122 at the receiver will typically increase from 36,288 bits (4,536 bytes) to 145,152 bits (18,144 bytes). For the 8k mode the figures need to be four times as large, so the memory will increase from 10 145,152 bits (18,144 bytes) to 580,608 bits (72,576 bytes). However, some existing demodulators are dual-mode and so already have 145,152 bits available for use when in the 8k mode. This means that they already have sufficient memory available for interleaving with 9-symbol blocks when in the 2k mode.

The main difference between the interleaved at the transmitter and the deinterleaver at the receiver is that the sense of the control (switching between ascending and permuted address sequences) is reversed. The other 20 difference is that the interleaves stores 1-bit data, the convolutionally coded bits, whilst the deinterleaver stores 3- or 4-bit data, the soft decisions about the coded bits. The changes to Section 4.3. 4.2 of the Standard follow in a straightforward manner; everything 25 becomes four times as long. Thus in 2k mode there are now 48 groups of words from the bit interleaved, and in 8k mode, 192. NmaX becomes 6098 in 2k mode and 24192 in 8k mode. MmaX becomes 8192 in 2k mode and 32768 in 8k mode.

Where the Standard says "YH(q) = Y'q for even symbols" and 30 "yq = Y'Hq, for odd symbols" (which specifies the phasing of the control), it needs to say "YH[q) = Y'q for the first group of four symbols in a super-frame and alternate groups of four symbols after that" and "Yq = Y'H{q} for the second group of four symbols in a super-frame and 35 alternate groups of four symbols after that". The details of the longer permuted sequence generators can be defined by new versions of Tables 3a and 3b and Figures 8a and fib.

! - 33 The interleaving depth does not have to be four symbols as described, though use of at least four symbols is desirable, at least in the 2K mode of DVB-T with a code rate of 2/3 (as used in the United Kingdom). This reduces s the BER from, say, 1 in 6 (as with 64-QAM) to less than 1 in 20, so that the Viterbi decoder can now succeed. The maximum useful interleaving depth will be typically in the range 0.1 to 0. 5 seconds. This corresponds to around 1000 to 2000 symbols in the 2K mode and 250 to 500 symbols in lo the 8K mode. The upper limit will be set by the practically of including a large amount of memory, how much delay can be tolerated, and where there is little further improvement in reception. The optimum value is best determined empirically.

t5 The advantage of using the extra memory is that the system has greater ruggedness, in that impulsive interference of greater duration will be susceptible to correction by the Viterbi decoder. To implement this proposal modifications are however required both at the so transmitter and the receiver, thus requiring an amendment to the standard.

This feature of improved interleaving with greater depth may be applicable to systems other than DVB-T which use many-carrier transmission with concatenated codes, for z5 example the Asymmetric Digital Subscriber Line (ADSL) system for telephone line communication and Digital Radio Mondiale (DRM).

Many modifications may be made to the system described and illustrated by way of example. The many 30 features of the system may be used independently of each other or in combinations other than those specifically disclosed. Whereas the description has been given in terms

of hardware components, the system may in large part be implemented in software, in which case the Figures can be as regarded as being in the nature of flow chart diagrams.

Claims

- 34 CLIMS 1. Apparatus for determining values encoded by a received

signal, comprising: an input for receiving a received many-carrier 5 signal, the received many-carrier signal comprising many data carriers representing a sequence of values in successive symbol periods; a ReedSolomon decoder coupled to the input for decoding values from the received many-carrier signal, the lo Reed-Solomon decoder having an erasures input and providing for erasures decoding; channel state indication determining means coupled to the input for determining a composite channel state indication for the carriers for each symbol period or a 5 part thereof; and coupling means coupling the output of the channel state indication determining means and the erasures input of the Reed-Solomon decoder for providing to the Reed Solomon decoder an erasures signal derived from the so channel state indication determining means.
2. Apparatus according to claim 1, in which the coupling means comprises a slicer for providing two output conditions indicative of 'normal' or 'erased' respectively. is
3. Apparatus according to claim 1 or 2, further comprising a deinterleaver coupled between the input and the Reed-Solomon decoder, and in which the erasures signal passes through the deinterleaver.
4. A method of determining values encoded by a received 30 signal, the method comprising the steps of:

r - 35 providing a Reed-Solomon decoder having a signal input and an erasures input, and providing for erasures decoding; receiving a received many-carrier signal comprising 5 many data carriers representing a sequence of values in successive symbol periods; applying a signal described from the received signal to the Reed-Solomon decoder to decode values from the received signal; lo determining from the received signal a composite channel state indication for the carriers for each symbol period or a part thereof; and applying a signal derived from the composite channel state indication to the erasures input of the Reed- Solomon 15 decoder.