GB2384114A

GB2384114A - Ti rich TiN barrier layers

Info

Publication number: GB2384114A
Application number: GB0222507A
Authority: GB
Inventors: Siddhartha Bhowmik; Jia Huang; Sailesh Mansinh Merchant
Original assignee: Agere Systems LLC
Current assignee: Agere Systems LLC
Priority date: 2001-09-28
Filing date: 2002-09-27
Publication date: 2003-07-16
Also published as: JP2003124211A; KR20030027844A; GB0222507D0

Abstract

An electronic device includes a semiconductor layer and a layer formed over the semiconductor layer comprising nitrogen, N, and Titanium, Ti, where in at least a portion of the layer the ratio of atomic concentration of N:Ti is measureably less than 1.0 +/-.05. Alternately a device may include a layer of semiconductor material, a metal element and a layer formed against the metal element, comprising nitrogen, N, and Titanium, Ti, where in at least a portion of the layer the ratio of atomic concentration of N:Ti is observably less than 1.0. The TiN layer reduces electromigration.

Description

23841 1 4

Structure and Method for Reducing Electromigration Field of the Invention

The present invention relates to electronic circuit structures and, more 5 specifically, to structures and methods for reducing electromigration.

Backeround of the Invention Electromigration (EM) failures in metallization systems have posed a key reliability issue in integrated circuitry for decades. EM is due to momentum exchange between electrons and atoms under high current densities, e.g., 104 10 A/cm2. When a metal line undergoes EM the metal depletes at the cathode and accumulates at the anode. Material depletion at the cathode increases line resistance, eventually leading to an open feature. On the other hand, accumulation creates hillocks which may cause metal shorts between neighboring conductor lines. Metal opens and shorts induced by EM cause 15 serious functional failures, severely limiting the useful life of integrated circuits.

In the past, modern submicron interconnect lines, e.g., 0.36 Em or less, have typically comprised Al bamboo structures with top and bottom cladding layers.

To mitigate EM, the structures may incorporate solute, microstructure and current shunting solutions. Solute formations, e.g., alloys of Al and Cu.

20 typically 0.5 to 1 weight percent Cu. can improve EM lifetimes by orders of magnitude relative to pure Al. Bamboo microstructure exhibits sigmficant EM improvement compared to polycrystalline structures, or mixtures of polycrystalline and bamboo structures. Cladding of metal line layers provides current shunting during metal depletion. The shunting layers increase device 25 lifetimes by assuring an alternate current path, albeit a path of increased resistance. Although the aforementioned techniques have resulted in substantial improvements to reduce EM, there exist continued demands to reduce the width of conductor lines and, consequently, increase the current density. Thus, it is 30 expected that device failures caused by EM will continue as the density of interconnect technology advances.

Several other attempts to solve the EM problem have resulted in limited success. For example, it is believed that a predominance of <111> texture in Cu or Al may retard EM. With the metal stack typically comprising Ti/TiN/Al(Cu)/TiN, improvements in texture orientation may be had by 5 modifying the sputtering process of the under-layers. This approach has been effected with Ionized Metal Plasma (IMP) sputter deposition of Ti. See, Jaiswal, et al., "A Novel Interconnect Stack for Improved Resistance to Electromigration and Stress-induced Voiding", Proceedings of Advanced Metallization Conference 1999, Materials Research Society, pp.735 incorporated herein by lo reference. It was found the Al <111> texture can be enhanced by using IMP deposition to form the Ti under-layer and some reductions in the rate of EM have been observed, but early electromigration failures still persist.

In addition to deposition by IMP sputtering, the anneal of under-layers and over-layers of Ti in the (Ti/AVTi/TiN) stack has been proposed.

5 Specifically, formation of the intermetallic compound TiAl3 during thermal anneal may provide some improvements in electromigration. See, Lee, et al., "Roles of Ti-Intermetallic Compound Layers on the electromigration Resistance of Al-Cu interconnecting Stripes", Journal of Applied Physics 71,(12), June 15, 1992, pp. 5877 also now incorporated herein by reference. With the thickness 20 of the deposited Ti underlayer and over-layer in the range of lO - 60 nm, it is unsettled whether this improvement is due to better shunting or changes in the Al microstructure. Nonetheless, it is important to recognize that, absent a specific anneal, some TiAI3 may result at the Al interface as a result of normal processing. 25 A more successful modification to the Ti/TiN stack (at least in the conductor line over-layers) may result from deposition of a thin Ti layer in the range of 50 to loOA, at times referred to as Ti flash. Provision of Ti flash/TiN over-layers has been shown to significantly improve via electromigration.

Summary of the Invention

30 There is now provided a semiconductor device and related method for reducing electromigration in the device. Generally an electronic device includes

a semiconductor layer with a second layer formed over the semiconductor layer, the second layer comprising nitrogen, N. and Titanium, Ti, where in at least a portion of the layer the ratio of atomic concentration of N:Ti is measureably less than 1.0 +/-.05.

5 In one form of the invention a device includes a layer of semiconductor material, a metal element and a layer formed against the metal element, comprising nitrogen, N. and Titanium, Ti, where in at least a portion of the layer the ratio of atomic concentration of N:Ti is observably less than 1.0. A conductive member may be formed over the layer of semiconductor material, the 0 member including a first conductive layer, a second layer comprising Ti and nitrogen formed beneath the first layer, and a third layer comprising Ti and nitrogen formed over the first layer, with at least one of the first and third layers having a ratio of atomic concentration of nitrogen to Ti less than 0.95 +/-.05.

Also according to the invention a device includes a layer of 5 semiconductor material with a transistor formed therein and a dielectric layer having multiple sublayers formed over the layer of semiconductor material. A metal element is positioned in the dielectric layer to facilitate electrical connection between the transistor device and a conductor external to the structure. A second layer is positioned in contact with the metal element, that 20 layer comprising nitrogen, N. and titanium, Ti, with the ratio of atomic concentration N:Ti in a measurable region of the second layer less than 0.90 +/ 05. In a related method for reducing electromigration a conductor is formed over a semiconductor layer and against the conductor there is formed a layer 2s having a ratio of atomic concentration of nitrogen to metal less than 0.95.

Preferably the metal is predominantly titanium.

Brief Description_o Drawls

The invention will be best understood from the following detailed description when read in conjunction with the accompanying figures. According

30 to common practice, the various features of the drawings are not to scale. On the contrary, the dimensions of the various features are modified to improve clarity.

Common reference numerals are used to identify similar features throughout the figures. Figures 1, 2 and 3 each illustrate an embodiment of an interconnect member according to the invention; 5 Figure 4 illustrates an improved EM failure distribution curve based on the Figure 1 embodiment of the invention; Figure 5 provides a comparison of EM failure rates in metal runners based on the Figure 1 embodiment of the invention; Figure 6 illustrates a semiconductor device incorporating one 0 embodiment of the invention; and Figure 7 illustrates in partial cross sectional view a portion of a semiconductor structure wherein a via member connecting two runner members incorporates the principles of the invention.

Detailed Description of the Invention

5 The following description provides exemplary embodiments of the

invention while the terminology used herein is intended to distinguish the material compositions from conventional materials. In the past when compositions described generally as TiN, titanium nitride or stoichiometric TiN have been referenced as component layers in semiconductor structures the 20 materials are understood to not mean that the corresponding layer has a 1:1 stoichiometric ratio between N and Ti. In fact, the layers are known generally to have a N:Ti ratio greater than 1.0, i.e., hyperstoichiometric titanium nitride (nitrogen-rich titanium nitride), wherein N:Ti may typically range from 1.1 to 1.3. One reason it has been a consistent practice in deposition of titanium nitride 25 layers to have a hyperstoichio metric ratio is that this avoids formation of Ti2N, which is less effective as a diffusion barrier than TiN. In the hyperstoichiometric titanium nitride layers at least some of the excess nitrogen, i.e., nitrogen in excess of what is needed for truly stoichiometric TiN, is bellieved to reside at grain boundaries within the layer. Having excess N in the grain boundaries is 30 also believed to inhibit grain boundary diffusion of Al, Ti and Cu. Thus hyperstoichiometric titanium nitride layers are believed to serve as better

diffusion barriers than stoichiometric titanium nitride layers, i.e., N:Ti = 1. For further information regarding formulation of materials containing various ratios of Ti and N see Constitution of Binary Alloys, 2d ea., McGraw-Hill Book Company 1958 at pp. 989-991. Heretofore semiconductor devices have not been s formed with hypostoichiometric titanium nitride, i.e., wherein N:Ti is less than one, and with regard to characterization of such layers, within error limits, e.g., 0.05 for Rutherford Backscattering techniques, semiconductor layers resulting from sputter deposition of N and Ti have not been characterized as stoichiometric, i.e., N:Ti = 1 or hypostoichiometric. It is believed that all 0 titanium nitride layers deposited in semiconductor processes have been hyperstoichiometric. According to a preferred embodiment of the invention, Figure 1 illustrates in schematic form an exemplary interconnect member 10, e.g., a metal runner. A stack layer 12 of oxides, typically silicon oxides formed by High 5 Density Plasma (HDP) or Plasma Enhanced TEOS (tetraethyl orthosilicate) deposition is formed over a semiconductor layer or lower level of metallization (not shown). Other dielectric materials and deposition techniques may be applied. A layer 14 of Ti (deposited by conventional means of Physical Vapor Deposition (PVD) or low pressure Chemical Vapor Deposition (CVD)) is 20 formed on the oxide layer 12 to facilitate adhesion of subsequently deposited layer 18 comprising Ti and N. The layer 18 may be formed by reactive sputtering from a Ti target in a poisoned mode to render the layer nitrogen rich.

That is, in the poisoned target deposition mode, the surface of the Ti target is fully nitrided and the deposition is performed in a nitrogen rich environment. As 25 is consistent for prior art layers of semiconductor structures formed

predominantly of Ti and N. the resulting layer 18 will has a ratio of atomic concentrations of N:Ti in the range of 1.15:1.00 +/-.05 and certainly greater than 1.0 +/-.05. An Al layer 20 (alloyed with Cu) is sputter deposited on top of the TiN layer 18. A layer 24 also comprising N and Ti is formed over the Al layer 30 20 by reactive sputtering from a Ti target. After initial deposition to begin forming the layer 24 the nitrogen coming into the chamber is reduced such that

the net ratio of Ti to nitrogen in the layer 24 is less than 1.0 (Ti-Rich) although the measured net ratio could be as high as 1.0 +/-.05. Preferably, the atomic ratio of N:Ti is substantially less thanl.0, e.g., 0.95 or less. The ratio of N:Ti can be adjusted by varying flows of Ar:N in the reaction chamber. A suitable flow 5 would have 50 sccm of Ar and 40 to 50 seem of nitrogen. Generally it is preferred that the nitrogen flow rate be less than the argon flow rate. It will be understood that one may arrive at different net ratios which will depend in part on chamber design and volume, target power, pressure and other variables. The net composition of the layer 24 can be characterized by Rutherford I o backscattering spectrometry (RBS) analysis.

Another embodiment of the invention is schematically illustrated in interconnect member 30 of Figure 2 including a dielectric stack layer 12 (e.g., of silicon oxides formed by HDP plasma enhanced CVD from TEDS). To facilitate adhesion with subsequently deposited layers, a layer 14 of Ti is deposited on the 5 oxide layer 12 in a vacuum chamber, e.g., by Physical Vapor Deposition (PVD).

However, as noted herein the presence of hypostoichiometric titanium nitride may render this unnecessary. A layer 34 comprising Ti and N is deposited over the layer 14 (or oxide layer 12 if layer 14 is omitted) in a manner consistent with the formation of the layer 24 of Figure 1, preferably exhibiting a N:Ti ratio of 20 about 0.95 or less, but generally in the range of 1.00 +/-.05 or less. An aluminum layer 20 is deposited over the layer 34 and TiN layer 38 is deposited according to a conventional physical vapor deposition method with a poisoned target as described earlier for the layer 18. A layer 36 of Ti may be deposited over the layer 20 to form a Ti-flash layer which may serve as an etch stop for 25 subsequent processing.

Figure 3 illustrates still another embodiment of the invention wherein an interconnect member 40 resembles the member 30 of Figure 2 except that the layer 42, corresponding to the layer 36 of Figure 2 comprises Ti and N deposited in a manner consistent with the formation of the layer 24 of Figure I, i.e., having 30 a N:Ti ratio of about 1.00 +/-.05, or less.

Multiple embodiments of the invention have been illustrated for a metal conductor stack having one or more layers comprising a ratio of atomic concentrations of N:Ti less than 1.0 +/-0.05. Such layers may include other constituents and are generally referred to as nitrogen deficient when the ratio of 5 atomic concentration for N:Ti is less than 1.O. Positioning of such layers along conductive members has been demonstrated to mitigate EM of interconnect and mitigate associated failures about via members connecting runner members to other levels of metallization and bond pads.

Figure 4 illustrates an improved EM failure distribution curve for lo integrated circuit failures in a semiconductor device containing a tungsten via constructed according to the invention. The figure compares measured times to failure between four test groups each containing different circuit samples and constructed according to the prior art (Tests 1 - 4) and a test group of circuits

constructed according to the Figure l embodiment of the invention (Test 5) .

For purposes of further comparison Figure 5 confirms reduced EM failure rates in metal runners according to the Figure 1 embodiment of the invention.

The figure illustrates that for eight test groups of different circuit samples (Tests 1 - 8) over 90 percent of the samples in each test group failed within 1000 hours of operation. In contrast, for a ninth test group constructed according to the 20 Figure 1 embodiment of the invention, no metal runner failures were observed during the first 1000 hours of operation. The measured mean time to failure for the prior art test samples corresponding to Tests 1 - 8 ranged from 44 to 418

hours. Thus the mean time to failure of the ninth group reflects an improvement, relative to the samples in the prior art test groups of at least a factor of two.

25 Figure 6 illustrates, in a simplified, partial cross sectional, schematic view, a semiconductor device 100 incorporating multiple levels of interconnect according the embodiment of Figure 3. The levels include runner members 30 connected to one another and an underlying transistor 110 by contact via members 120. Typically, the transistor 110 is one of many devices formed on an 30 underlying semiconductor layer 130 and electrically isolated from other devices by insulative regions 140, e.g., shallow trench isolation or LOCOS grown

regions. The vies 120 may be formed conventionally of W or other metal layers with sublayers such as Ti and TiN intervening between the primary via metal, e.g., tungsten, and the adjoining conductor. Layers of comprising atomic concentration of N:Ti according to the invention may be formed in the vies to 5 further mitigate EM.

In the simplified, partial cross sectional view of Figure 7, a contact via member 160 formed in a dielectric stack layer 170 is shown to connect two runner members 180 formed in a conventional manner, e.g., by sputter deposition of A1. The via member 160 forms part of a multilevel interconnect 0 system including an underlying dielectric layer 172 formed over a semiconductor substrate. The via member includes a plug portion 182, predominantly comprising A1 and preferably alloyed with Cu. and further includes an optional Ti sublayer 184. Over the sublayer 184 there has been deposited a sublayer 186 comprising N and Ti characterized as nitrogen IS deficient, i.e., N:Ti is less than 1.0. This Ti rich sublayer 186 facilitates wetting of A1 during deposition of the plug material 182. The runner members 180 also include sublayers 190 comprising N and Ti according to the invention, e.g., N:Ti less than 1.0.

Figure 8 illustrates in simplified, partial cross sectional view, a MOM 20 capacitor 200 incorporating features of the invention. In a multi- level interconnect system formed over a semiconductor substrate (not shown) a lower runner member portion 180a serves as a lower capacitor plate and an upper runner member portion 180b serves as an upper capacitor plate. A layer 202 of dielectric material is formed between the plate runner member portions 180a and 25 180b. By way of example, the dielectric layer 202 may be formed of conventional silicon oxide, e.g., by plasma enhanced CVD, or silicon nitride or may comprise so-called high k capacitor dielectric materials such as tantalum pentoxide, titanium dioxide or materials formed with Hf or Zr. A sublayer 190 comprising N and Ti characterized as nitrogen deficient, i.e., N:Ti less than 1.0, 30 is formed over layer 180b.

The invention has been described with regard to an Al alloy conductive member in a level of interconnect on a semiconductor device. In other embodiments, the invention applies to metallization systems having conductive members formed with Cu. Au, Ag, Co, W. other forms of Al and other metals, as 5 well as the large array of alloys which may be formed with these. Also, while the disclosed embodiments described a layer comprising certain ratios of atomic concentration for Ti and N. layers comprising nitrogen and varying concentrations of others metals will also provide EM improvements. Generally, such layers may be formed with refractory metals and nitrogen, wherein the ratio lo of atomic concentration between the nitrogen, N. and the metal, M, is less than 1.0. Examples included layers formed with Ta, W. Co, Ti, or combinations of these. In the past, layers comprising Ti in combination with N have consistently been deposited with ratios of atomic concentration N:Ti which 5 naturally result when providing an abundance of nitrogen in the atmosphere as well as in the poisoned target. According to the invention, the deposition may occur in an environment which results in a substantially lower ratio N:Ti, e.g., 1.0 or less. The resulting layer is nitrogen deficient relative to conventional depositions of metal nitrides in systems having conductor members, e.g., Al, 20 formed with an underlayer or an over-layer of metal nitride. More generally, the conductive member for which EM is mitigated according to the invention may be any form of metal element which carries current, including a via contact to a level of interconnect in a semiconductor device. More generally, the metal element may be any conductor capable of carrying at least 104 A/cm2, and will 2s typically carry current through a cross sectional area less than.16 square micron.

Another advantage of providing a layer having N:Ti, of 1.0 or more preferably less than 1.0, is that the resulting layer has a relative abundance of Ti such that when the layer is deposited directly on the dielectric material sufficient adhesion to the dielectric can be assured. This renders unnecessary a discrete 30 layer of Ti at the interface of the dielectric and the layer containing Ti and N. Further, deposition rates for the hypostoichiometric titanium nitride are two to

three times faster than deposition rates for hyperstoichiometric titanium nitride.

Although specific values for the ratio of atomic concentrations of N:Ti have been disclosed, a wide range of values are contemplated, including 0. 85, 0. 8, 0.75, 0.7 and less than these.

Although the invention has been described with reference to exemplary embodiments, it is not so limited. Rather, the attended claims are to be construed to include numerous variants and embodiments which will be apparent to those skilled in the art upon reading of this detailed description. The scope of

the invention is only limited by the claims which follow.

Claims

Claims:

1. A semiconductor device comprising: a layer of semiconductor material; a metal element; and a layer fommed against the metal element, comprising nitrogen, N. and Titanium, Ti, where in at least a portion of the layer the ratio of atomic concentration of N:Ti is observably less than 1.0.

2. The device of claim 1 wherein the metal element is a conductive runner in a level of interconnect.

3. The device of claim I wherein the metal element is a conductive member comprising Al.

4. The device of claim 1 wherein the layer comprising nitrogen is formed over the metal element.

5 The device of claim 1 wherein the layer comprising N and Ti is formed along a conductive runner and the ratio of atomic concentration of N:Ti in the layer is 0.95 or less.

6. The device of claim 1 wherein the layer comprising N and Ti has a ratio of atomic concentration of N:Ti of 0.90 or less and the metal element comprises one or more materials taken from the group consisting of Al and Cu.

7. A semiconductor device comprising: a layer of semiconductor material; and

a conductive member formed over the layer of semiconductor material, said member including a first conductive layer, a second layer comprising Ti and nitrogen formed beneath the first layer, and a third layer comprising Ti and nitrogen formed over the first layer, with at least one of the first and third layers 5 having a ratio of atomic concentration of nitrogen to Ti less than 0.95 +/-.05.

8. The device of claim 7 wherein the third layer comprises a ratio of atomic concentration of nitrogen to titanium of approximately 0.90.

9. The device of claim 7 wherein the conductive member comprises one or more elements taken from the group consisting of Al, Cu. Au, Ag, W and Co. lo 11. A method for reducing electromigration in a semiconductor structure, comprising: providing a semiconductor layer; forming a conductor over the semiconductor layer; and forming against the conductor a layer having a ratio of atomic 5 concentration of nitrogen to metal less than 0.95.

12. The method of claim 11 wherein the step of forming the conductor layer includes depositing a layer including one or more elements from the group consisting of Al and Cu.

14. A method for reducing electromigration in a circuit having a conductive 20 member comprising the step of positioning next to the conductive member a layer comprising nitrogen, N. and Titanium, Ti, wherein the ratio of atomic concentration N:Ti in a portion of the layer is less than 0.95 +/-.05 as measured by a Rutherford Backscattering technique.

15. A semiconductor structure comprising: 25 a layer of semiconductor material with a transistor formed therein; a dielectric layer comprising multiple sublayers formed over the layer of semiconductor material; a metal element positioned in the dielectric layer to facilitate electrical connection between the transistor device and a conductor external to the 30 structure;

a second layer positioned in contact with the metal element, comprising nitrogen, N. and titanium, Ti, wherein the ratio of atomic concentrations N:Ti in a measurable region of the second layer is less than 0.90 +/-.OS.

16. The structure of claim 15 wherein the stated ratio of atomic concentrations 5 N:Ti in a measurable region of the second layer is less than 0.80 +/-.05.

17. The structure of claim 15 wherein the metal element is positioned in a via to provide electrical connection between a conductive runner and another conductive element.

18. The structure of claim IS wherein the metal element comprises Al.

lo 19. An electronic device comprising: a semiconductor layer; a layer formed over the semiconductor layer comprising nitrogen, N. and Titanium, Ti, where in at least a portion of the layer the ratio of atomic concentration of N:Ti is measureably less than 1.0 +/-.05.

5 20. The device of claim 19 wherein the ratio of atomic concentration of N:Ti is measureably less than 0.95 +/-.05.

21. The device of claim 19 wherein the ratio of atomic concentration of N:Ti is measureably less than.90 +/-.05.