JP2003124211A - Structure and method for reducing electromigration - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure and a method for reducing electromigration. SOLUTION: In one embodiment of a method for reducing electromigration in a device, an electronic device includes a semiconductor layer and a layer composed of nitrogen N and titanium T formed on the semiconductor layer. At at least a part of the layer, an atomic density ratio of N:Ti is measured smaller than 1.0±0.05. Alternatively, the device may include a layer of semiconductor material, a metallic element and a layer composed of nitrogen N and titanium T formed for the metallic element in which the atomic density ratio of N:Ti is measured smaller than 1.0 at at least a part of the layer.

Description

Detailed Description of the Invention

FIELD OF THE INVENTION The present invention relates to electronic circuit structures, and more particularly to structures and methods for reducing electromigration.

[0002] electromigration (EM) failure in the background metallization system of the present invention, for several decades has been the problem of the key failure in an integrated circuit. In EM, electrons and atoms exchange momentum under a high current density of, for example, 10 ⁴ A / cm ² . When the metal lines give rise to EM, the metal depletes at the cathode and accumulates at the anode. Depletion of material at the cathode increases the line resistance and eventually leads to an open circuit fault. On the other hand, accumulation causes hillocks, which can cause metallic shorts between adjacent lines. Metallic opens and shorts caused by EMs are significant, causing serious malfunctions that limit the useful life of integrated circuits. Traditionally, modern interconnect lines, eg 0.36 μm or less, have typically included Al bamboo structures with top and bottom cladding layers.

To alleviate EM, the structure may incorporate solutes, microscopic structures and current switching solutions. Forming solutes of Al and alloys of Cu, typically containing 0.5 to 1 weight percent Cu, can improve EM lifetime by several orders of magnitude compared to pure Al. Bamboo microstructure has significantly improved EM compared to polycrystalline structure or a mixture of polycrystalline and bamboo structure. If a clad is formed in the metal line layer, the current can be switched during metal depletion. The switching layer increases the lifetime of the device by reliably changing the current path despite the increased resistance current path.

While the above description has provided substantial improvements to reduce EM, there continues to be a need to reduce conductive lines and therefore current density. As such, device failures caused by EM continue with advances in interconnect technology.

Several other attempts to solve the EM problem have been successful. For example, in Cu or Al
It is believed that the EM decreases when the 111> structure becomes dominant. Typically Ti / TiN / Al (Cu)
The orientation of structures in metal stacks containing / TiN has been modified by the underlying layer sputtering process.
This approach has been performed by ionized metal plasma (IMP) sputter deposition of Ti. Jaiswal
Wal, et al., "A New Interconnect Stacking Structure To Improve Resistance To Electromigration And Stress-Induced Void Generation", Proceedings Of Advanced Metallization Conference.
ings of Advanced Metalliz
ation Conference) 1999, Materials Research Society, page 735. This document is included herein by reference. By using IMP deposition to form the Ti underlayer, Al <
It has been found that the 111> structure can be increased, and the speed of the EM has been observed to decrease to some extent, but early electromigration failures are still present.

In addition to deposition by IMP sputtering,
It has been proposed to anneal lower and upper layers of Ti in a (Ti / Al / Ti / TiN) stack.
Specifically, the formation of intermetallic compound TiAl ₃ during thermal annealing may improve electromigration to some extent. Lee et al., “Al-C
Role of Ti Interconnect Compound Layer on Electromigration Resistance of u Interconnect Stripes, ”Journal of Applied Physics (Journal)
of Applied Physics) 7 /, (1
2), June 15, 1992, pp. 5877. This document is included herein by reference. 10-
At deposited Ti bottom and top layer thicknesses in the range of 60 nm, it is not possible to conclude whether this improvement is due to the well switched or altered Al microstructure.
Nevertheless, it is important to recognize that some TiAl ₃ may result in Al interfaces as a result of normal processes, even without a specific anneal.

Ti (at least in the upper layer of the conductor line)
An effective modification of the / TiN stack structure is obtained by depositing a thin Ti layer in the range of 50 to 100Å, often referred to as Ti flash. Forming a Ti flash / TiN top layer has been shown to be significantly improved through electromigration.

[0008] Related methods for lessening the electromigration in summary semiconductor devices and device of the present invention is shown. Generally, an electronic device includes a semiconductor layer and a second layer formed on the semiconductor layer.
The second layer contains nitrogen N and titanium Ti. In at least a portion of the layer, the atomic density ratio of N: Ti is
1.0 +/-. Measured smaller than 05.

In one form of the invention, a device includes a layer of semiconductor material, a metallic element and a layer comprising nitrogen N and titanium Ti and formed for the metallic element. In at least some of the layers, the atomic density ratio of N: Ti is observed to be less than 1.0. A conductive portion may be formed on the layer of semiconductor material, the portion being formed on the first conductive layer, a second layer containing Ti and nitrogen formed below the first layer, the first layer. A third layer containing Ti and nitrogen, the first and third layers
At least one of the layers has a nitrogen to Ti atomic density ratio of 0.95 +/-. 05.

Also in accordance with the invention, the device includes a layer of semiconductor material having a transistor formed therein, a dielectric layer having a plurality of sublayers formed on the layer of semiconductor material, the metal element being a transistor device. And is disposed in the dielectric layer to facilitate electrical connection between the conductor and the outside of the structure. The second layer is placed in contact with the metallic element and comprises nitrogen N and titanium Ti, and the atomic density ratio of N: Ti in the measurable region of the second layer is 0.90 + /.
−. Less than 05.

In a related method for reducing electromigration, a conductor is formed on a semiconductor layer and a layer is formed having a nitrogen to metal atomic density ratio to the conductor of less than 0.95. It The metal is preferably titanium.

DETAILED DESCRIPTION OF THE INVENTION The terminology used herein is to distinguish material composition from conventional materials, but the following description illustrates examples of the invention. Conventionally, the composition generally described as TiN is titanium nitride or stoichiometric TiN refers to the constituent layers in the semiconductor structure, and the material is the corresponding layer, the stoichiometry between N and Ti is 1: 1. It is understood that having a ratio does not mean that.
In fact, the layers are known to have N: Ti ratios of 1.0 or higher, ie superstoichiometric titanium nitrides (nitrogen rich titanium nitrides). In this case, N: Ti is typically in the range 1.1 to 1.3. One reason that consistent deposition of titanium nitride layers to have a superstoichiometric ratio has been due to this is Ti ₂
The formation of N is to be avoided. It is less effective as a diffusion barrier than TiN. It is believed that in superstoichiometric titanium nitride layers, at least some excess nitrogen is present at grain boundaries in the layer, that is, more nitrogen than is needed for true stoichiometric TiN. . Excessive N at the grain boundaries hinders grain boundary diffusion of Al, Ti and Cu. Therefore, it is believed that the superstoichiometric titanium nitride layer acts as a better diffusion barrier than the stoichiometric titanium nitride layer or N: Ti = 1. For more information on the formulation of materials containing various ratios of Ti and N, see Binary Alloy Construction, 2 volumes, McGraw-Hill Publishing Company 195.
8, pages 989-991. Heretofore, semiconductor devices have used low-stoichiometric titanium nitride, namely N: Ti.
Was not formed with a nitride having a value of less than 1. With regard to the evaluation of such layers, in the case of the Rutherford backscattering technique, the semiconductor layers obtained by sputter deposition of N and Ti, for example, with an error range of 0.05, are stoichiometric, ie N: Ti = 1. It has not been evaluated for presence or low stoichiometry. It is believed that all titanium nitride layers deposited in semiconductor processes were superstoichiometric.

In accordance with the preferred embodiment of the present invention, FIG. 1 shows a schematic form of an example of an interconnect (10), eg, a metal runner. A stack of oxides (12), typically silicon oxide, formed by high density plasma (HDP) or plasma enhanced TEOS (tetraethyl orthosilicate) deposition is used for metallization (not shown) of semiconductor layers or underlying layers. Not formed). Other dielectric materials and deposition techniques may be applied. Of Ti (deposited by conventional means of physical vapor deposition (PVD) or low pressure chemical vapor deposition (CVD)) to promote adherence of the subsequently deposited layer of Ti and N (18). A layer (14) is formed on the oxide layer (12). Layer (18) may be formed by reactive sputtering from a Ti target in Poison mode with excess nitrogen. That is, in Poison target deposition mode, the Ti target surface is fully nitrided,
The deposition is performed in a nitrogen excess atmosphere. Similar to the prior art layers of semiconductor structure formed mainly of Ti and N, the resulting layer (18) is 1.15: 1.00 +/−. 05,
Certainly 1.0 +/-. The atomic density ratio of N: Ti is larger than 05. Al layer (alloyed with Cu) (2
0) is sputter deposited on top of the TiN layer (18). The layer (24) is formed on the Al layer (20) by reactive sputtering from a Ti target, and N and T
It consists of i. After the initial deposition to initiate layer (24) formation, the nitrogen entering the chamber has a net Ti to nitrogen ratio in the layer (24) less than 1.0 (Ti excess).
To reduce. However, the measured net ratio is 1.0 +/-. May be as high as 05. The atomic ratio of N: Ti is essentially less than 1.0, for example 0.9.
5 or less is preferable. The N: Ti ratio can be adjusted by changing the flow rate of Ar: N in the reaction chamber. Suitable flow rates are 50 sccm Ar and 40 to 50 sccm nitrogen. Generally, it is preferred that the flow rate of nitrogen be less than the flow rate of argon. It will be appreciated that depending on the design and volume of some chambers, target power, pressure and other variables, different net ratios are possible. The net composition of layer (24) can be evaluated by Rutherford backscattering spectrum (RBS) analysis.

Another embodiment of the invention is (eg, TEO
It is shown schematically in the interconnect (30) of FIG. 2 which includes a dielectric stack (12) of silicon oxide formed by S to HDP plasma enhanced CVD. It is deposited on the oxide layer (12) in a vacuum vessel, for example by physical vapor deposition (PVD), to promote adherence with subsequently deposited layers. However, as described herein, the presence of low stoichiometric titanium nitride eliminates this requirement. The layer (34) composed of Ti and N is formed in the same manner as the formation of the layer (24) in FIG.
If 4) is omitted, it is deposited on the oxide layer (12)).
It is preferred that the N: Ti ratio be about 0.95 or less, but generally 1.00 +/-. It is in the range of 05 or less. An aluminum layer (20) is deposited on layer (34) and a TiN layer (38) is deposited according to conventional physical vapor deposition with a poison target, as described above for layer (18). A layer of Ti (36) may be deposited on layer (20) to form a Ti flash layer that will serve as an etch stop layer in a subsequent process.

FIG. 3 illustrates yet another embodiment of the present invention in which the interconnect (40) is similar to the portion (30) of FIG. 2, but corresponds to the layer (36) of FIG. Layer (42) is
The same manner of forming layer (24) in FIG. 1, ie about 1.0.
0 +/-. It consists of Ti and N deposited to have an N: Ti ratio of 05 or less.

Several embodiments of the present invention include 1.0 +/-
The case of a laminated structure of a metal conductor having one or a plurality of layers containing an atomic density ratio of N: Ti smaller than 0.05 is shown. Such layers may contain other components and are generally referred to as nitrogen deficient when the atomic density ratio of N: Ti is less than 1.0. Placement of such layers along the conductive portion is shown to mitigate the EM of the interconnect and to mitigate attendant failures around the via portion connecting the runner portion to other levels of metallization and bond pads. Came.

FIG. 4 shows an improved EM failure distribution curve for integrated circuit failures in a semiconductor device containing a tungsten via formed in accordance with the present invention. The figures include different circuit samples, up to a failure between four test groups (Test 1-4) made according to the prior art and a test group (Test 5) of a circuit made according to the embodiment of FIG. 1 of the invention. Comparing the measured times.

For further comparison, FIG. 5 is a schematic representation of the invention of FIG.
Confirm the reduced EM failure rate in metal runners according to the example of FIG. The figure shows that for eight test groups of different circuit samples (Tests 1-8), over 90 percent of the samples in each test group failed within 1000 hours of operation. In contrast, in the ninth test group made according to the embodiment of FIG. 1 of the present invention, the first 10
No metal runner failures were observed during 00 hours of operation. For prior art test samples corresponding to tests 1-8,
The average time measured for failure was 44 to 418 hours. Therefore, the mean time to failure of the ninth group reflects an improvement of at least two orders of magnitude over the samples of the prior art test group.

FIG. 6 schematically illustrates, in partial cross-section, a semiconductor device (100) incorporating multiple levels of interconnection according to the embodiment of FIG. The levels are interconnected and the runner portion (30) is connected to the underlying transistor (110) by a contact via portion (120).
including. Typically, transistor (110) is one of many devices formed on the underlying semiconductor layer (130).
It is then electrically isolated from other devices by an insulating region (140) such as a shallow trench isolation or a LOCOS growth region. The via (120) is conventionally formed of W or another metal layer and may have a basic via metal such as tungsten and sublayers such as Ti and TiN sandwiched between adjacent conductors. . A layer comprising an N: Ti atomic density according to the present invention may be formed in the via to further relax the EM.

In the simplified partially cross-sectional view of FIG. 7, the contact via portion (160) formed in the dielectric stack (170) is formed by a conventional method such as sputter deposition of Al. The two illustrated runner portions (180) are shown to be connected. The via portion (160) forms part of a multi-level interconnect system that includes an underlying dielectric layer (172) formed on a semiconductor substrate. The via portion comprises a plug portion (182), which comprises mainly Al, preferably an alloy with Cu, and optionally a Ti partial layer (184). Partial layer (1
84) on top of which nitrogen is deficient, ie a partial layer of N and Ti characterized by N: Ti less than 1.0 (18
6) has been deposited. This Ti-excess partial layer (186)
Promotes wetting of Al during the deposition of plug material (182). The runner portion (180) also includes a partial layer (190) containing N and Ti according to the present invention, eg, where N: Ti is less than 1.0.

FIG. 8 shows a MOM capacitor (200) incorporating the features of the present invention in a simplified, partial cross-section. In a multilevel interconnect system formed on a semiconductor substrate (not shown), an underlying runner portion (1
80a) acts as the lower capacitance plate and the upper runner portion (180b) acts as the upper capacitance plate. The layer of dielectric material (202) is the plate runner portion (180a).
And (180b). By way of example, the dielectric layer (202) may be formed of conventional silicon oxide or silicon nitride, for example by plasma enhanced CVD,
Or tantalum pentoxide, titanium dioxide or Hf or Z
It may include so-called high k capacitance dielectrics such as materials formed with r. A partial layer (190) of N and Ti, characterized by nitrogen deficiency, ie N: Ti less than 1.0, is formed on layer (180b).

The present invention has been described with respect to Al alloy conductor portions in the level of interconnection on semiconductor devices. In another embodiment, the present invention provides Cu, Au, A
It is applied to metallization systems having conductor portions formed of g, Co, W, other forms of Al and other metals, and many types of alloys that may be formed therewith. Also, while the examples presented here have shown layers with some ratio of atomic densities for Ti and N, layers containing nitrogen and other elements of varying densities will also provide EM improvement. Generally, such layers may be formed of refractory metals and nitrogen, where the ratio of atomic densities between nitrogen N and metal M is less than 1.0. Examples are Ta, W, Co, Ti
Alternatively, a layer formed by a combination of these is included.

Conventionally, layers containing Ti in combination with N have been consistently deposited with a naturally occurring atomic density ratio of N: Ti when both the poison target and the atmosphere contain a large amount of nitrogen. According to the present invention, the deposition may be carried out in an atmosphere which results in an essentially low ratio N: Ti of, for example, 1.0 or less. The resulting layer is nitrogen deficient as compared to conventional metal nitride deposition in systems having a conductor portion such as Al formed with a metal nitride lower or upper layer, for example. More generally, the metal element is at least 10 ^4.
It can be any electrical conductor capable of flowing A / cm ² , typically the metal being. Through the cross-sectional area of less than 16 square microns,
Apply current.

Another advantage of forming a layer with N: Ti of 1.0 or more preferably less than 1.0 is that the resulting layer is relatively rich in Ti so that the layer is deposited directly on the dielectric material. This is to ensure sufficient adhesion to the dielectric. This eliminates the need for a separate layer of Ti at the interface of the dielectric and the layers containing Ti and N. Further, the deposition rate of low stoichiometric titanium nitride is 2-3 times faster than the deposition rate of superstoichiometric titanium nitride. Although specific values are shown for the atomic density ratio of N: Ti, a wide range of values including 0.85, 0.8, 0.75, 0.7 and smaller values are conceivable.

Although the present invention has been described by way of examples, it is not so limited. Rather, the claims are intended to cover many variations and embodiments that will become apparent to those skilled in the art upon reading this detailed description. The present invention can be clearly understood by referring to the drawings.
The elements drawn in the drawings are not to scale and the dimensions of each element have been modified for clarity.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an interconnection part according to the present invention, respectively.

FIG. 2 is a diagram showing an embodiment of an interconnection part according to the present invention, respectively.

FIG. 3 is a diagram showing an embodiment of an interconnection part according to the present invention, respectively.

FIG. 4 shows an improved EM failure distribution curve based on the embodiment of FIG. 1 of the present invention.

FIG. 5: E in a metal runner according to the embodiment of FIG. 1 of the present invention.
It is the figure which compared the M failure speed.

FIG. 6 is a diagram showing a semiconductor device incorporating an embodiment of the present invention.

FIG. 7 is a partial cross-sectional view of a portion of a semiconductor structure in which a via portion connecting two runner portions incorporates the principles of the present invention.

FIG. 8 is a simplified, partial cross-sectional view of a MOM capacitor incorporating features of the present invention.

[Explanation of symbols]

10 Interconnects 12 Laminated structure, oxide layer 14 layers 18 layers, TiN layer 20 Al layer, aluminum layer 24 layers 30 Interconnects, parts 34,36 layers 38 TiN layer 40 interconnections 42 layers 100 semiconductor devices 110 transistors 120 contact via part, via 130 semiconductor layer 140 insulating area 160 Contact via part, via part 170 laminated structure 172 dielectric layer 180 runner part 180a Plate runner part, lower runner part 180b Plate runner part, upper runner part, layer 184 partial layer 186 partial layer 190 partial layers 192 (none in text) 200 MOM capacity 202 Dielectric layer, layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ziafan             United States 91030 California,             South Pasadena, Breewood Court               969 (72) Inventor Silesh Manshin Merchant             United States 32835 Florida, Oh             Land, Vineland Oaks Bou             Lvard 8214 F term (reference) 5F033 HH08 HH11 HH13 HH14 HH15                       HH18 HH19 HH33 JJ09 JJ11                       JJ13 JJ14 JJ15 JJ18 JJ19                       JJ33 KK08 KK11 KK13 KK14                       KK15 KK18 KK19 KK33 LL10                       MM08 NN06 NN07 PP15 PP16                       XX05

Claims (19)

[Claims] 1. A layer of semiconductor material; a metal element; and nitrogen N
And titanium Ti, in at least part of the layer,
A semiconductor device comprising a layer formed over a metallic element where the atomic density ratio of N: Ti is observed to be less than 1.0. 2. The device of claim 1, wherein the metallic element is a conductive runner in one level of the interconnect. 3. The device of claim 1, wherein the metallic element is a conductor portion containing Al. 4. The device of claim 1, wherein the nitrogen containing layer is formed on the metal element. 5. The layer containing N and Ti is formed along the conductive runner, and the atomic density ratio of N: Ti in the layer is:
The device of claim 1 which is 0.95 or less. 6. The layer containing N and Ti has an atomic density ratio of 0.90 or less, and the metal element comprises one or more materials taken from the group consisting of Al and Cu. Device. 7. A layer of semiconductor material; and a conductive portion formed over the layer of semiconductor material, the portion comprising a first conductive layer, Ti and nitrogen formed under the first conductive layer. Comprising a second layer comprising and a third layer comprising Ti and nitrogen formed on the first layer, at least one of the first and third layers being 0.95 +/-. A semiconductor device having an atomic density ratio of nitrogen to Ti less than 05. 8. The device of claim 7, wherein the third layer comprises an atomic density ratio of nitrogen to titanium of about 0.90. 9. The conductive portion is made of Al, Cu, Au, A
The device of claim 7 including one or more elements from the group consisting of g, W and Co. 10. A semiconductor comprising forming a semiconductor layer; forming a conductor on the semiconductor layer and forming a layer having a nitrogen to metal atomic density ratio of 0.95 to the conductor. A method of reducing electromigration in a structure. 11. The step of forming a conductor layer comprises Al and Cu.
11. The method of claim 10, comprising depositing a layer containing an element of one or more elements of the group consisting of: 12. Nitrogen N and titanium T next to the conductive portion.
A layer containing i is arranged and the atomic density ratio of N: Ti in a portion of the layer is 0.9, as measured by Rutherford backscattering technique.
5 +/-. A method of reducing electromigration in a circuit having a conductive portion including steps less than 05. 13. A layer of semiconductor material having a transistor formed therein; a dielectric layer comprising a plurality of partial layers formed on a layer of semiconductor material; electrical between a transistor device and a conductor to the exterior of the structure. A metal element arranged in the dielectric layer for facilitating the connection; arranged in contact with the metal element,
The atomic density ratio N: Ti in the measurable region containing nitrogen N and titanium Ti was 0.90 +/-. A second structure smaller than 05; 14. The atomic density ratio N: Ti in the measurable region of the second layer is 0.80 +/−. 14. The structure of claim 13, which is less than 05. 15. The structure of claim 13, wherein the metal element is disposed in the via to electrically connect the conductive runner to another conductive element. 16. The structure of claim 13, wherein the metal element comprises Al. 17. A semiconductor layer; formed on the semiconductor layer, comprising nitrogen N and titanium Ti, wherein in at least a portion of the layer, the atomic density ratio of N: Ti is 1.0 +/−. An electronic device comprising a layer measured to be less than 05. 18. The atomic density ratio of N: Ti is 0.95.
+/-. 18. The device of claim 17, which measures less than 05. 19. The atomic density ratio of N: Ti is. 90+
/-. 18. The device of claim 17, which measures less than 05.