GB2367671B - Software fifos in a multimaster bus system - Google Patents

Software fifos in a multimaster bus system

Info

Publication number
GB2367671B
GB2367671B GB0200399A GB0200399A GB2367671B GB 2367671 B GB2367671 B GB 2367671B GB 0200399 A GB0200399 A GB 0200399A GB 0200399 A GB0200399 A GB 0200399A GB 2367671 B GB2367671 B GB 2367671B
Authority
GB
United Kingdom
Prior art keywords
bus system
multimaster bus
fifos
software
software fifos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0200399A
Other versions
GB0200399D0 (en
GB2367671A (en
Inventor
Geir Robert Svelmoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of GB0200399D0 publication Critical patent/GB0200399D0/en
Publication of GB2367671A publication Critical patent/GB2367671A/en
Application granted granted Critical
Publication of GB2367671B publication Critical patent/GB2367671B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
GB0200399A 1999-07-20 2000-07-19 Software fifos in a multimaster bus system Expired - Fee Related GB2367671B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NO19993558A NO312926B1 (en) 1999-07-20 1999-07-20 Communication over multimaster bus
PCT/NO2000/000242 WO2001006382A1 (en) 1999-07-20 2000-07-19 Software fifos in a multimaster bus system

Publications (3)

Publication Number Publication Date
GB0200399D0 GB0200399D0 (en) 2002-02-27
GB2367671A GB2367671A (en) 2002-04-10
GB2367671B true GB2367671B (en) 2003-10-15

Family

ID=19903600

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0200399A Expired - Fee Related GB2367671B (en) 1999-07-20 2000-07-19 Software fifos in a multimaster bus system

Country Status (5)

Country Link
AU (1) AU6324000A (en)
DE (1) DE10084835B3 (en)
GB (1) GB2367671B (en)
NO (1) NO312926B1 (en)
WO (1) WO2001006382A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0360153A2 (en) * 1988-09-19 1990-03-28 Princeton University Oblivious memory computer networking
EP0391584A2 (en) * 1989-04-03 1990-10-10 AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Fifo memory system
US5214759A (en) * 1989-05-26 1993-05-25 Hitachi, Ltd. Multiprocessors including means for communicating with each other through shared memory
US5522045A (en) * 1992-03-27 1996-05-28 Panasonic Technologies, Inc. Method for updating value in distributed shared virtual memory among interconnected computer nodes having page table with minimal processor involvement
WO1997000533A1 (en) * 1995-06-15 1997-01-03 Intel Corporation A method and apparatus for transporting messages between processors in a multiple processor system
US5870572A (en) * 1991-07-22 1999-02-09 International Business Machines Corporation Universal buffered interface for coupling multiple processors, memory units, and I/O interfaces to a common high-speed interconnect

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68924306T2 (en) * 1988-06-27 1996-05-09 Digital Equipment Corp Multi-processor computer arrays with shared memory and private caches.
WO1993004432A2 (en) * 1991-08-16 1993-03-04 Multichip Technology High-performance dynamic memory system
FR2687487B1 (en) * 1992-02-19 1996-12-20 Alcatel Business Systems SYSTEM FOR SHARING ACCESS TIME TO A MEMORY SHARED BETWEEN A PROCESSOR AND OTHER APPLICATIONS.
US5594702A (en) * 1995-06-28 1997-01-14 National Semiconductor Corporation Multi-first-in-first-out memory circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0360153A2 (en) * 1988-09-19 1990-03-28 Princeton University Oblivious memory computer networking
EP0391584A2 (en) * 1989-04-03 1990-10-10 AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Fifo memory system
US5214759A (en) * 1989-05-26 1993-05-25 Hitachi, Ltd. Multiprocessors including means for communicating with each other through shared memory
US5870572A (en) * 1991-07-22 1999-02-09 International Business Machines Corporation Universal buffered interface for coupling multiple processors, memory units, and I/O interfaces to a common high-speed interconnect
US5522045A (en) * 1992-03-27 1996-05-28 Panasonic Technologies, Inc. Method for updating value in distributed shared virtual memory among interconnected computer nodes having page table with minimal processor involvement
WO1997000533A1 (en) * 1995-06-15 1997-01-03 Intel Corporation A method and apparatus for transporting messages between processors in a multiple processor system

Also Published As

Publication number Publication date
NO993558L (en) 2001-01-22
AU6324000A (en) 2001-02-05
NO312926B1 (en) 2002-07-15
NO993558D0 (en) 1999-07-20
WO2001006382A1 (en) 2001-01-25
GB0200399D0 (en) 2002-02-27
DE10084835B3 (en) 2005-12-22
GB2367671A (en) 2002-04-10

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20150719