GB2341769B - Data packet reordering in a computer bus system - Google Patents
Data packet reordering in a computer bus systemInfo
- Publication number
- GB2341769B GB2341769B GB9820423A GB9820423A GB2341769B GB 2341769 B GB2341769 B GB 2341769B GB 9820423 A GB9820423 A GB 9820423A GB 9820423 A GB9820423 A GB 9820423A GB 2341769 B GB2341769 B GB 2341769B
- Authority
- GB
- United Kingdom
- Prior art keywords
- data packet
- bus system
- computer bus
- packet reordering
- reordering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9820423A GB2341769B (en) | 1998-09-18 | 1998-09-18 | Data packet reordering in a computer bus system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9820423A GB2341769B (en) | 1998-09-18 | 1998-09-18 | Data packet reordering in a computer bus system |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9820423D0 GB9820423D0 (en) | 1998-11-11 |
GB2341769A GB2341769A (en) | 2000-03-22 |
GB2341769B true GB2341769B (en) | 2003-10-08 |
Family
ID=10839135
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9820423A Expired - Fee Related GB2341769B (en) | 1998-09-18 | 1998-09-18 | Data packet reordering in a computer bus system |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2341769B (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006982A (en) * | 1988-10-21 | 1991-04-09 | Siemens Ak. | Method of increasing the bandwidth of a packet bus by reordering reply packets |
WO1992016080A1 (en) * | 1991-03-01 | 1992-09-17 | Washington University | Data packet resequencer for a high speed data switch |
US5481536A (en) * | 1993-10-29 | 1996-01-02 | Siemens Aktiengesellschaft | Method for restoring a prescribed sequence for unordered cell streams in ATM switching technology |
US5619497A (en) * | 1994-12-22 | 1997-04-08 | Emc Corporation | Method and apparatus for reordering frames |
US5666551A (en) * | 1994-06-30 | 1997-09-09 | Digital Equipment Corporation | Distributed data bus sequencing for a system bus with separate address and data bus protocols |
-
1998
- 1998-09-18 GB GB9820423A patent/GB2341769B/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006982A (en) * | 1988-10-21 | 1991-04-09 | Siemens Ak. | Method of increasing the bandwidth of a packet bus by reordering reply packets |
WO1992016080A1 (en) * | 1991-03-01 | 1992-09-17 | Washington University | Data packet resequencer for a high speed data switch |
US5481536A (en) * | 1993-10-29 | 1996-01-02 | Siemens Aktiengesellschaft | Method for restoring a prescribed sequence for unordered cell streams in ATM switching technology |
US5666551A (en) * | 1994-06-30 | 1997-09-09 | Digital Equipment Corporation | Distributed data bus sequencing for a system bus with separate address and data bus protocols |
US5619497A (en) * | 1994-12-22 | 1997-04-08 | Emc Corporation | Method and apparatus for reordering frames |
Also Published As
Publication number | Publication date |
---|---|
GB2341769A (en) | 2000-03-22 |
GB9820423D0 (en) | 1998-11-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) |
Free format text: REGISTERED BETWEEN 20101111 AND 20101117 |
|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20150918 |