GB2365625A - Method for forming a triple well of a semiconductor device - Google Patents
Method for forming a triple well of a semiconductor device Download PDFInfo
- Publication number
- GB2365625A GB2365625A GB0126594A GB0126594A GB2365625A GB 2365625 A GB2365625 A GB 2365625A GB 0126594 A GB0126594 A GB 0126594A GB 0126594 A GB0126594 A GB 0126594A GB 2365625 A GB2365625 A GB 2365625A
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- well
- region
- type impurities
- photoresist pattern
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A method for forming a triple well of a semiconductor device. The triple well includes an n-well A, a first p-well B surrounded by the n-well A and a second p-well C spaced from the first p-well B and adjacent to the n-well A. The n-well A is formed by implanting impurities in a horizontal layer beneath the surface of the substrate, and then implanting impurities in a region above one end of the horizontal layer. Only one conductivity type of impurities need be implanted in each well. Therefore, it is possible to prevent a decrease of carrier mobility and an increase of the leakage current.
Description
<Desc/Clms Page number 1> METHOD FOR FORMING A TRIPLE WELL OF A SEMICONDUCTOR DEVICE BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to @a method for forming semiconductor devices and more particularly, to a method for forming a triple well consisting of three ion-implanted regions, each of which contains only one conductivity type of impurities.
2. Description of the Prior Art.
In general, the conventional semiconductor devices are formed by the COOS (Complementary MOS) technology. According to the CMOS technology, a PMOS and an NMOS transistors are fabricated on a same wafer. Accordingly, the well formation technique is required to isolate the transistors from one another.
The diffusion process has been used in the well formation technique. According to this diffusion well formation technique, impurities are implanted at a low energy level and the high- temperature process is performed for a long time. Accordingly, the manufacturing cost is increased and it-is difficult to control the characteristics of semiconductor devices because the ion concentration is monotonously decreased from the surface of the well to the bottom of the well.
A conventional well formation technique is developed to solve the above mentioned problems. According to the conventional well
<Desc/Clms Page number 2>
formation technique, impurities are implanted at a high energy level and a relatively simple thermal treatment is performed. It is possible to prevent the punch through and the latch up phenomena and to improve the characteristics of semiconductor devices.
The well structure is classified into twin well and triple well structures on the basis of the number of wells. FIG. 1 and FIG., 2 are schematic views of twin well and triple well structures respectively formed on the semiconductor substrate 10 and 20. The twin well includes an n-well 11 and a p-well 12. The triple well, shown in FIG. 2, is formed on the p-type semiconductor substrate 20 and it includes an n-well A, a first p-well B and a second p-well C. The first p-well B is apart, by a predetermined distance, from a second p-well C and is adjacent to the n-well A. The second p-well C is surrounded by the n-well A. The conductivity types of respective wells may be changed into the opposite types when the triple well is formed on the n-type semiconductor substrate.
In comparison with the twin well structure, the triple well structure has an advantage in that it is possible to differently control the characteristics of an NMOS transistor formed on the first p-well B and an NMOS transistor formed on the second p-well C. The triple well structure also has another advantage that the second p- well C has the sufficient voltage to withstand the noise because the well junction capacitance between the second p-well C and the n-well A is relatively large.
The conventional method for forming a triple well is shown in FIGS. 3A to. 3D.
<Desc/Clms Page number 3>
First; referring to FIG. 3A, a photoresist pattern 31 is formed on a p-type semiconductor substrate 30. The photoresist pattern 31 exposes two regions, in which an n-well A and a second p-well C are respectively to be formed. The second p-well C is surrounded by the n-well A. After forming the photoresist pattern 31, the implantation processes are carried out by three or four times with different energy to form n-type impurities doped regions 32 in the n-well A and the second p-well C.
Referring to FIG. 3B, the photoresist pattern 31 is removed and a photoresist pattern 33 is formed. The photoresist pattern 33 exposes a region, in which a first p-well B is to be formed. The first p-well B is apart, by a predetermined distance, from the second p-well C and is adjacent to the n-well A. After forming the photoresist pattern 33, the implantation process are carried out by three or four times with different energy to form p-type impurities doped regions 34 in the first p-well B.
Referring next to FIG. 3C, the photoresist pattern 33 is removed and a photoresist pattern 35 is formed. The photoresist pattern 35 exposes a region, in which the second p-well C, surrounded by the n-well, is to be formed. After forming the photoresist pattern 35, the implantation processes are carried out by three or four times with different energy to form p-type impurities doped regions 36 in the second p-well C.
A portion of n-type impurities doped regions 32 was formed in the second p-well C before the p-type impurities doped regions 36 are formed. Accordingly, the amount of the p-type impurities implanted
<Desc/Clms Page number 4>
into the second p-well C should be sufficient to *offset the n-type impurities formerly implanted into the second p-well C. Therefore, it is difficult to control the doping profile of the second p-well C. The leakage current increases because the substrate is damaged. The mobility of carriers decreases because two conductivity types of ions-exist in one well. ..
Referring next to FIG. 3D, the triple well, which includes the n-well A, the first p-well B and the second p-well C, is formed in the semiconductor substrate 30 by the thermal treatment performed after the implantation processes.
FIG. 4 is an ion concentration profile 41 of the region taken along the line X-X' in FIG. 3D. The ion concentration profile 42 of the n-type impurities implanted in the process to form the n-well A and the ion concentration profile 43 of p-type impurities implanted in the process to form the second p-well C are also shown in FIG.4. The longitudinal axis represents the logarithm of the effective concentration. The effective concentration is defined by the difference between the p-type impurities concentration Na and the n- type impurities concentration Nd. The ion concentration profile 41 of the second p-well C is determined by the composition of the ion concentration profiles 42 and 43.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a triple well capable of preventing the reduction of the
<Desc/Clms Page number 5>
mobility of carriers and reducing the leakage current.
In accordance with the present invention, there is provided a method for fabricating a semiconductor device having a triple well structure, the method comprising the steps of providing a semiconductor substrate; implanting first . conductivity type impurities into a first region of said semiconductor substrate to form a first well; implanting second conductivity type impurities into a second region of said semiconductor substrate, wherein. said second region is adjacent to said first well and positioned below a surface of said semiconductor substrate and extends to a depth corresponding to the depth of said first well; implanting second conductivity type impurities into a third region of said semiconductor substrate so that said second region and said third region form a second well surrounding said first well; and implanting first conductivity type impurities into a fourth region of said semiconductor substrate to form a third well, wherein said fourth region is adiacent to said second region.
<Desc/Clms Page number 6>
BRIEF DESCRIPTION OF THE DRAWINGS
<Desc/Clms Page number 7>
These and other objects, features and advantages of the present invention will be more fully apparent from the description and the accompanying drawings in which: FIG. I is a cross sectional view of a twin well structure; FIG. 2 is a cross sectional view of a triple well structure; FIGS. 3A to 3D are cross sectional views illustrating a conventional method for forming a triple well of semiconductor device: FIG. 4 is a plot showing an ion concentration profile of the region taken along the line X-X' in FIG. 3D; FIGS. 5A to 5E are cross sectional views illustrating a method for forming a triple well of semiconductor device; and FIG. 6 is a plot showing an ion concentration profile of the region taken along the line X-X' in FIG. 5E.
An example, helpful for understanding the present invention will be described in detail below with reference to FIGS. 5A to 5E and 6. In FIGS. 5A to 5E, a method for forming a triple well is shown.
First, referring to FIG. 5A, a photoresist pattern 51 is formed on a p-type semiconductor substrate 50. The photoresist pattern 51 exposes two regions, in which an n-well A and a second p-well C are respectively to be formed. The second p-well C is
<Desc/Clms Page number 8>
surrounded by the n-well A. After forming the photoresist pattern . 51, n-type impurities are deeply implanted into the n-well A to form a first impurities doped region 52.
Referring to FIG. 5B, the photoresist pattern 51 is removed and a photoresist pattern 53 is formed. The photoresist pattern 53 is formed, exposing the upper surface' of the' n-well A. After forming the photoresist pattern 53, N-type impurities are implanted into the region exposed by the photoresist pattern 53, to form a second impurities doped regions 54 in the n-well. The. implantation processes are carried out by three or four times with different energy.
In the implantation process to form the n-well A, none of the n-type impurities are implanted in the second p-well C. Therefore, it is easy to design the doping profile of the second p-well C surrounded by the n-well A.
Referring next to FIG. 5C, the photoresist pattern 53 is removed and a photoresist pattern 55 is formed. The photoresist pattern 55 exposes a region in which a first p-well B is to be formed. The first p-well B is apart, by a predetermined distance, from the second p-well C and is adjacent to the n-well A. After forming the photoresist pattern 55, the implantation processes are carried out by three or four times with different energy to form the p-type impurities doped regions 56.
Referring next to FIG. 5D, the photoresist pattern 55 is removed and a photoresist pattern 57 is formed. The photoresist pattern 57 exposes a region, in which the second p-well C is to be
<Desc/Clms Page number 9>
formed. The second p-well C is surrounded by the n-well A. After forming the photoresist pattern 57, the implantation processes are carried out by three or four times with different energy to form the p-type impurities doped regions 58. In the second p-well C, only p-type impurities are implanted, which is different from the conventional method. Accordingly, it is possible to prevent the reduction of the mobility of carriers and reduces the leakage current: Referring next to FIG. 5E, the triple well, including the n= well A, the first p-well & and the second p-well C, is formed in the semiconductor substrate 50 by the thermal treatment performed after the implantation processes.
FIG. 6 shows an ion concentration profile 61 of the region taken along the line X-X' in FIG. 5E. The ion concentration profile 62 of the n-type impurities implanted in the process to form the n-well A and the ion concentration profile 63 of p-type impurities implanted in the process to form the second p-well C are also shown in FIG.6. The longitudinal axis represents the logarithm of the effective concentration. The effective concentration is defined by the difference between the p-type impurities concentration Na and n-type impurities concentration Nd. The ion concentration profile 67. in the second p-well C region is determined only by the implantation process for forming the second p-well C.
Another method for forming a triple well will be described below. According to this method, three
<Desc/Clms Page number 10>
or four times bf the implantatiot processes are carried out with different energy, to form a first p-well surrounded by an n-well. Thereafter, three oz four times of implantation processes are carried out with different energy to form a second p-well which is apart, by a predetermined distance, from the first p-well and is adjacent to the n-well. The, ii-type impurities are deeply implanted into the n-well to form a first impurities doped region of the n-well and the implantation processes are carried out by three or four times with different energy to form a second impurities doped regions of the n-wel1.
In a related method a first and a second p-well are simultaneously formed. That is to say, p-type impurities are simultaneously implanted into the first and the second p- well, thereafter, n-type impurities are implanted only into the n-well. Alternatively, n- type impurities may be implanted only into a portion of an n-well, thereafter, p-type impurities may be simultaneously implanted into the first and second p-well.
The first p-well is surrounded by the n-well and the second p-well is apart, by a predetermined distance, from the first p-well and is adjacent to the n-well.
In the above-mentioned methods, impurities deeply implanted in said deepest part of the n-well are phosphor. The dose of implanted phosphor is in the range of 3E13/cm' to and it is implanted at an energy level in the range-of 1.6 MeV to 2 MeV.
<Desc/Clms Page number 11>
Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the present invention as disclosed in the accompanying claims.
<Desc/Clms Page number 12>
Claims (2)
- CLAIMS: 1. A method for fabricating a semiconductor device having a triple well structure, the method comprising the steps of a) providing a semiconductor substrate; b) implanting first conductivity type impurities into a first region of said semiconductor substrate to form a first well; c) implanting second conductivity type impurities into a second region of said semiconductor substrate, wherein said second region is adjacent to said first well and positioned below a surface of said semiconductor substrate and extends to a depth corresponding to the depth of said first well; d) implanting second conductivity type impurities into a third region of said semiconductor substrate so that said second region and said third region form a second well surrounding said first well; and e) implanting first conductivity type impurities into a fourth region of said semiconductor substrate to form a third well, wherein said fourth region is adjacent to said second region.
- 2. A method of fabricating a semiconductor device according to claim 1 and substantially as hereinbefore described with reference to Figures 5 and 6.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076307A KR100228331B1 (en) | 1996-12-30 | 1996-12-30 | Method for manufacturing triple well of semiconductor device |
| GB9727402A GB2320812B (en) | 1996-12-30 | 1997-12-24 | Method for forming a triple well of a semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0126594D0 GB0126594D0 (en) | 2002-01-02 |
| GB2365625A true GB2365625A (en) | 2002-02-20 |
| GB2365625B GB2365625B (en) | 2002-05-15 |
Family
ID=26312857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0126594A Expired - Fee Related GB2365625B (en) | 1996-12-30 | 1997-12-24 | Method for forming a triple well of a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2365625B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5501993A (en) * | 1994-11-22 | 1996-03-26 | Genus, Inc. | Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation |
-
1997
- 1997-12-24 GB GB0126594A patent/GB2365625B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5501993A (en) * | 1994-11-22 | 1996-03-26 | Genus, Inc. | Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2365625B (en) | 2002-05-15 |
| GB0126594D0 (en) | 2002-01-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20131224 |