GB2362005A - Hardware/software codesign system - Google Patents

Hardware/software codesign system

Info

Publication number
GB2362005A
GB2362005A GB0115062A GB0115062A GB2362005A GB 2362005 A GB2362005 A GB 2362005A GB 0115062 A GB0115062 A GB 0115062A GB 0115062 A GB0115062 A GB 0115062A GB 2362005 A GB2362005 A GB 2362005A
Authority
GB
United Kingdom
Prior art keywords
hardware
software
processor
description
codesign
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0115062A
Other versions
GB2362005B (en
GB0115062D0 (en
Inventor
Jonathan Martin Saul
Matthew Philip Aubury
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Celoxica Ltd
Original Assignee
Celoxica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Celoxica Ltd filed Critical Celoxica Ltd
Publication of GB0115062D0 publication Critical patent/GB0115062D0/en
Publication of GB2362005A publication Critical patent/GB2362005A/en
Application granted granted Critical
Publication of GB2362005B publication Critical patent/GB2362005B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

A hardware/software codesign system for making an electronic circuit which includes both dedicated hardware and software controlled resources. The codesign system receives a behavioural description of the target electronic system and automatically partitions the required functionality between hardware and software, while being able to vary the parameters (e.g. size or power) of the hardware and/or software. Thus, for instance, the hardware and the processor for the software can be formed on an FPGA, each being no bigger than is necessary to perform the desired functions. The codesign system outputs a description of the required processor (which can be in the form of a net list for placement on the FPGA), machine code to run on the processor, and a net list or register transfer level description of the necessary hardware. It is possible for the user to write some parts of the description of the target system at register transfer level to give closer control over the operation of the target system, and the user can specify the processor or processors to be used, and can change, for instance, the partitioner, compilers or speed estimators used in the codesign system. The automatic partitioning may be performed by using a genetic algorithm which estimates the performance of randomly generated different partitions and selects an optimal one of them.
GB0115062A 1998-12-22 1999-12-21 Hardware/software codesign system Expired - Fee Related GB2362005B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9828381.5A GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system
PCT/GB1999/004338 WO2000038087A1 (en) 1998-12-22 1999-12-21 Hardware/software codesign system

Publications (3)

Publication Number Publication Date
GB0115062D0 GB0115062D0 (en) 2001-08-15
GB2362005A true GB2362005A (en) 2001-11-07
GB2362005B GB2362005B (en) 2003-07-16

Family

ID=10844844

Family Applications (2)

Application Number Title Priority Date Filing Date
GBGB9828381.5A Ceased GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system
GB0115062A Expired - Fee Related GB2362005B (en) 1998-12-22 1999-12-21 Hardware/software codesign system

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GBGB9828381.5A Ceased GB9828381D0 (en) 1998-12-22 1998-12-22 Hardware/software codesign system

Country Status (3)

Country Link
AU (1) AU1875200A (en)
GB (2) GB9828381D0 (en)
WO (1) WO2000038087A1 (en)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
WO2000031652A2 (en) 1998-11-20 2000-06-02 Altera Corporation Reconfigurable programmable logic device computer system
US6430736B1 (en) * 1999-02-26 2002-08-06 Xilinx, Inc. Method and apparatus for evolving configuration bitstreams
US6539532B1 (en) 1999-02-26 2003-03-25 Xilinx, Inc. Method and apparatus for relocating elements in an evolvable configuration bitstream
US6363517B1 (en) 1999-02-26 2002-03-26 Xilinx, Inc. Method and apparatus for remotely evolving configuration bitstreams
US6363519B1 (en) 1999-02-26 2002-03-26 Xilinx, Inc. Method and apparatus for testing evolvable configuration bitstreams
US6378122B1 (en) 1999-02-26 2002-04-23 Xilinx, Inc. Method and apparatus for evolving a plurality of versions of a configuration bitstream in parallel
AU2001283549A1 (en) * 2000-08-07 2002-02-18 Altera Corporation Software-to-hardware compiler
US7343594B1 (en) 2000-08-07 2008-03-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US7069204B1 (en) * 2000-09-28 2006-06-27 Cadence Design System, Inc. Method and system for performance level modeling and simulation of electronic systems having both hardware and software elements
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
US20020112219A1 (en) * 2001-01-19 2002-08-15 El-Ghoroury Hussein S. Matched instruction set processor systems and efficient design and implementation methods thereof
US7055019B2 (en) 2001-02-13 2006-05-30 Ellipsis Digital Systems, Inc. Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms
US20020116166A1 (en) * 2001-02-13 2002-08-22 El-Ghoroury Hussein S. Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set process systems using interconnected design components
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
EP1286279A1 (en) * 2001-08-21 2003-02-26 Alcatel Configuration tool
US6668312B2 (en) * 2001-12-21 2003-12-23 Celoxica Ltd. System, method, and article of manufacture for dynamically profiling memory transfers in a program
US20030140337A1 (en) * 2001-12-21 2003-07-24 Celoxica Ltd. System, method, and article of manufacture for data transfer reporting for an application
US20030121010A1 (en) * 2001-12-21 2003-06-26 Celoxica Ltd. System, method, and article of manufacture for estimating a potential performance of a codesign from an executable specification
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
GB0215034D0 (en) * 2002-06-28 2002-08-07 Critical Blue Ltd Architecture generation method
EP1527390A2 (en) * 2002-07-25 2005-05-04 Koninklijke Philips Electronics N.V. Source-to-source partitioning compilation
AU2003286131A1 (en) * 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US6964029B2 (en) * 2002-10-31 2005-11-08 Src Computers, Inc. System and method for partitioning control-dataflow graph representations
US6983456B2 (en) * 2002-10-31 2006-01-03 Src Computers, Inc. Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
DE10316292A1 (en) * 2003-04-09 2004-11-11 Siemens Ag Method and arrangement for the performance prediction of an information technology system
US7424698B2 (en) 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
US7073159B2 (en) 2004-03-31 2006-07-04 Intel Corporation Constraints-directed compilation for heterogeneous reconfigurable architectures
WO2007067894A2 (en) * 2005-12-05 2007-06-14 National Instruments Corporation Implementing a design flow for a programmable hardware element that includes or is coupled to a processor
US8121813B2 (en) 2009-01-28 2012-02-21 General Electric Company System and method for clearance estimation between two objects
US20120096445A1 (en) * 2010-10-18 2012-04-19 Nokia Corporation Method and apparatus for providing portability of partially accelerated signal processing applications
US8959469B2 (en) 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
KR102441717B1 (en) * 2014-11-12 2022-09-07 자일링크스 인코포레이티드 Heterogeneous multiprocessor program compilation targeting programmable integrated circuits
CN104572234A (en) * 2014-12-29 2015-04-29 杭州华为数字技术有限公司 Method for generating source codes used for parallel computing architecture and source-to-source compiler
US10956241B1 (en) 2017-12-20 2021-03-23 Xilinx, Inc. Unified container for hardware and software binaries

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994010627A1 (en) * 1992-11-05 1994-05-11 Giga Operations Corporation System for compiling algorithmic language source code into hardware
WO1997013209A1 (en) * 1995-10-03 1997-04-10 Telefonaktiebolaget L M Ericsson (Publ) Method of producing a digital signal processor
EP0772140A1 (en) * 1995-10-23 1997-05-07 Interuniversitair Micro-Elektronica Centrum Vzw A design environment and a design method for hardware/software co-design

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1065611A3 (en) * 1995-10-23 2006-05-10 Interuniversitair Microelektronica Centrum Vzw A design environment for hardware/software co-design

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994010627A1 (en) * 1992-11-05 1994-05-11 Giga Operations Corporation System for compiling algorithmic language source code into hardware
WO1997013209A1 (en) * 1995-10-03 1997-04-10 Telefonaktiebolaget L M Ericsson (Publ) Method of producing a digital signal processor
EP0772140A1 (en) * 1995-10-23 1997-05-07 Interuniversitair Micro-Elektronica Centrum Vzw A design environment and a design method for hardware/software co-design

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
32nd Annual Hawaii Int Conf on Systems Sciences, 1999, 5-8 Jan, p10, ISBN:0-7695-0001-3, Saul J M . *
IEE Proc:Computers and Digital Techniques, v143, n1, pp 55-63, 1 Jan 1996, ISSN:1350-2387, Edwards *
Int Workshop on Field Programmable Logic and Applications, Abingdon, pp 284-293, 1 Sep 1997, Lechner *

Also Published As

Publication number Publication date
GB9828381D0 (en) 1999-02-17
GB2362005B (en) 2003-07-16
AU1875200A (en) 2000-07-12
GB0115062D0 (en) 2001-08-15
WO2000038087A1 (en) 2000-06-29

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20100128 AND 20100203

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20181221