GB2360630A

GB2360630A - Semiconductor device having device section and alignment mark section with isolation regions

Info

Publication number: GB2360630A
Application number: GB0024591A
Authority: GB
Inventors: Hiroki Koga
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1999-10-07
Filing date: 2000-10-06
Publication date: 2001-09-26
Also published as: KR100371295B1; JP2001110889A; GB0024591D0; KR20010050911A; TW508719B

Abstract

Semiconductor device (10) has device section (11) and alignment mark section (12). The device section (11) has element regions and element isolation regions, and alignment mark section (12) has mark formation regions (12a) and mark isolation regions (12b). The ratio of the area of the mark formation region (12a) to the sum of the area of mark formation (12a) and mark isolation regions (12b) is smaller than the ratio of the area of the element region to the sum of the area of the element region and element isolation region. The isolation regions are preferably trench isolation regions. The mark formation region (12a) may be in a rectangular frame shape. The height difference between the surface of the mark formation region (12a) and the surface of the mark isolation region (12b) enables detection by an alignment mark detector. Also disclosed is a semiconductor device with device section (11) and alignment mark section (12), where both sections have two regions formed in identical processes, and the ratio of the areas of the two regions in each section is different.

Description

2360630 SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an element isolation structure by means of a trench isolation provided with alignment marks f or registration.

Description of the Prior Art

According to the conventional manufacturing process of a semiconductor device, in the formation of a pattern through arrangement of masks on a wafer, it was necessary for a second and subsequent masks to be arranged in alignment with the patterns formed 'in the preceding steps.

For the purpose of the alignment, the pattern formation is proceeded by aligning a mask pattern with a pattern in a device section while confirming positional information based on an indexing pattern (alignment marks) formed in the outer periphery of the device section and an indexing pattern formed on the mask.

The alignment marks that will be illustrated below are marks in a pattern used for alignment of an element region for source/drain region in a layer and a gate electrode to be formed in its upper layer in a metal - oxide semiconductor (MOS) transistor, and are formed in the element region and in an element isolation region. Although the element isolation region in the alignment mark section does not play a role for element isolation, it will be so called for convenience, and a similar situation applies also to the element region.

FIG. 11 is a plan view showing an example of device layout 2 for a conventional semiconductor device. As shown in FIG. 11, a wafer 100 includes a device section 2, an alignment mark section 3 to be used for overlapping in a lithography process, and a scribe region 13. The squareshaped device section 2 is demarcated by being surrounded by the scribe section 13, and the alignment mark section 3 is arranged in the scribe region 13 one for every lateral and longitudinal sides, for example, for each device section. A semiconductor device 1 is obtained by cutting the wafer 100 along the scribe lines 13a with a scriber, and separating the cut piece into a semiconductor chip or putting the cut piece into a sealed package. If cutting takes place along lines deviated from the correct positions of the scribe lines 13a, the semiconductor device 1 may have alignment marks cut in pieces or may lose them, but such an imperfect piece will also be referred to as a semiconductor device 1 in the following discussion.

FIG. 12 shows an example of a conventional pattern in which element regions are formed, where FIG. 12 (a) is a plan view of a device section and FIG. 12 (b) is a plan view of an alignment mark section. As shown in FIG. 12 (a), the device section 2 (FIG. 11) has a plurality of element regions 2a that are juxtaposed in the longitudinal and lateral directions, and element isolation regions 2b that are other than the element regions 2a. In the device section, a regular pattern such as the memory cell array section of a dynamic random access memory (DRAM) i s f ormed, and a MOS transi s tor i s f ormed in each element region 2a.

Each element region 2a is formed in a rectangular shape with a lateral width of about 0. 20 M m and a longitudinal width of about 1.00 #m in the plane of the paper of FIG. 12, and these 3 regions 2a are formed adjacently with a spacing of about 0.20 ju m in the lateral direction and about 0. 60 u m in the longitudinal direction, and the columns of the element regions 2a are arranged staggered alternately in the longitudinal 5 direction.

As shown in FIG. 12 (b), the alignment mark section 3 has a plurality of element regions 3a juxtaposed in the lateral direction, and element isolation regions 3b formed between the element regions 3a. Each of the element regions 3a is formed in a rectangular shape with a lateral width of about 6. 00 p m, and they are arranged so as to be adjacent with each other about 6. 00 11 m apart. In other words, the alignment mark section 3 has a 1-to-1 line and space arrangement.

Here, for the element regions and the element isolation regions, the ratio of the area occupied by the element regions in a certain area S will be defined as data factor. When the certain area S involves an area pertaining to the element regions and an area pertaining to the element isolation regions, the data factor is represented by: data ratio = area of the element regions/(area of the element regions + area of the element isolation regions). In the case shown in FIG. 12, the data factor is about 31.25% (FIG. 12W) for the device section 2, and about 50% (FIG. 12(b)) for the alignment mark section 3.

Now, as a field oxide film for element isolation formed on a silicon substrate of the waf er 100 a local oxidation of silicon (LOCOS) film has been used conventionally. However, when an LOCOS film is employed, the width of the element isolation region is enlarged due to the bite of the silicon oxide film, which is disadvantageous under the current tendency of 4 advancement in the refinement of the device structure. For this reason, a shallow trench isolation (STI) structure in which an isolation oxide film is formed in a shallow trench is being adopted lately.

FIG. 13 to FIG. 15 illustrate the manufacturing processes of a general trench isolation structure in a conventional alignment mark. FIG. 13 shows sectional views of processes (part 1) as seen facing the direction of arrows B and B' in FIG.

12 (b), and FIG. 14 (part 2) and FIG. 15 (part 3) show similar sectional views of the processes.

First, on a silicon substrate 4, a silicon oxide film Sa is grown by thermal oxidation to a thickness of about 5 to 30nm, preferably to about 20nm, then a silicon nitride film 6 is grown on top of it by, for example, low pressure chemical vapor deposition (LPCVD) to a thickness of about 100 to 25Orm, preferably to about 20Onm, and a resist pattern 7 is formed by photolithography at a scheduled site for formation of the element isolation region (FIG. 13(a)).

Next, the silicon nitride film 6 and the silicon' oxide film 5a are etched sequentially by a dry etching, and the resist pattern 7 is removed (FIG. 13 (b)). Then, the silicon substrate 4 is etched to a prescribed depth by a dry etching using the patterned silicon nitride film 6 as a mask to form a trench 8 (FIG. 13 (c)) - The depth of the trench 8 is about 200 to 40Onm, preferably about 30Onm. The thickness of the remaining silicon nitride film 6 is given by (grown thickness of 100 to 250nm) - (etched amount of about 10 to 50nm) where (about 10 to 5Onm, preferably about 20nm) represents the reduction in the film thickness.

Next,a silicon oxide film 5b is grown to about 10 to 30nm, preferably to about 20nm on the inner surface of the trench 8 by a thermal oxidation of the inner surface of the trench 8. Then, a silicon oxide film 5c is grown to a thickness of about 450 to 650nm, preferably to about 50Onm by a high density plasma (HDP) oxide film growth method in this example, and the silicon oxide film 5c is embedded in the trench 8 (FIG. 14 (d) Next, an unwanted amount of silicon oxide film Sc is removed by chemical mechanical polishing (CMP), and the thickness of the remaining silicon nitride film 6 is controlled to about 120 to 170nm, preferably to about 150nm, (FIG. 14 (e)). Then, the height difference d between the surface of the silicon oxide film 5c and the lower surface of the silicon oxide film 5a is adjusted to about 45 to 95nm, preferably to about 75nm by a wet etching using buffered hydrofluoric acid or the like. Thi s adjustment is carried out, since an exact film thickness control by CMP is dif f icult, by inspecting the film thickness after the CMP, and determining the etching time by calculation based on the difference of the inspected thickness from a predetermined film thickness. Then, the remaining silicon oxide film 6 is removed completely by etching with hot phosphoric acid for about 60 to 100min, preferably for about 80min, and the silicon oxide film 5a on the element region is removed by a wet etching. The condition of the wet etching is the removal of about 20 to 40nm, prefe.rably about 30run of the silicon oxide film 5a (FIG.

14(f)).

Next, a silicon oxide film 5d is grown on the element region by thermal oxidation once more to a thickness of about 10 to 30nm, preferably to about 20nm, and an impurity is implanted to the channel region (not shown) of a MOS transistor (FIG.

15(g)). Then, the silicon oxide film 5d is removed by a wet 6 etching. The condition for the wet etching is the removal of the film 5d by about 20 to 40nm, preferably by about 30nm. In this case, in the device section 2, the manufacturing conditions are so set that the surface of the silicon oxide film 5c is flush with the surface of the silicon substrate 4 in the region other than the silicon oxide f ilm 5c, with no stepped part. Moreover, a silicon oxide film 5e which is to serve as a gate oxide film for the device section 2 is grown to about 6 to 12nm, preferably to about lOnm by a thermal oxidation (FIG. 15 (h)).

Next, polycrystalline silicon 9a is grown to about 50 to 15Onm, preferably to about 10Onm to form a gate electrode of the device section 2, and tungsten silicide 9b is grown to about 50 to 20Onm, preferably to about 150nm (FIG. 15 (i)). Then, though not shown, a photoresist is coated on the surface of the tungsten silicide 9b to form a pattern for the gate electrode, and the photoresist is subjected to exposure of an aligner using a prescribed mask pattern. In this case, positional information on the alignment marks on the wafer and the alignment marks on the mask is read by an alignment mark detector provided in the aligner, and the mask position or the wafer position is adjusted so as to align their positions Next, referring to FIG. 18 that illustrates the configuration and the operation of the alignment mark detector, the method of alignment mark detection will be described.

Light (i) emitted from a light source 31 is reflected (r) by the surface of the wafer 100 and enters an alignment mark detector 32 which detects the intensity of the reflected light r. The alignment mark detector 32 detects a point where the intensity of the reflected light r changes by scanning the incident light i from the light source 31 in the horizontal 7 direction of the paper, and decides it as the boundary of the alignment mark.

Now, when a film 9 has transmitting property to the wavelength of the incident light i, namely, when the intensity of transmitted light tl is higher than the intensity of reflected light r2, it is possible to detect the boundary of the lower layer even if the surface of the layer is flat. For example, if the reflected light r3 from an element isolation region 5 is weak in a region k, the detection level of the alignment detector 32 is low as shown in FIG. 18. In the meantime, if the reflected light r3 from an element region 4 is strong in a region m, the detection level of the alignment detector 32 is high as shown in FIG. 18. The alignment mark detector 32 decides a point at which the curve for the detection level intersects the line for a prescribed threshold as the boundary of the alignment mark.

on the contrary, when the film 9 has a strong reflecting property to the wavelength of the incident light i, namely, when the intensity of the reflected light r2 is higher than the intensity of the transmitted light tl, the detector 32 cannot detect the boundary of the lower layer if the surface is flat. For example, both of the reflected light r3 in the region k from the element isolation region 5 and the reflected light r3 in the region m f rom the element region 4 are strong, and the detection level of the alignment mark detector 32 remains at a high level as shown in FIG. 18. Because of this, the alignment mark detector 32 cannot detect the boundary of the alignment mark (boundary of the element isolation region 5 and the element region 4) since the curve for the detection level will never intersect the line for the prescribed threshold.

8 Moreover, even when the reflecting property of the film 9 is strong, the boundary of the alignment mark (boundary of the element isolation region 5 and the element region 4) can be detected if there is a prescribed level difference of size d.

For example, in the region m and a region o the re f lected light r is strong, and the detection level is at a high level as shown in FIG. 18. In a region n, reflected light rl is reflected in a direction other than toward the alignment mark detector 32 so that the detection level falls off. The alignment mark detector 32 decides the point at which the curve for the detection level intersects the line for the prescribed threshold, or the midpoint between two intersections as the boundary of the alignment mark.

However, if the level dif f erence d is smaller than a specified value, the boundary (boundary between the element isolation region 5 and the element region 4) of the alignment mark cannot be detected. For example, if the level difference d is small, the reflected light rl reflected irregularly by the region n can be made incident on the alignment mark detector 32, so the detection level will not drop too much as shown in FIG. 18. Since the curve for the detection level has no intersection with the line for the threshold, the alignment mark detector 32 cannot detect the boundary of the alignment mark.

Accordingly, when a film of tungsten silicide (WSi) or titanium silicide (TiSi) that has an especially large reflectance (r/i) to the alignment light (i) is formed in such an underlying layer, it is not possible in an aligning work of lithography process to recognize the alignment mark se.ction 3 with high accuracy since the lower layer of the silicide film cannot be seen clearly.

9 In other words, if a tungsten silicide (WSi) film is not formed as a gate electrode and there is only the polycrystalline silicon film 9a, then it is possible to detect the alignment mark (element region) since the element region and the element 5 isolation region in the lower layer can be seen through.

However, the gate electrode of a DRAM is used also as a word line, and it is required to have a low resistance, so the gate electrode is generally made of a silicide (WSi). When a film of WSi is formed, its reflecting property is so strong that the boundary of the lower layer is difficult to be seen, resulting in deterioration in the alignment precision, which brings about a drop in the yield of the products.

As shown in FIG. 15 (i), when an alignment mark is formed by trench isolation through formation of the isolation oxide film 5c in the shallow trench 8, the level difference between the element isolation region 3b and the element region 3a is about 20nm, and since the surface is almost flat and the boundary of the layer becomes difficult to be discerned, high precision alignment has been difficult to attain.

Namely, if the result of the removal by CMP of the excess portion of the oxide film embedded in the shallow trench is such that there is no substantial difference in the data factor of the device section 2 and the alignment mark section 3, for example, in such a case as the data factor of about 31.25% for the device section 2 and about 50% for the alignment mark section (FIG. 12), the difference in the thickness of the remaining nitride films after the CMP is slight, and the level difference in the alignment mark is very small even in the finished state of the element isolation.

To cope with the situation, a technique is known in which after formation of the element isolation a stepped part is formed by etching the embedded oxide film in the element isolation region of only the alignment mark section 3.

FIG. 16 illustrates sectional views of processes as seen facing arrows B and B' in FIG. 12 (b) that show a part of the manufacturing processes of a trench isolation for another type of conventional alignment mark, and FIG. 17 is a plan view for describing a part of the manufacturing processes shown in FIG.

16. The processes (j), (k) and (1) in FIG. 16 are those following the process (g) in FIG. 15 in place of the processes (h) and (i) in FIG. 15.

When the embedded oxide film of the element isolation region of only the alignment mark section 3 is etched after the formation of the element isolation, the etching is carried out after growth once more of a silicon oxide film 5d on the element region by thermal oxidation to a thickness of about 10 to 30nm, preferably to about 20nm (FIG. 15 (g)) - After the formation of the silicon oxide film 5d, the silicon oxide film 5c is removed by about 100 to 250nm., preferably by about 150nm by a wet or dry etching. In this case, as shown in FIG. 17, the memory cell array section is protected by covering it with a resist mask, and the resist is removed so as to open windows only for the alignment mark sections 3 (regions surrounded by thick lines in the figure).

Accordingly, the embedded oxide film 5c is etched only in the element isolation region of the alignment mark section 3 (FIG. 16(j)).

Next, a silicon oxide film 5e that is to serve as a gate oxide film of the device section (FIG. 11) is grown to a thickness of about 6 to 12nm, preferably to about lOnm by thermal oxidation (FIG. 16W). Then, polycrystalline silicon 9a is grown to about 50 to 150nm, preferably to about 10Onm, and tungsten silicide 9b is grown to about 50 to 20Ornn, preferably to about 150nm, to form the gate of the device section 2 (FIG. 16 (1)).

As a result, the level difference between the element isolation region and the element region becomes about 150rm which permits the alignment mark detector 32 to detect it, realizing alignment with high precision.

As in the above, when etching the embedded oxide film of the element isolation region of only the alignment mark section 3, it becomes necessary to add a lithography process in which the alignment mark sections 3 alone are exposed and the device sections 2 are covered, so that it results in an increase in the number of processes.

As conventional semiconductor devices with step difference which serves as an indexing pattern, there have been.known (I) a semiconductor device and its manufacture as disclosed in Japanese Patent Applications Laid Open, No. Hei 11-87488, and (2) a semiconductor and its manufacture as disclosed in Japanese Patent Applications Laid Open, No. Hei 11-67894.

In the semiconductor device and its manufacture in (1), the amount of SiO, to be embedded in the trench of the alignment mark region is reduced compared with the other portions, and a wet etching is carried out by covering those portions that are desired not to be reduced in the amount of SiO,. with a resist pattern to reduce in advance the amount of the oxide f ilm in the trench. In the semiconductor device and its manufacture in (2) the situation is handled similarly by reducing the thickness of one part smaller than in other parts.

However, in either of the semiconductor devices and their 12 manufactures in the above, it is necessary to prepare a mask because a part of the film has to be etched back to create a level difference, and it is inevitable to increase the number of lithography and etching processes by one each. In addition, in the case of the semiconductor and its manufacture in (2), the slope of the step part by CMP tends to be in imbalance, and nonuniformitY of the slope in the wafer plane (errors generated being not constant and the precision of alignment cannot be made uniform) tends to occur.

In short, if the increase in the number of processes is suppressed, the alignment precision decreases, and the yield factor of the products drop eventually. On the other hand, to improve the alignment precision, it is necessary to add several processes, including a lithography process, which brings about a rise in the manufacturing cost.

BRIEF SUMMARY OF THE INVENTION

It is an object of the preferred embodiment of the present invention to provide a semiconductor device that enables highprecision alignment without increasing the number of processes in the lithography process for forming a gate.

The semiconductor device according to the present invention has a device section comprising element regions and element isolation regions that isolate the element regions, and an alignment mark section comprising mark formation regions and mark isolation regions that isolate the mark formation regions, where the ratio of the area of the mark formation regions to the area of the mark isolation 13 regions is smaller than the ratio of the area of the element regions to the area of the element isolation regions.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred features of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is a plan view showing an example of the device arrangement of the semiconductor device according to the embodiment of this invention; FIG. 2 is a plan view of the alignment mark section for forming the element regions; FIG. 3 is an explanatory diagram for showing the relation between the remaining film thickness of the silicon nitride film and the data factor when the initial thickness of the silicon is nitride film 15 working as a stopper film is set at 20Onm and the silicon oxide film is subjected to CMP under specified conditions; FIG. 4 (a) to FIG. 4 (c) are process sectional views (part 1) along line A-A' in FIG. 12(a) showing the manufacturing processes of the device section in FIG. 1; FIG. 5(d) to FIG. 5(f) are process sectional views (part 2) along line A-A' in FIG. 12(a) showing the manufacturing processes of the device section in FIG. 1; FIG. 6(g) to FIG. 6(1) are process sectional views (part 3) along line A-A' in FIG. 12(a) showing the manufacturing proces-ses of the device section in FIG. 1, and FIG. 6 (j) is a sectional view along line C-C$ in FIG. 12(a); FIG. 7(a) to FIG. 7(c) are process sectional views (part 1) 14 as seen f acing arrows B and B' in FIG. 2 showing the manuf acturing processes of the alignment mark section in FIG. 1; FIG. 8 (d) to FIG. 8 (f) are process sectional views (part2) as seen f acing arrows B and B in FIG. 2 showing the manuf acturing 5 processes of the alignment -mark section in FIG. 1; FIG. 9 (g) to FIG. 9 (i) are process sectional views (part 3) as seen f acing arrows B and B in FIG. 2 showing the manuf acturing processes of the alignment mark section in FIG. 1; FIG. 10 is a plan view showing another example of the alignment mark section; FIG. 11 is a plan view showing an example of device arrangement in a conventional semiconductor device; FIG. 12 shows an example of a conventional pattern with formed element regions in which FIG. 12 (a) is a plan view of the device section and FIG. 12 (b) is a plan view of the alignment mark section; FIG. 13 (a) to FIG. 13 (c) are process sectional views (part 1) as seen facing arrows B and B' in FIG. 12(b) showing the manufacturing processes of a general trench isolation in a conventional alignment mark; FIG. 14(d) to FIG. 14(f) are process sectional views (part 2) as seen facing arrows B and B' in FIG. 12(b) showing the manufacturing processes of a general trench isolation in a conventional alignment mark; FIG. 15(g) to FIG. 15(i) are process sectional views (part 3) as seen facing arrows B and B' in FIG. 12(b) showing the manufacturing processes of a general trench isolation in a conventional alignment mark; FIG. 16(j) to FIG. 16(1) are process sectional views as seen 30 facing arrows B and B' in FIG. 12 (b) showing a part of the manufacturing processes of a trench isolation in another conventional alignment mark; FIG. 17 is a plan view for illustrating a part of the manufacturing processes in FIG. 16; and FIG. 18 gives a diagram for describing the configuration and the operation of the alignment mark detector.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the drawings, an embodiment of the present invention will be described in the following.

As shown in FIG. 1 which shows a plan view of an example of the device arrangement of the semiconductor device according to the embodiment of the invention, a wafer 100 has a device section 11, a scribe region 13, and alignment mark sections 12 used for overlapping in lithography process. The rectangular device section 11 is demarcated by being surrounded by the scribe region 13, and the alignment mark section 12 is arranged in the scribe region 13 one each on the longitudinal and lateral sides, for example, for each device section 11. A semiconductor device 10 is obtained by cutting the wafer 100 along scribe lines 13a with a scriber, separating the cut piece and forming the piece in a semiconductor chip form, or sealing it in a package. When the wafer 100 is cut along lines deviating from the correct scribe lines 13a, semiconductor device 10 obtained may have alignment marks cut in pieces or missing, but such a piece will also be referred to as a semiconductor device 10 in the following.

The device section 11 has a plurality of element regions juxtaposed in the longitudinal and the lateral directions, and element isolation regions that isolate adjacent element regions (FIG. 12 (a)) - The element regions are formed into a rectangular shape of a lateral width of about 0.20jum and a longitudinal width of about 1.00 pm, and they are arranged adjacent with each other separated by about 0.20,um in the lateral direction and about 0. 60 pm in the longitudinal 5 direction, with their columns arranged staggered alternately. In the device section 11, there are formed a DRAM, a CPU or various kinds of logic circuit.

As shown in FIG. 2 which shows a plan view of the alignment mark section 12, the section 12 has a plurality of element regions 12a as mark formation regions juxtaposed in the lateral direction, and element isolation regions 12b as mark isolation regions isolating adjacent element regions 12a. Each of the element regions 12a is formed, as if it is framed, into a rectangular frame consisting of a pair of left and right longitudinal lines and a pair of top and bottom lines, and they are arranged juxtaposed so as to have the spacing between the center lines of adjacent longitudinal lines of about 6.OOU M.

The data factor of a specified region S in the alignment mark section 12 is about 3.33% if the width of the rectangular frame is assumed to be about 0.2pm. This value is about 1/10 of the data factor of about 31.25% (FIG. 12 (a)) for the specified region S of the pattern in the device section 11. Namely, the alignment mark section 12 is formed such that the area of the element region per unit area is smaller than for the area of the element isolation region. Incidentally, the data factor for the alignment mark section for this embodiment is almost 1/17 of the data factor (about 50%, see FIG. 12(b)) for the conventional alignment mark section. This difference in the data factor brings about a difference in the thickness of the 17 remaining silicon nitride film after CMP in the manufacturing processes of the semiconductor device as will be mentioned later.

In short, in the alignment mark section 12, the ratio of the area of the element region 12a to the area of the element isolation region 12b is made to be smaller than the corresponding ratio for the device'section by forming the area of the element region 12a per unit area to be smaller than the area of the element isolation region 12b per unit area.

FIG. 3 is an explanatory diagram showing the graph between the thickness of the remaining silicon nitride film and the data factor when CMP of the silicon oxide film is carried out under specified conditions for the case of the initial thickness of the silicon nitride film serving as a stopper film of 20Onm.

As shown in FIG. 3, when CMP is conducted under the same conditions, the thickness of the remaining silicon nitride film after the CMP increases with the increase in the data factor, and at a data factor of, for example, about 50% the thickness is about 140nm.

Moreover, the thickness of the remaining film has a larger rate of decrease for a smaller data factor, i.e. a data factor below around 30%,but the rate.of decrease remains slight for the data factor beyond around 30%. For example, the thickness of the remaining film is about 130= for the data factor of about 30%, and about 30nm for the data factor of about 3%, and their difference is almost 100 nm.

In other words, in an element isolation pattern, if there is given a large difference between the data factors of the device section 11 and the alignment mark section 12, and the ratio occupied by the element regions in the alignment mark section 12 is made extremely small compared with the ratio occupied by the element regions in the device section 11, the thickness of the remaining silicon nitride film on the element regions after CMPbecomes small comparedwith the other portions, and the rate of reduction is the larger for the smaller data factor.

In the subsequent manufacturing processes, the conditions for wet etching or the like of the oxide film are set so as to make the height of the surface of the element region of the actual device section to be equal to the height of the surface of the element isolation region. Accordingly, in the alignment mark section 12, the height of the surface of the element isolation region becomes lower compared with the height of the surface of the element region, and there will be generated a sufficiently large level difference that exceeds the detection capability of the level difference detection device, a level dif f erence, f or example, of about 10Onm which is roughly f ive times as large the conventional level difference of about 20= mentioned above.

Next, the manufacturing processes of the semiconductor device in FIG - 1 will be described separately, first for the device section 11, then for the alignment mark section 12.

FIG. 4 illustrates the process sectional views (part 1) along line A-A' in FIG. 12 (a) that shows the manufacturing processes of the device section in FIG. 1, FIG. 5 illustrates similar process sectional views (part 2), and FIG. 6(g) to FIG. 6(i) are similar process sectional views (part 3). FIG.. 6 (j) is a sectional view along line C-C' in FIG. 12 (a) First, on a silicon substrate 14, a silicon oxide film 15 30 is grown by thermal oxidation to a thickness of about 5 to 40nm, 19 preferably to about 20nm, then, a silicon nitride film 16 is grown on top of it by, for example, LPWD to a thickness of about 100 to 250nm, preferably to about 20Orim, and a resist pattern 17 is formed by photolithography in a planned site of formation 5 of the element region (FIG. 4 (a) Next, the silicon nitride film 16 and the silicon oxide film 15 are etched back sequentially and the resist pattern 17 is removed by a dry etching (FIG. 4 (b)). Following that, the silicon substrate 14 is etched to a prescribed depth by a dry etching using the patterned silicon nitride film 16 as a mask to form trenches 18 (FIG. 4 (c)). The depth of the trench 18 is about 200 to 40Onm., preferably about 30Onm. The remaining silicon nitride film will have a thickness of (grown film thickness of 100 to 250nm) - (etched amount of about 10 to 50nm, preferably about 20nm), where (about 10 to 50nm, preferably about 20nm) represents the reduction component of the film.

Next, the inner surface of the trenches 18 are subjected to a thermal oxidation to grow a silicon oxide film 19 to a thickness of about 10 to 30nm, preferably to about 20nmon the inner surface of the trenches 18. Then, in this example, a silicon oxide film 20 is grown to a thickness of about 450 to 650nm., preferably to about 50Onm by a high density plasma oxide f ilm growth method to embed the silicon oxide film 2 0 in the trenches 18 (FIG. 5 (d)).

Next, an unwanted portion of the silicon oxide film 20 is removed, and the remaining silicon nitride film 16 is made to have a thickness of about 100 to 150nm, preferably about 130nm by CMP (FIG. 5 (e)). In this case, due to the difference in the polishing rate between the silicon oxide film 20 and the silicon nitride film 16, the surface of the silicon oxide film 20 will be lower by an amount (A) (20 to 30rLm) than the surface of the silicon nitride film 16. Then, the surface of the silicon oxide film 20 is adjusted by a wet etching to be higher than the surface of the silicon substrate 14 by about 45 to 95nm., preferably by about 75=. For thispurpose, the silicon oxide film 20 has to be etched by an amount (B) (about 75 to 10Onm) After the height adjustment, the silicon nitride film 16 is removed by etching with hot phosphoric acid for about 60 to 100min, preferably for about 80min, and the silicon oxide film on the element region is removed by a wet etching. The condition of the wet etching is the removal of the film by about to 4 Onm, preferably by about 30nm (FIG. 5 (f)).

Next, a silicon oxide film 21 is grown by thermal oxidation once more on the element region to about 10 to 3Onm, preferably to about 20run (FIG. 6 (g)). Then, well formation and channel implantation for adjustment of threshold voltage Vt of the transistor are conducted using the silicon oxide film 21 as a mask, with a lithography process being employed as needed. After that, the silicon oxide f ilm 21 on the element region is removed by a wet etching. The condition f or the wet etching is the removal of the film by about 20 to 40nm, preferably by about 30nm. In this case, due to the difference in the polishing rate of the silicon oxide film 20 and the silicon nitride film 16, the surface of the silicon oxide film 20 will be lower by an amount (A) (about 20 to 30nm) than the surface of the silicon nitride film 16. Furthermore, a silicon oxide film 22 that will serve as a gate oxide film is grown by thermal oxidation on the element region to a thickness of about 6 to 12nm, preferably to about lOnm (FIG. 6 (h) Next, a gate is formed by growing polycrystalline silicon 23 to a thickness of about 50 to 150m, preferably to about 10Onm, 21 and further growing tungsten silicide 24 to a thickness of about 50 to 20Onm, preferably to about 150m (FIG. 6 (i)). Although polycrystalline silicon 23 and tungsten silicide 24 are used in this embodiment, a film of silicide, such as titanium silicide or cobalt silicide, may be employed, or a polymetal film using tungsten or the like may be formed as a metal gate.

FIG. 7 illustrates process sectional views (part 1) as seen facing arrows B and B' in FIG. 2 which shows the manufacturing processes of the alignment mark section in FIG. 1'I FIG. 8 illustrates similar process sectional views (part 2); and FIG. 9 illustrates similar process sectional views (part 3). Repetitive description about processes similar to the manufacturing processes for the device section (FIG. 4 to FIG. 6) above will be omitted.

First, on the silicon substrate 14, the silicon oxide film and the silicon nitride f ilm 16 are grown, and a resist pattern 17 is formed at a planned site for an element region (FIG. 7 (a) Next, after etching sequentially the silicon nitride film 16 and the silicon oxide film 15 and after removal of the resist pattern 17 (FIG. 7(b)), the trench 18 is formed by etching the silicon substrate 14 to a prescribed depth (FIG. 7 (c)). Next, after forming the silicon oxide film 19 on the inner surface of the trenches 18, the silicon oxide film 20 is embedded in the trenches 18 (FIG. 8 (d) The processes in FIG. 7 (a) to FIG. 8 (d) correspond to those in FIG. 4 (a) to FIG. 5 (d), respectively.

Next, an unwanted amount of the silicon oxide film 20 is removed and the thickness of the remaining silicon nitride film 16 is made.about 0 to 50nm by CMP (FIG. 8 (e) Namely, in the alignment mark section 12, the thickness of the remaining silicon nitride 22 film 16 is made to be about 1/4 at the optimum value, compared with the thickness of about 100 to 150nm, preferably about 130nm of the device section 11 (FIG - 5 (e)). In this case, the surface of the silicon oxide film 20 is lower than the surface of the silicon nitride film 16 by an amount (A) (about 20 to 30nm) due to the difference in the etching rate of the silicon oxide film and the silicon nitride film 16. Then, the height of the silicon oxide film 20 is adjusted by a wet etching. The conditions for the wet etching are determined by the conditions for the device section 11, similar to the description in connection with FIG. 5 (f), and about 20 to 40nm of the silicon oxide film 20 is removed.

After the height adjustment, the silicon nitride film 16 is removed, and the silicon oxide film 15 on the element region is removed. In this case, for the complete removal of the silicon oxide film 15 it is necessary to etch the film 15 by more than 40= to ensure overetching,.. considering the variation in the thickness of the silicon oxide film 15. For this reason, the silicon oxide film 20 in the element isolation region has to be etched also to a similar extent (more than 40nm) (FIG. 8(f)). Moreover, the silicon oxide film 21 is grown once more on the element region (FIG. 9(g)). The processes in FIG. 8 (f) and FIG. 9 (g) correspond to those in FIG.

5(f) and FIG. 6 (g), respectively.

After that, the silicon oxide film 21 on the element region is removed by a wet etching with BHF. In this process the silicon oxide film 20 on the element isolation region is also etched to a similar extent (D) (more than 30nm) for a similar reason as above. Furthermore, the silicon oxide film 22 is grown on the element region by thermal oxidation to serve 23 as a gate oxide film (FIG. 9 (h) This process corresponds to the process in FIG. 6 (h). The sum of the etching quantities (B) to (D) amounts to 145 to 170nm. The surface of the silicon oxide film20 becomes lowerby about 165 to 20Onmthan the surface of the silicon nitride film 16 since the height difference (A) has to be added to the sum just mentioned. Moreover, the surface of the silicon oxide film20 as measured fromthe surface of the silicon substrate for the element formation region is lowered by about 110 to 145nm. In this way, a level dif f erence of about 10Onm will be generated between the surface of the gate oxide film 22 and the surface of the silicon oxide film 20 which fills in the element isolation region.

In this manner, alignment marks for aligning the mask for the gate pattern to be formed in the device section 11 are arranged in the scribe region 13. In this case, a level difference of about 10Onm is secured between the element isolation region and the element region, so that the alignment mark detector 32 is able to detect the level difference. In other words, by noting the fact that the thickness of the remaining film of the silicon nitride film after CMP varies depending upon the difference in the data factor, a level difference is formed only in the alignment mark section 12 by reducing to a large extent the data factor of only the alignment mark section 12.

This is an inherent feature of CMP which results from the fact that there exists a slight dif f erence in the abrasion rate in the case of abrading a portion where a pattern is formed densely and in the case of abrading a portion where a pattern is formed sparingly, when conducting a CMP for removing an excess portion in the silicon oxide film 20 embedded in the 24 shallow trench 18 (FIG. 8 (d) Accordingly, with the data factor lowered to about 3%, polishing proceeds at a fast rate owing to the reduction in the area of the element region of the alignment mark secti on 12, with a result of reduction in the thickness of the remaining silicon nitride film 16 after CMP. In the final finished form, there is created level difference of about 10Onm by means of the film formation. In short, in forming an element isolation having the above pattern as a trench isolation, the size of the step between the element isolation region and the element region in the alignment mark section 12 is arranged to be larger than that in the actual device region 11.

As a result, it is possible to obtain a sufficiently large level difference d. larger than the detection capability of the alignment mark detector 32 that is built in an aligner or the like without addition of excess processes as is done conventionally.

The selectivity ratio of the polishing rate in CMP varies depending upon various conditions of slurry, abrasive pad or the like. In the present trench isolation, assuming the selectivity ratio of the polishing rate of the silicon nitride film and the polishing rate of the silicon oxide film to be, for example, 5, the oxide film is easier to polish than the nitride film. In short, the silicon nitride film has a role of polishing stopper for stopping the polishing by CMP. As a polishing stopper a material having a selectivity ratio that is easy to determine is employed.

FIG. 10 is a plan view showing another example 'of the alignment mark section. As shown in FIG. 10, this alignment 30 mark section 25 is obtained by modifying the frame lines of the alignment mark section 12 in FIG. 2 into intermittent broken lines. As a result, it is possible to further cut down the data factor, and the data factor for a prescribed region S of the alignment mark section 25 can be reduced to 1. 66%. In this case, the pattern for the alignment mark section is on a fully usable level, although the signal intensity is weakened to some extent. Moreover, in this case, even for the alignment mark section on one site, a two-dimensional alignment is possible by scanning the light rays i not only in the X direction but also in the Y direction.

In other words, since the integrated output value is used as a signal, the alignment marksare not necessarily in a continuous line form, but may be in a broken line form, provided that a sufficiently large value of the SIN can be secured.

Furthermore, the element region may be formed by a pair of longitudinal frame lines on the left and right which are obtained by removing the pair of lateral frame lines on the top and bottom from the rectangular frame lines. In either case, there occurs no inconvenience in the sense of obtaining positional information through appearance of a peak, and moreover, it is possible to arbitrarily adjust the data factor by varying the width of the longitudinal frame line.

As in the above, according to this invention, a difference in the thickness of the remaining film working as a polishing stopper filmcanbe generatedin theprocess after CMPbyvarying the data factor through modification in the arrangement of the mask pattern. Thus, in the final finished form of the gate oxide film, a level dif f erence of about 10Onm can be generated in the alignment mark section 12, although it is flat in the device section. Accordingly, it is possible to automatically 26 form a level difference fully utilizable for indexing even without a change in the actual manufacturing processes, namely, without addition of processes.

Moreover, in the conventional method, there was generated a difference in the slopes of the left and right element regions during CMP, and an error tended to be generated in pinpointing the center position of the element region, because of a large width of 6[im in the element region. However, according to this invention, the width of the element region has a small value of 0. 2 pm so that the left and right slopes of the element region in FIG. 9 (i) are almost equal, and the error in locating the center position of the element region can be reduced.

In the above embodiment, the level difference (see FIG. 9 (h)) obtained between the surface of the gate oxide film 22 and the surf ace of the silicon oxide f ilm 20 that f ills in the element isolation region is not limited to 10Onm, and it only need be a level difference larger than the detection capability of the alignment mark detector 32 built in the aligner or the like employed. Accordingly, the level difference required can be made small if the detection capability of the alignment mark detector 32 built in the aligner or the like is enhanced.

Moreover, since the data factor varies depending upon the conditions of CMP and the material combination of the stopper film, the relation between the thickness of the remaining silicon nitride film and the data factor for CMP (FIG. 3) will vary with the change in the data factor. Moreover, the data factor may be set at a prescribed value by forming dummy element regions or element isolation regions within the device section. 30 Moreover, the above embodiment has been described with a DRAM 27 as an example, but this invention is not limited to that case, and it can be applied to semiconductor devices such as a microcomputer or an application- specific integrated circuit (ASIC).

Furthermore, the above embodiment has been described with the element region or the element isolation region as an example, but this invention is not limited to that case, and it can be applied to a process as long as it is a process in which a level difference is formed based on the difference in the data factor as in a wiring process.

As described above, according to the invention the ratio of the element region to the element isolation region for the alignment mark section is made smaller than in the device section. Accordingly, in the lithography process for forming a gate in the manufacture of a semiconductor device, it is possible to form alignment marks without increasing the number of processes, and to perform alignment with high precision.

Although the invention has been described with reference to a specific embodiment, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment will become apparent to persons skilled in the art upon reference to the description of the invention. it is therefore contemplated that the appended claims will cover any modifications or embodiments as fall within the true scope of the invention.

Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

The text of the abstract filed herewith is repeated here as 28 part of the specification.

A semiconductor device has a device section consisting of element regions and element isolation regions that isolate the element regions, and an alignment mark section consisting of mark formation regions and mark isolation regions that isolate the mark formation regions. The ratio of the mark formation regions to the mark isolation regions is smaller than the ratio of the element regions to the element isolation regions.

Claims

29 CLAIMS:

1. A semiconductor device comprising a device section having element regions and element isolation regions for isolating said element regions, and an alignment mark section having mark formation regions and mark isolation regions for isolating said mark formation regions, wherein the ratio of the area of said mark formation regions to the area of said mark isolation regions is smaller than the ratio of the area of said element regions to the area of said element isolation regions.

2. The semiconductor device as claimed in claim 1, wherein said mark formation region is formed in a rectangular frame shape.

3. The semiconductor device as claimed in claim 1, wherein the level difference generated by the difference in the height of the surface of the mark formation region and the height of the surface of the make isolation region is larger than the value of the detection capability of an alignment mark detector.

4. The semiconductor device as claimed in claim 1, wherein said element regions and said mark formation regions are isolated by a trench isolation structure.

5. A semiconductor device having a device section consisting of first regions and second regions, and an alignment mark section consisting of third regions and fourth regions formed in respectively identical processes for said first regions and said second regions, the area ratio of said third regions compared to the sum of said third regions and said fourth regions being smaller than the area ratio of said first regions compared to the sum of said first regions and said second regions.

6. The semiconductor device as claimed in claim 3, further comprising a film with high reflectance that covers said level difference.

7. The semiconductor device as claimed in claim 6, wherein said film with high reflectance is a silicide film or a metallic film.

8. A semiconductor device substantially as herein described with reference to and as shown in Figures 1 to 10 of the accompanying drawings.