GB2360155A - Switched current sources - Google Patents

Switched current sources Download PDF

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Publication number
GB2360155A
GB2360155A GB0005486A GB0005486A GB2360155A GB 2360155 A GB2360155 A GB 2360155A GB 0005486 A GB0005486 A GB 0005486A GB 0005486 A GB0005486 A GB 0005486A GB 2360155 A GB2360155 A GB 2360155A
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Patent type
Prior art keywords
source
current
mode
switches
switch
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Granted
Application number
GB0005486A
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GB2360155B (en )
GB0005486D0 (en )
Inventor
David Mark Chapman
Martin Andrew Fryer
Dominic Charles Royce
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Nokia of America Corp
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Nokia of America Corp
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Publication date

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Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895Details of the current generators

Abstract

A switched current source, which may be used in a charge pump, has an active mode of operation in which output current is supplied, and an inactive mode of operation in which output current is not supplied, wherein sub- threshold conduction in the inactive mode in the main current paths of the source is greatly reduced relative to prior proposals. The current source comprises first and second MOSFETS 20, 22 forming a complementary pair, each transistor having a gate 28, 30 for controlling the magnitude of current in the main current path each transistor having first switches 34-40 for selectively switching the gate to a state, in the inactive mode, in which the transistor is off; and second switches 60-70 for selectively switching into the main current path in the inactive mode, a respective voltage source 64, 66 for reducing current leakage in the main current path. A control unit 74 responds to the switching of first switches 34-40 to subsequently switch second switches 60-70 to reduce stray capacitive effects. The offset voltage sources could be realised through the use of resistors in series (R1,R2, and R3 fig 4). A standby mode is disclosed in which the switches are set in the same way as in the reduced leakage mode except that voltage sources VPOFFSET and VNOFFSET 64, 66 and PBIAS and NBIAS inputs are also shut down, and switches 34, 36, 68, 70, opened, to save power.

Description

1 Switched Current Sources 2360155 The present invention relates to

switched current sources, having an active mode of operation in which output current is supplied, and an inactive mode of operation in which output current is not supplied.

There are many applications of switched current sources such as digital to analogue converters and charge pumps in phase locked loop (PLL) synthesisers (for example as used in handsets of mobile stations in mobile telecommunication systems). Some applications need up and down drive, some only drive one way. By way of explanatior4 reference is made to Figure 1 which illustrates the concept of using an up and down charge pump in a PLL synthesiser. A reference oscillator 2 is provides a reference frequency to a divider 4 which in turn provides a comparison frequency to a phase comparator 6. Phase comparator 6 also accepts for comparison a divided down version of the output frequency of a voltage controlled oscillator (VCO) 8, divided down by a well known dividing arrangement 10 comprising main divider, swallow counter and prescaler. The phase comparator 6 provides an error signal, which drives an up and down charge pump 12, which in turn supplies current to charge capacitance in a loop filter 14, loop filter 14 providing a stable voltage to hold WO 8 at a desired operating frequency.

The PLL Synthesiser uses the loop continuously in order to settle to the required output frequency and to maintain that frequency; it then shuts down the whole loop when the activity is complete. Some applications require the loop control voltage to stay correct and the WO to stay at the correct frequency for some finite time after the loop is partly shut down. There are several possible reasons for this' requirement. In each case the need is for the charge pump 12 to go to a very low leakage state, the loop filter 14 to use low leakage components and the WO 8 to have very low leakage.

Previous charge pumps as used in such a PLL Synthesiser are usually one of two designs, as shown in Figures 2a and 2b.

The charge pumps shown in figures 2a and 2b both employ a complementary pair of enhancement mode p and n type MOSFET transistors 20, 22, with their main current paths connected in series across drain VIDD and source VSS power supply rails 24, 26. Control voltages PBIAS and NBIAS 16, 18 are applied from a bias generator (not shown) to respective control gates 28, 30. An output 32 is provided to the loop filter from a nodal point between the main current paths of the transistors. In Figure 2a, switches 34, 36 are provided in the gate electrode paths, and switches 38, 40 are coupled 2 between the gate electrode and either supply rail 24, 26; switches 34-40 are controlled by the phase comparator 6. In Figure 2b, further p and n type enhancement mode transistors 42, 44 are coupled in the series current path between the supply rails 24, 26, and are arranged to be switched, under control of the phase comparator 6, by connection of their gate electrodes to the supply rail voltages 5 VDD or VSS.

The charge pumps of Figures 2a and 2b operate both in an active mode in which current is supplied from the output 32, and in an inactive mode in which current is not supplied from the output, and the transistors 20, 22 are set to provide minimum current leakage in their main current paths. Thus in Figure 2a, in the active mode of operation, the bias voltages PB1AS and NBIAS control transistors 20, 22 to give whatever current is required from the charge pump when driving up or down. The output MOSFET gates 28, 30 are switched by switches 34-40 (normally implemented as small MOSFETs) between the bias voltages (switches 34, 36 closed) and either VDD or VSS (switches 38, 40 closed) such that the current is on or off. In the inactive mode, switches 38, 40 are permanently ON to put Ves at zero volts. For many applications this works very well but there is a significant sub-threshold conduction (- 1 nanoamp) in the output MOSFETs 20, 22 main current paths in the inactive mode, which sets a minimum for the off current.

In operation of figure 2b the voltages on PB1AS and NBIAS are again set up, but are connected permanently to the current setting MOSFET gates 28, 30. Each transistor 20, 22 is switched on or off by series switches 42, 44 in the active mode of operation to give desired current at output 32. These switches are driven by the full supply voltage VDD-VSS and so can be smaller that the current setting MOSFET's 20, 22. Therefore in the inactive mode of operation a smaller sub-threshold current is provided. However, any charge stored on a node 50, 52 between the switch 42, 44 and the respective current setting MOSFET 20, 22 in the inactive mode can give some undesired transient effects when the next active mode period starts, which will in turn give unacceptable levels of comparison frequency spurs. Further, as typical supply voltages get smaller (-2-3V), the advantage of the small transistors 42, 44 will reduce since their size must increase for efficient switching, and hence the sub-threshold conduction will also increase.

It can be seen that neither option can give an extremely low off-state leakage current as needed in some applications.

SUMMARY OF THE EWENTION

It is an object of the invention to provide a switched current source in which the problems of leakage current in an inactive mode of operation are substantially reduced.

3 The present invention provides a switched current source, having an active mode of operation in which output current is supplied, and an inactive mode of operation in which output current is not supplied, the current source comprising: a transistor means having a control electrode for controlling the magnitude of current in a main current path: a control electrode switch means. for selectively switching the control electrode to a state, in the inactive mode, in which the transistor means is off, and a voltage source switch means for selectively switching into said main current path, in the inactive mode, a voltage source for reducing current leakage in the main current path.

As preferred, the transistor means is an enhancement mode MOSFET, and a second transistor means, comprising an enhancement mode MOSFET of opposite type, forms a complementary pair with the first MOSFET. As preferred, the second MOSFET has a control electrode switch means for selectively switching the gate electrode to a state in which the transistor is off, and a voltage source switch means for selectively switching into its main current path in the inactive mode, a voltage is source for reducing current leakage in the main current path.

In accordance with the invention, in order to reduce sub-threshold conduction leakage current in the inactive mode, two measures are provided: 1. A control electrode switch means selectively switches the control electrode to a state in which the transistor means is off. For an enhancement mode MOSFET, the gate electrode is put to the same voltage as the source so that VGs is zero, which is a state of least conduction for the main current path. In the applications of interest, it is not normally possible to put the gate electrode to a voltage out of the range of supply voltage so as to reduce the conduction still further. 2. A voltage source switch means selectively switches into said main current path, in the inactive mode, a voltage source for reducing current leakage in the main current path. By inserting a voltage source of appropriate polarity into the main current path, the source is biassed relative to the gate,. to minimize leakage current. However, in view of the low overall power supply voltages in the applications of interest, the voltage is switched out of the main current path in the active mode of operation, in order to increase the available voltage and currents in the main current path.

Thus, the problems of the prior art can be overcome. In particular the leakage of the circuit of

Figure 2a is avoided, and the stray capacitive effects of Figure 2b may be avoided, since the switching in the main current path may occur only after the transistors are switched off via their gate electrodes.

4 In accordance with the invention, it is possible to reduce the subthreshold conduction to a negligible value, e.g. -50 pico amps. Further the present invention can be implemented inexpensively.

Brief Description of the Drawings

A preferred embodiment of the invention will now be described with reference to the accompanying drawings, wherein:

Figure 1 is a schematic block diagram of a known type of PLI, synthesiser, and employing a charge pump; Figure 2a and 2b are schematic circuit diagrams of known types of charge pump switched current sources; Figure 3 is a circuit diagram of a switched current source in accordance with the invention; and Figure 4 is a more detailed circuit diagram of the embodiment of Figure 3.

Description of the Preferred Embodiment is Referring to Figure 3, similar parts to those shown in Figures 2 are denoted by the same reference numerals. Transistor switches 60, 62 (p and n " enhancement mode MOSFETs), designated PCLAW and NCLAW, are connected between the respective supply rails 24, 26 and transistors 20, 22. Voltage sources 64, 66 WOFFSET and VNOFFSET are connected in series with respective switches 68, 70 in conduction paths, in parallel with respective switches 60, 62. The phase comparator provides control signals on lines 76 to control switches 3440, and a control unit 74, actuated by an initiate signal on line 72, provides control signals on lines 78 to control switches 60 70. Some or all of control lines 76 from phase comparator 6 to switches 34 - 40 also drive control unit 74.

In add ition to the above described active and inactive modes of operation, the circuit of Figure 3 provides a third mode, a low power-or standby mode. The operation of the circuit is as follows:

1. Active Charge Pqm ping Mode: Transistor switch PCLAMP 60 is held continuously on by signals on lines 76 connecting its gate to the VSS supply rail 26. Transistor switch NCLAW 62 is held continuously on by signals on lines 76 connecting its gate to VDD supply rail 24. Both Low Leakage Mode switches 68, 70 are open so that WOFFSET and VNOFFSET voltage sources 64, 66 are isolated. The voltages PB1AS and NBIAS 16, 18 are driven to the correct voltage by a bias generator for the required output current. The ON and OFF switches 34 - 40 are controlled by lines 76 so that biasses PB1AS and NBIAS are applied for selected periods of time for transistors 20, 22 to give current pulses at the output 32. The switches 60, 62 PCLAMP and NCLAW have adequately low ON resistance such that the voltage drop across their main current path VDs-oN is insignificant in the compliance range of the charge pump; otherwise, there may be insufficient voltage drop across transistors 20, 22 for correct operation. The two voltage sources 64, 66 VPOFFSET and VNOFFSET are set up ready for the mode to follow.

Low Leakne (Inactive) Mode: An initiate signal on line 72 actuates control unit 74. Phase comparator 6 provides control signals on lines 76 so that PCLAMP switch 60 is switched off by connecting its gate electrode to the VDD supply rail 24, and NCLAW switch 62 is switched off by connecting its gate to VSS supply rail 26. Signals on lines 76 also gate control unit 74 so that, subsequently, control unit 74 provides signals on lines 78 so that both Low Leakage Mode switches i o 68, 70 are closed so that voltage sources 64, 66 are operativeand switches 60, 62 are effectively shorted out. Hence leakage in the main current paths of switches 60, 62 will not affect leakage current at OUTPUT 32 in this Low Leakage Mode. ON and OFF switches 34 -40 are all set to give no current into the output, switches 3 8, 40 being closed to connect the gate to the source voltage.

Thus, when a request to start thelow leakage mode is received on line 72 it is not acted on until the current setting MOSFETs 20, 22 are both known to be in the off state. At this time lines 78 will drive PCLAW and NCLAW 60, 62 and switches 68, 70 to select the low leakage mode. Alternatively it is possible to generate a signal in the reference divider 4 at a time point well separated from the phase comparison point and use this in place of lines 76 to set the timing of logic block 74. Which implementation is best will depend on fine details of the design of a PLL using this low leakage mode.

With this approach the leakage current seen at the output is set solely by the sub-threshold conduction of the current setting MOSFETs 20, 22 and this is very much reduced due to the shift in source bias voltage by the VPOFFSET and VNOFFSET voltage sources 64, 66. Any leakage in the PCLAW and NCLAMP MOSFETs 60, 62 does not affect the output and is fed by the VPOFFSET and VNOFFSET voltage sources. The two bias voltages PBIAS and NBIAS are set up for the state following the period of Low Leakage.

It will be noted that in order to avoid capacitive effect problems noted for Figure 2b, this low leakage mode is entered (control unit 74 controlling switches 60-70) only when the output current is off (as determined by control unit 74 controlling switches 334-40)and not at all during the normal PLL settling time. Thus, for best performance by avoiding glitches the timing of the change of mode from Active Charge Pumping to Low Leakage Mode should be when the ON and OFF switches 34 -40 are set to give no output current.

6 Low Power or Standby Mode: In this mode, the switches are set the same as for Low Leakage Mode except that the voltage sources WOFFSET and VNOFFSET 64, 66 and PWAS and NBIAS inputs are also shut down, and switches 34, 36, 68, 70 opened, to save power.

is One specific implementation of the offset voltage sources 64, 66 is a chain of resistors as shown in Figure 4, comprising resistors R I, R3, R2 series connected with a transistor switch 80. Resistor R1 constitutes source 64, WOFFSET, and resistor R2 constitutes voltage source 66, VNOFFSET. The values of R1 and R2 can be the same or different and if different can be adjusted to allow for the different threshold voltages of the p-channel and n-channel Current setting MOSFETs 20, 22 to give io matched sub-threshold low leakage. R3 is included if the two offset voltages do not sum to the supply voltage VDD - VSS. In many applications, R3 is zero. The MOSFET ENABLE switch 80 is used to shut off the voltage offsets in Low Power or Standby state. Many other circuit arrangements can be used to give suitable offset voltages, including the use of VSS for WOFFSET and VD1) for VNOFFSET, as indicated in chain dotted lines 82, 84.

Thus there has been shown and described a switched current source which may be used in Charge Pumps in PLL Synthesisers, Digital to Analog Converters and other applications. Problems of the prior art are avoided in that sub-threshold conduction is minimized by moving the output MOSFETs' sources voltages away from supply or ground. It solves the problem of getting very low leakage current and is straightforward and low cost to implement. Different bias shifts can be used for the p- and n-channel outputs of a complementary pair of MOSFETs to allow for different threshold voltages. Good driving performance is maintained by using mode dependent source bias (VPOFFSET, VNOFFSET or VDD, VSS via PCLAW, NCLAW). Clean switching between modes is effected by only switching when the output is not driving.

7

Claims (14)

1. A switched current source, having an active mode of operation in which output current is supplied, and an inactive mode of operation in which output current is not supplied, the current source comprising: a transistor means having a control electrode for controlling the magnitude of current in a main current path: a control electrode switch means for selectively switching the control electrode to a state, in the inactive mode, in which the transistor means is off, and a voltage source switch means for selectively switching into said main current path, in the inactive mode, a voltage source for reducing current leakage in the main current path.
2. A source according to claim 1, including a second transistor means having a control electrode for controlling the magnitude of current in its main current path, the main current paths of the firstmentioned and second transistor means being connected in series, with output current being provided from between the main current paths, and wherein the second transistor means has a control electrode switch means for selectively switching the control electrode to a state, in the inactive mode, in which the transistor means is off, and a voltage source switch means for selectively switching into its main current path in the inactive mode, a voltage source for reducing current leakage in the main current path-
3. A source according to claim 1 or 2, wherein the first mentioned transistor means is an enhancement mode MOSFET.
4. A source according to claim 2, wherein the first mentioned transistor means is an enhancement mode MOSFET, and the second transistor means comprises an enhancement mode MOSFET of opposite type, forming a complementary pair with the first MOSFET.
5. A source according to any preceding claim, wherein the or each said voltage source switch means comprises a first switch disposed between the main current source of the respective transistor means and a power supply rail, and a path in parallel with the first switch including the voltage source and a second switch.
8
6. A source according to any preceding claim wherein the or each voltage source is provided by a resistance drawing current from a power supply rail.
7. A source according to claim 2, wherein the first mentioned and second mentioned voltage sources are provided by a series chain of resistors connected in series across the power supply rails of the source.
8. A source according to claim 7, including a switch means connected in said series chain of resistors for switching off in a low power mode of operation.
9. A source according to claim 2, wherein the first mentioned and second mentioned voltage sources have different values, each matched to the characteristics of the respective first and second transistor means.
10. A source according to any of claims 1 to 5, wherein the or each voltage source is provided by the power supply rail of the current source opposite to the rail to which the main current path of the first mentioned transistor means is connected.
11. A source according to any preceding claim, wherein said control electrode switch means comprises a switch connected in the control signal path to the control electrode, and a switch connected between the control electrode and a power supply rail of the source.
12. A source according to claim 5, wherein the source has a low power mode of operation in which said first and second switches are both in an off condition.
13 A source according to any preceding claim, including means for ensuring that the control electrode switch means is operative to switch off the transistor Tneans, before entering the inactive mode of operation for reducing capacitive effects.
14. A switched current source, substantially as hereinbefore described with reference to Figures 3 or 4 of the accompanying drawings.
GB0005486A 2000-03-07 2000-03-07 Switched current sources Expired - Fee Related GB2360155B (en)

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GB2360155A true true GB2360155A (en) 2001-09-12
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10252618A1 (en) * 2002-11-11 2004-05-27 Infineon Technologies Ag Circuit arrangement for a charging pump for phase locked loops has alternative path for output potential according to switching condition
US6888386B2 (en) * 2002-04-23 2005-05-03 Winbond Electronics Corporation Method and apparatus for change pump circuit
WO2009117708A1 (en) * 2008-03-21 2009-09-24 Qualcomm Incorporated Stepped gain mixer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473283A (en) * 1994-11-07 1995-12-05 National Semiconductor Corporation Cascode switched charge pump circuit
US5825640A (en) * 1997-06-30 1998-10-20 Motorola, Inc. Charge pump circuit and method
US5861766A (en) * 1997-04-17 1999-01-19 Western Digital Corporation Multimode frequency synthesizer having high loop gain in frequency seek mode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473283A (en) * 1994-11-07 1995-12-05 National Semiconductor Corporation Cascode switched charge pump circuit
US5861766A (en) * 1997-04-17 1999-01-19 Western Digital Corporation Multimode frequency synthesizer having high loop gain in frequency seek mode
US5825640A (en) * 1997-06-30 1998-10-20 Motorola, Inc. Charge pump circuit and method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888386B2 (en) * 2002-04-23 2005-05-03 Winbond Electronics Corporation Method and apparatus for change pump circuit
DE10252618A1 (en) * 2002-11-11 2004-05-27 Infineon Technologies Ag Circuit arrangement for a charging pump for phase locked loops has alternative path for output potential according to switching condition
WO2009117708A1 (en) * 2008-03-21 2009-09-24 Qualcomm Incorporated Stepped gain mixer
US8229043B2 (en) 2008-03-21 2012-07-24 Qualcomm Incorporated Stepped gain mixer
KR101203440B1 (en) 2008-03-21 2012-11-21 퀄컴 인코포레이티드 Stepped gain mixer
KR101256772B1 (en) 2008-03-21 2013-04-25 퀄컴 인코포레이티드 Stepped gain mixer

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GB2360155B (en) 2003-10-01 grant
GB0005486D0 (en) 2000-04-26 grant

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