JPH0833321A - Booster circuit - Google Patents

Abstract

PURPOSE:To provide a booster circuit in which the loss is reduced through simple circuitry by controlling the switching of series and parallel connection of a plurality of capacitors charged with high voltage using only a low voltage clock signal. CONSTITUTION:Capacitors 31-33 are charged in parallel by turning NMOS transistors 41-43 ON and turning PMOS transistors 51-53 OFF. When the NMOS transistors 41-43 are then turned OFF and the PMOS transistors 53 is turned ON, a power supply voltage VCC appears at a joint 76 and the voltage at a joint 73 is boosted to the sum of the voltage of the capacitor 33 and the power supply voltage VCC. Since the gate voltage of the PMOS transistors 52 drops below the source voltage thereof, the PMOS transistor is turned ON and the PMOS transistor 51 is also turned ON to connect the capacitors 31, 32, 33 in series. Consequently, high voltage at the joint 71 can be obtained from an output terminal 62 through a rectifying circuit 61.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit for generating a high voltage higher than a power supply voltage in a short time.

[0002]

2. Description of the Related Art As one of the booster circuits used conventionally, there is known a booster circuit using a charge pump for sequentially transferring the charge charged in a capacitor to the next capacitor to boost the charge. FIG. 4 is a circuit diagram showing an example of a booster circuit using a conventional charge pump. In the figure,
101 is a power supply terminal, 102 is an output terminal, 103 is a first clock terminal, 104 is a second clock terminal, 105-
107 is a connection point, 111-114 are diodes, 121
˜124 are capacitors.

The diodes 111 to 114 are connected in series, and the connecting points 105 to 107 connect the capacitors 1 to
21 to 123, and a capacitor 124 is connected to the output of the diode 114. The power supply voltage VCC is supplied to the power supply terminal 101. In addition, the first clock terminal 103 and the second clock terminal 104,
Two-phase clocks Φ1, Φ2 having a phase difference of 180 degrees are respectively supplied. This two-phase clock Φ1, Φ2
Is boosted in conjunction with.

The charges supplied from the power supply terminal 101 to the connection point 105 through the diode 111 are accumulated in the capacitor 121 when the clock φ1 is 0V. Then, the clock Φ1 becomes the power supply voltage VCC, and the clock Φ2 becomes 0.
When it reaches V, it is transferred to the connection point 106 through the diode 112 and stored in the capacitor 122. At this time,
By the voltage VCC of the clock Φ1 and the voltage VCC due to the electric charge accumulated in the capacitor 121,
The voltage of 22 is boosted to 2 VCC. Similarly, the voltage is boosted to the capacitors 123 and 124 by repeating accumulation and transfer, and an output voltage 5VCC that is about 5 times the power supply voltage is obtained at the output terminal 102. According to such a booster circuit, since a high voltage can be obtained without using a transformer or the like, the power supply can be downsized and the cost can be reduced.

By the way, in the booster circuit shown in FIG. 4, as a method of obtaining a higher voltage, it is conceivable to simply increase the number of stages. However, in this way the charge is
In the method of step transfer and boosting, the higher the voltage, the longer it takes to obtain the desired voltage.
Therefore, in order to obtain a high voltage faster, a circuit is conceivable in which a plurality of stages of the booster circuit shown in FIG. 4 are used to boost the voltage in parallel and the final stage capacitor is connected in series to obtain the high voltage. There is.

FIG. 5 is a circuit diagram showing another example of the conventional booster circuit. In the figure, 131 to 133 are boosting blocks, 1
Reference numerals 41 to 143 are diodes, 151 to 153 are capacitors, 161 to 163 are N channel MOS transistor switches, 171 to 173 are P channel MOS transistor switches, 181 is a step-up inverting circuit, 182 is a rectifying circuit, 191 is an output terminal, and 192. Is a first clock terminal, 193 is a second clock terminal, and 194 to 196 are connection points.

The boosting blocks 131 to 133 are circuits for obtaining a high voltage equal to or higher than the power supply voltage, and are composed of the boosting circuit shown in FIG. 4, for example. Boosting blocks 131 to 1
The output of 33 is connected to capacitors 151-153 via diodes 141-143. N-channel MOS transistor switches 161 to 163 are provided at terminals on the opposite side of the capacitors 151 to 153, respectively.
P-channel MOS transistor switches 171-17
3 are connected in parallel. The N-channel MOS transistor switches 161 to 163 are respectively connected to the ground VSS and controlled by the second clock signal Φ2 supplied to the gate. The P-channel MOS transistor switches 171 to 173 are connected to the capacitor 152, the capacitor 153, and the power supply, respectively, and are controlled by the first clock signal Φ1 supplied to the gate via the boosting inverting circuit 181. . The boosting inverting circuit 181 is a circuit for boosting the first clock signal Φ1. The first clock signal Φ input from the first clock terminal 192 and the second clock terminal 193
The first and second clock signals Φ2 are clock signals that have a phase difference of 180 degrees and do not overlap. Capacitor 15
The voltage at the connection point 194 between 1 and the diode 141 is output from the output terminal 191 via the rectifier circuit 182.

Next, the operation of this circuit will be described. The second clock signal Φ2 is the power supply voltage, that is, N channel M
While the OS transistor switches 161 to 163 are on, the booster blocks 131 to 133 cause the power supply voltage VCC to rise.
The high voltage boosted above is the diodes 141 to 143.
Through capacitors 151 to 153 to charge the connection points 194 to 196 to V1 to V3, respectively. At this time, although the first clock signal Φ1 is 0V, it is inverted by the step-up inverting circuit 181 and a voltage equal to or higher than the output voltage of the step-up block is supplied to the P-channel MOS transistor switches 171 to 173. Channel MO
The S transistor switches 171 to 173 are off. Next, when the N-channel MOS transistor switches 161 to 163 are turned off and then the P-channel MOS transistor switches 171 to 173 are turned on, the capacitors 151 to 153 are connected in series, and the connection point 19
4 to 196 voltages V1 to V3 and VCC (V
1 + V2 + V3 + VCC) is output from the output terminal 191 through the rectifier circuit 182.

Thus, when a higher voltage is to be obtained, the boosting rate can be increased several times by connecting the capacitors at the final stage of the boosting blocks in series, and the number of stages of each boosting block can be increased. High voltage can be obtained without. Therefore, according to this circuit, a high voltage can be obtained in a short time.

By the way, in such a booster circuit, a MOS transistor is used as a switching element as shown in FIG. 5 for the purpose of integration and low power consumption. Therefore, in order to reliably perform the switching operation of the high voltages V1 to V3 boosted to the power source voltage or more by the boosting blocks 131 to 133, the gate control signals of the P channel MOS transistor switches 171 to 173 are set to V.
It must be 1 to V3 or more. Now, V1 = V2 = V
3 = VDD (> VCC). While the N-channel MOS transistor switches 161 and 162 are on, the P-channel MOS transistor switch 171 cuts off the current path between the connection points 195 and 196 to which the high voltage is applied by the boosting blocks 132 and 133 and the ground potential. , 172 must be turned off. Therefore, in order to cut off the potential VDD between the source and the drain, the P-channel MOS transistor switch 171,
It is necessary to apply a voltage of VDD-Vthp or higher to the gate of 172. Where Vthp is a P channel MOS
It is the threshold voltage of the transistor. Normally, VDD is higher than the power supply voltage VCC. Therefore, in the circuit shown in FIG. 5, the boosting inverting circuit 181 boosts the clock signal voltage VCC to VDD-Vthp or higher and applies it to the gate.

As described above, if the outputs of a plurality of boosting blocks are connected in series to obtain a high voltage, a circuit for boosting the clock signal above the output voltage of each boosting block is required, and the circuit configuration becomes complicated. . Further, in the circuit shown in FIG. 5, when the capacitors are connected in parallel to series, P
Channel MOS transistor switches 171 to 173
Since it is operated individually, it is necessary to supply a control signal to each of them, which complicates the switching mechanism. Furthermore,
For some reason, the output voltage of the boost block rises,
P-channel MOS transistor switches 171-17
If the drain voltage of any one of 3 becomes higher than the gate control signal, the P-channel MOS transistor cannot maintain the off state, resulting in a large loss in switching.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and a plurality of capacitors charged at a voltage higher than the power supply voltage are switched from parallel connection to series connection to generate a higher voltage. In the booster circuit to be obtained, a field effect transistor is used for controlling parallel connection and switching from parallel connection to series connection or from serial connection to parallel connection, and control of connection and switching in such a configuration is controlled by a clock signal below a power supply voltage. It is an object of the present invention to provide a booster circuit that can be performed only by itself, does not require a complicated switching mechanism, and has less connection loss due to switching.

[0013]

According to the present invention, in a booster circuit for switching a plurality of capacitors charged at a voltage higher than a power supply voltage from a parallel connection to a series connection to obtain a higher voltage, a voltage higher than the power supply voltage is used. And a rectifying element connected to the output of the boosting block,
A first field-effect transistor connected to the rectifying element, a first field-effect transistor connected to the capacitor for connecting / disconnecting the ground according to a second control signal, and a second field-effect transistor connected to the capacitor. N circuit blocks are provided, and the second field effect transistor of the 1st to N-1th circuit blocks is connected to the rectifying element and the capacitor of the next circuit block, and the gate thereof is a booster of the next circuit block. The second field effect transistor of the Nth circuit block is connected to the output of the block, the second field effect transistor of the Nth circuit block is connected to the power supply, and the first control signal is input to the gate of the second field effect transistor. It is characterized in that an output is taken out from a connection point of the rectifying element and the capacitor.

[0014]

According to the present invention, by operating the first field effect transistor and grounding one end of the capacitor,
The output voltage from each boosting block is held in the capacitor. At this time, when a signal of about the power supply voltage, for example, is input as the first control signal to the second field effect transistor of the Nth circuit block, the second field effect transistor is turned off. Second of the 1st to N-1th circuit blocks
Since the output voltage from each step-up block is applied to the gate of the field-effect transistor, the field-effect transistor is turned off.

When the first field effect transistor is turned off and the second field effect transistor of the Nth circuit block is turned on after the completion of the boosting by each boosting block, the source voltage of each second field effect transistor is changed. As the gate voltage rises and the relative gate voltage decreases, the second field effect transistors of the 1st to N-1th circuit blocks are also turned on.
As a result, the capacitors holding the voltage boosted by each boosting block are connected in series, and a voltage higher than the voltage generated in each boosting block can be taken out.

As described above, when the capacitors are switched from parallel to series, all the second field effect transistors are turned on by simply turning on the second field effect transistors of the Nth circuit block. The voltage may be given as the first clock signal. Therefore, there is no need for a circuit for boosting the clock signal as in the prior art, and a booster circuit that can obtain a high voltage in a short time can be realized with a simple configuration. In addition, the second field effect transistor of the Nth circuit block can be switched in a chained manner only by turning on the second field effect transistor, so that the switching mechanism can be simplified. it can. Furthermore, when connecting capacitors in parallel,
Since the current path formed between the high voltage and the ground potential by the second field effect transistor is cut off by the high voltage output from the boosting block itself, the high voltage is surely cut off. Therefore, a booster circuit with less connection loss can be realized with a simple configuration.

[0017]

1 is a circuit diagram showing an embodiment of a booster circuit according to the present invention. In the figure, 11 to 13 are boosting blocks, 21
-24 are diodes, 31-36 are capacitors, 41-
43 is an N-channel MOS transistor switch, 51
~ 53 is P channel MOS transistor switch, 6
1 is a rectifier circuit, 62 is an output terminal, 63 is a first clock signal terminal, 64 is a second clock signal terminal, 71-76
Is the connection point.

Each of boosting blocks 11 to 13 generates a voltage higher than the power supply voltage. Each boost block 11
The outputs of ˜13 are connected to the anodes of the diodes 21-23, respectively. In addition, the boosting blocks 12, 1
3 outputs the capacitors 34 and 35 and the P channel MOS transistor switches 51 and 5 respectively.
It is also connected to the 2nd gate. Capacitors 34 and 35
The other terminal of is grounded.

The cathodes of the diodes 21 to 23 are connected to one terminals of the capacitors 31 to 33, and the cathodes of the diodes 22 and 23 are further P-channel MO.
It is also connected to the sources of the S transistor switches 51 and 52. These connection points are referred to as connection points 71 to 73, respectively. The other terminals of the capacitors 31 to 33 are connected to the drains of the P channel MOS transistor switches 51 to 53 and the drains of the N channel MOS transistor switches 41 to 43. These connection points are referred to as connection points 74 to 76, respectively.

The P-channel MOS transistor switches 51 to 53 function to switch between parallel and series connection of the capacitors 31 to 33. The connection between the P-channel MOS transistor switches 51 and 52 is as described above. P
The gate of the channel MOS transistor switch 53 is connected to the first clock signal terminal 63, and the P channel MOS transistor switch 53 is controlled by the first clock signal. The power supply voltage is applied to the source of the P-channel MOS transistor switch 53, and the drain is connected to the capacitor 33 as described above.

The N-channel MOS transistor switches 41 to 43 are switches for connecting one end of the capacitors to the ground when charging the capacitors 31 to 33.
The drains of the N-channel MOS transistor switches 41 to 43 are connected to the capacitors 31 to 33 as described above, and the sources are grounded. Also, N channel MO
The gates of the S transistor switches 41 to 43 are connected to the second clock signal terminal 64, and the N channel MOS transistor switches 41 to 43 are controlled by the second clock signal.

Although the first clock signal Φ1 input from the first clock signal terminal 63 and the second clock signal Φ2 input from the second clock signal terminal 64 are in-phase clocks, In order to ensure the above, the rising and falling timings are slightly shifted.

A rectifier circuit 61 is connected to the cathode side of the diode 21. The output voltage rectified by the rectifier circuit 61 is output from the output terminal 62. Rectifier circuit 61
Is composed of a diode 24 and a capacitor 36. The anode of the diode 24 is connected to the cathode of the diode 21, which is the input of the rectifier circuit 61, and the cathode side of the diode 24 is connected to one terminal of the capacitor 36 and the output terminal 62. The other terminal of the capacitor 36 is grounded.

In the above circuit, if the internal impedance of the boosting blocks 11 to 13 is sufficiently small, the capacitors 34 and 35 are not necessary and can be omitted.

In the above-described embodiment, an example using three boosting blocks is shown, but the number of boosting blocks is not limited to three, but two or four.
In general, it is possible to use N or more boosting blocks, such as three or more, and to similarly configure them. At this time, as for the P-channel MOS transistor switch corresponding to the N-th boosting block, the power supply voltage may be applied to the source and the first clock signal may be input to the gate, as in the P-channel MOS transistor switch 53. .

An example of the operation of one embodiment of the booster circuit of the present invention will be described below. FIG. 2 is a timing chart at the time of operation in one embodiment of the booster circuit of the present invention.
2A is the voltage of the output terminal 62, FIG. 2B is the voltage of the connection point 72, FIG. 2C is the voltage of the connection point 73, and FIG.
2D shows the voltage at the connection point 76, FIG. 2E shows the clock signal Φ1, and FIG. 2F shows the clock signal Φ2.

In the period t1, the first clock signal terminal 6
The power supply voltage VCC is applied to both the third and second clock signal terminals 64. Therefore, N channel M
The OS transistor switches 41 to 43 are turned on, and the boosting blocks 11 to 13 supply the output voltages V1 to V3 to the connection points 71 to 73 of the capacitors 31 to 33 through the diodes 21 to 23. Capacitors 31-33
The voltage of the connection points 71 to 73 is lowered by the voltage drop Vd of the diodes 21 to 23 by the charging of the voltage V1-Vd, V.
2-Vd, V3-Vd. At this time, P channel M
The power supply voltage V is applied to the gate of the OS transistor switch 53.
Since CC is applied, the P-channel MOS transistor switch 53 is off. On the other hand, to the sources of the P-channel MOS transistor switches 51 and 52, the voltages V2-Vd and V3-Vd lower than the high voltages V2 and V3 output from the boosting blocks 12 and 13 by the voltage drop Vd of the diodes 22 and 23 are applied. Then, high voltages V2 and V3 are applied to the gates. As a result, the P-channel MOS transistor switches 51 and 52 automatically maintain the off state. This off state is maintained while the P-channel MOS transistor switch 53 is off.

Even if V2 and V3 change for some reason, the source voltage Vs and gate voltage Vg of the P-channel MOS transistor switches 51 and 52 are Vg.
Since the relation of> Vs is established, the switch 501,
502 can be turned off.

Next, in the period t2, the second clock signal terminal 64 is set to 0V and the N-channel MOS transistor switches 41 to 43 are turned off, and then the first clock signal terminal 63 is set to 0V. Then, P channel MOS
The transistor switch 53 is turned on, and the connection point 76 changes from 0V to the power supply voltage VCC. This makes the connection point 7
3 is boosted to (V3-Vd + VCC). At this time, P
Since the gate of the channel MOS transistor switch 52 remains V3, (V3-Vd + VCC)> (V
3 + Vthp), the P-channel MOS transistor switch 52 is turned on, and the connection point 75 changes from 0V to (V3-Vd + VCC-Vt).
hp). Here, Vthp is a P channel MOS
It is the threshold voltage of the transistor. Furthermore, connection point 7
2 is also boosted, the P-channel MOS transistor switch 51 is also turned on, the connection point 74 is also boosted, and the connection point 71 is (V1 + V2 + V3 + VCC-3Vd-2).
Vthp). Finally, at the output terminal 62, including the voltage drop of the diode 24, (V1 + V2 +
The voltage V3 + VCC-4Vd-2Vthp) is output.

As described above, the P-channel MOS transistor switches 51 and 52 are also turned on in a chain by turning on only one P-channel MOS transistor switch 53, so that the capacitors 31 to 33 can be connected in series. . As a result, the switching mechanism can be simplified. In addition, it is possible to switch between multiple capacitors charged in parallel with the high voltage output of the booster block in parallel or in series using only the low voltage clock signal, eliminating the need for an additional circuit for boosting the clock signal as in the past. Becomes

FIG. 3 is a circuit diagram showing another embodiment of the booster circuit according to the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. Reference numerals 81 to 83 are P-channel MOS transistor switches, and reference numerals 91 to 93 are N-channel MOS transistor switches. The embodiment shown in FIG. 3 corresponds to the boosting blocks 11 to 1 in the embodiment shown in FIG.
3 shows the case where the output of 3 has a negative polarity. Therefore, the polarities of the diodes 21 to 24 are opposite to each other, and P is used instead of the N-channel MOS transistor switches 41 to 43.
Channel MOS transistor switches 81-83
N-channel MOS transistor switch 91 instead of P-channel MOS transistor switches 51-53
~ 93 are used. Further, -VCC is applied to the source of the N-channel MOS transistor switch 93. Other circuit configurations are similar to those of the circuit shown in FIG.

The operation of this circuit is the same as that of the circuit shown in FIG. 1 except that the polarities thereof are reversed, and the description thereof is omitted here. In the timing chart shown in FIG. 2, the polarities are opposite, and the first clock signal Φ1 and the second clock signal Φ2 have −VC during the period t1.
In the period C and the period t2, the voltage may be 0 V, for example.
Thus, even if the output of the boosting block has a negative polarity, a circuit that achieves a similar function can be obtained.

In each of the above embodiments, the boosting block 1
Although the contents of 1 to 13 are not described, any circuit may be used as long as it can supply a high voltage higher than the power supply voltage. For example, various circuits such as a conventional circuit as shown in FIG. 4 and a circuit in which a capacitor is charged in parallel and a high voltage is obtained by connecting the capacitors in series after charging can be used.

Further, although two clock signals are used in each of the above-mentioned embodiments, one clock signal is used to supply each of the MOS transistors if a little leak current can be tolerated. May be.

Since the MOS transistors are used as the switching elements in the configurations of the above-described embodiments, they are advantageous when integrated into an IC. For example, if integrated into an IC using a CMOS manufacturing technique or the like, the power supply can be downsized and the cost can be reduced. Not limited to the CMOS manufacturing technology, various semiconductor technologies can be used. Of course, the present invention is not limited to the MOS type and can be widely configured by using field effect transistors.

[0036]

According to the present invention, a plurality of capacitors charged with a high voltage can be switched in parallel or in series only with a low voltage clock signal, so that a high voltage can be obtained in a short time. The possible booster circuit can be realized with a simple configuration. Further, according to the switching system of the present invention, a series connection of a plurality of capacitors charged with a high voltage can be performed in a chain by only switching one switching element, so that the switching mechanism is simplified. Furthermore, when the capacitors are connected in parallel, the current path formed between the high output voltage of the boosting block and the ground potential can be reliably turned off by using the output voltage of the boosting block. Loss can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a booster circuit of the present invention.

FIG. 2 is a timing chart at the time of operation in one embodiment of the booster circuit of the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the booster circuit of the present invention.

FIG. 4 is a circuit diagram showing an example of a booster circuit using a conventional charge pump.

FIG. 5 is a circuit diagram showing another example of a conventional booster circuit.

[Explanation of symbols]

11-13 ... Booster block, 21-24 ... Diode,
31-36 ... Capacitors 41-43, 91-93 ... N
Channel MOS transistor switch 51-53,
81 to 83 ... P-channel MOS transistor switch, 61 ... Rectifier circuit, 62 ... Output terminal, 63 ... First clock signal terminal, 64 ... Second clock signal terminal, 71
~ 76 ... connection point.

Claims (1)

[Claims] 1. A booster circuit for generating a higher voltage than a power supply voltage in a booster circuit for switching a plurality of capacitors charged at a voltage higher than the power supply voltage from a parallel connection to a series connection to obtain a higher voltage; A rectifying element connected to the output of the boosting block, the capacitor connected to the rectifying element, and a first field effect transistor connected to the capacitor and turning on / off the connection with the ground according to a second control signal, N circuit blocks having second field effect transistors connected to the capacitors are provided, and the second field effect transistors of the 1st to N-1th circuit blocks are the rectifying elements and the capacitors of the next circuit block. And its gate is connected to the output of the boosting block of the next circuit block, and the second circuit block of the Nth circuit block is connected. The field effect transistor is connected to a power supply and has a gate to which a first control signal is input, and is configured to take out an output from a connection point between the rectifying element and the capacitor in the first circuit block. A booster circuit characterized by the above.