GB2357900A - DRAM capacitor electrode having hemispherical silicon grains - Google Patents

Abstract

The lower capacitor electrode comprises a first lightly doped or non-doped amorphous silicon layer 31 and a highly doped amorphous silicon layer 32. In this structure crystal grain growth from the amorphous silicon layer 31 to the amorphous silicon layer 32 is suppressed and hemispherical silicon grains are formed uniformly on the top and side surfaces of the electrode during annealing. Alternatively, the impurity concentration may be varied continuously in a single amorphous silicon layer from a low impurity concentration adjacent the substrate to a high impurity concentration near the surface of the electrode.

Description

2357900 9EMICONDUCTOR CAPACITOR DEVICE.-: 5 The present invention relates

to a semicoDductor device, and more specifically to a capacitor incorporated in a semiconductor device and a method for forming the. same.

At present, as can be seen in a DRAM (dynamic random access memory), a high integAtion density is demanded in semiconductor devices. In order to fulfil this demand, an area required for each memory cell in the DRAM has been extremely redilced. For example, in a 1MDRAM or 4MDRAM, a 0.8 pim rule has been adopted in the semiconductor device design, and further, in a 161v1DRAM, a 0.6 gm rule has been adopted.

As mentioned above, the integration den sity is increased more and more; that is- the memory capacity - is increased more and more in a semiconductor memory. However,. in order to raise the production efficiency and to lower the production cost,. it is not allowed to increase the size of a semiconductor device chip. Because 6f this an importarit problem to be solved in the semiconductor device is how small the memory cells can be formed.

However, if the area of the memory cell is reduced, the amount of electric charges stored in the memory cell correspondingly become small; Therefore, it has become difficult to realize a Iligh integration densi y oi memory cells and at the same time to ensurre that the necessary i mount of electric charge is stored in each memory cell.

Under the above mentioned circumstance, a memory cell havina, a 0:

trench capacitor and a memory cell having a stacked capacitor have beeri proposed and reduced to practice.

As compared with the memory cell having the trench capacitor the:

memory cell having the stacked capacitor has an excellent soft-error' resistance and the'.:advantage that nc damage is inflicted on the silicon:

substrate. Therefore, the stacked capacitor type memory cell is expec:ted, as the main next generation memory cell structure.

As the stacked capacitor, there is proposed a stacked capacitor:

formed by utilizing a HSG (herni-spherical (silicon crystalline) grain);, technique (See for example Japanese Patew' Application Pre-examinationi Publication No. JIP-A-5-110023, incorporated here by reference). Ihe stacked capacitor consists of d"capacitor -'-.o,.er plate, a capacitor.

insulator film and a capacitor upper plate, the capacitor lower plate being electrically connected through a contact hole formed in an interlayer insulator film, to a MOSFET (metal-oxide-semiconductor fi effect transistor) formed in the-semiconductor substrate.

Here, the HSG technique is to form a number of hemi-spherical grains on a surface of a storage electrode -(dapacitor lower plate), so that the 2 surface area of the storage electrode is substantially increased, with the result that an increased capacitance is achieved.

in order to form the storage electrode having the surface covered with the hemi-spherical grains mentioned above, various processes were proposed. For example, JP-A-5-110023 proposes to deposit a voidless polysilicon film or an amorphous silicon film by a UCVD (low pressure chemical vapor deposition) process as an underlying film of a capacitor lower plate, then to form a natural oxide film on the underlying film,'- and to deposit another amorphous silicon film on the natural oxide film by a LPCV13 process, as an overlying film of the capacitor lower plate, and further to conduct a heat treatmeat to the overlying amorphous silicon film, so that a surface-roughed polysilicon film having a concavo-convex upper surface is formed.

In this process, when the overlying amorphous silicon film is heat treated, migration occurs in the amorphous silicon film, so that crystalline grairs arc. formed, with the result that the surface-roug",.'ied polysilicon film having the concavo-convex upper surface is formed. In addition, in this Process, since crystallinity of the underlying silicon EIni is prevented from giving any influence to the overlying roughed polysilicon film by the natural oxide film, it is possible to sufficiently roughen the overlying silicon film surface.

Furthermore, Japanese Patent Application Pre-examination Publication No. JP-A-7-014797 (which was a publication of Japanese Patent Application No. 140710/1994 filed claiming Convention Priority based on U.S. Patent Application Serial No. 081071904 filed on June 3, 1993, incorporated here by reference), proposes another method for forming a polysilicon layer having, a concavo-convex surface. A silicon dioxide layer is formed on a polysilicon layer, and a silicon layer is formed on the silicon dioxide layer while being exposed to a dopant gas. This prevents generation of a dopant defective iegio occurdna when there is used a hl-h temperature dopant migration methed for causing, by means of heat treatment, the dopant to move upward from a layet underlying under a surface-roughened polysilicon layer. The result is t at a polysilicon layer having a concavo-convex surface is formed.

Both of JP-A-5-110023 and JP-A-7-014797 as.mentionea at)ov(,, ar characterized by enlarging the concavities and convexities formed on the top surface of a capacitor lower plate, but pay no attentio to formation of concavities aind convexities on the side surface of tha. capacitor lower plate. In order to increase the capacitance of the me ory i cell capacitor, it is necessary to form the concavities and convexities not only on the top surface of the capacitor lower plate but also on the side - suiface, of the capacitor lower plate which is exposed when the capacitor lower plate is formed and which is therefore covered with a capacitor upper plate. Therefora, when the methods of JP-A-5-110023 and JP-j-7-, 014797 are applied for forming a capacitor on an actual MOSM, a sufficient capacitance cannot be obtained.

Furthermore, neither JP-A-5-110023 nor JP-A-7-014797 discusses, a phenomenon occurring at a boundary between an interlayer insulator! film and a capacitor lower plate when the capacitor is connected to a;' MOSFET formed in the semiconductor device.

Japanese Patent Application Pre-examination Publication No. R-A-5-304273 (which corresponds to U.S. Patent 5,385,863, incorporated here by reference) suggests forming concavities and'convexities on a side surface of a capacitor lower plate by utilizing the HSG technique called "crystal nucleation". In this crystal nucleation, silicon atoms in the top surface and the side surface of an amorphous silicon film are caused to migrate, with the result that the concavities and convexities are formed on both the top surface and the side surface.

However, when the capacitor lower plate is formed in accordance with this crystal nucleation, crystallization of the film starts from a boundary between the capacitor lower plate film and the interlayer insulator film, and this crystallization reaches to the top and side surfaces before the silicon atoms in the top and side surfaces have sufficiently migrated. If crystallization reaches the top and side surfaces, m]-ration of silicon atoms can no Ion-er occur, and therefore, the concavities and convexities can no longer be formed on the top and side surfaces. As a result, it is not possible to form the concavities and convexities over the whole surface of the cppacitor lower plate. It is also not possible to avoid gerteration of defective regions of about 10% to 20%.

Accordingly, it is an object of at least the preferred embodiments of the present invention to provide a capacitor which is incorporated in a semiconductor device and which has overcome the above mentioned defects of the conventional ones.

Another object of at least the preferred embodiments of the present invention is to provide a capacitor which i.- incoiporated in a semiconductor device and which has uniform- concavities and convexities on both a top surface and a side surface of a capacitor lower plate, thereby to have an increased large capacitance.

In bne form, the invention provides a capacitor which is incorporated in a semiconductor device and which is formed in contact with an interlayer insulator film, but is not subjected to influence of crystallization from the interlayer insulator film.

A further object of at least the preferred embodiments of the present invention is to provide a method for forming a capacitor incorporated in a semiconductor device, capable of uniformly forming, concavities and convexities on both a top surface and a side surface of a capacitor lower plate, thereby to manufacture the capacitor having an increased large capacitance.

A still further object of at least the preferred embodiments of the present invention is to provide a method for forming a capacitor having a capacitor lower 5 - plate in contact with an interlayer insulator film in a semiconductor device, wh' le preventing crystallization aeneratina from a boundary between the interlayer ir sulat 1 or film and the capacitor lower plate.

According to the present invention there is provided a capacitor incorporated in a semiconductor device comprising a substrate covered by an insulating la) er, the capacitor having:

a lower plate in the form of a semiconductor layer deposited on the insulati pg layer, the semiconductor layer being treated to form concavities and convexities over its exposed surface; an insulating film formed over the exposed top and side surfaces thereof; add a top plate of semiconductor material formed over the insulating filrr.:

wherein the semiconductor layer is formed with a laminate structure giving good conductivity to its top surface and promoting the formation of concavities add convexities over the side of its exposed surface.

The invention also provides methods of making such capacitors.

The present invention may further be achieved in accordance with the presett invention by a capacitor incorporated in a semiconductor device and hxiing ia capacitor lower plate having a top surface and a side surface continuous to the top surface, the capacitor lower plate being composed of a first silicon film, a crystallization preventing layer formed on the flist silicon film, and a second fflicoIn film formed-on the crystallization preventing layer, the capacitor lower plate having concavities and convexities in the form of herni-spherical grains formed on the tO surface and the side surface, the capacitor lower plae being, covered with a capacitor insulating film, which is covered with a capacitor upper plate.

Accordin- to a second aspect of the present invention, there is prov ded a capacitor incorporated in a semiconductor device and having a capacitor lower plate having a top surface region and connected to another circuit element formed in the senficonductor device, the capacitor lower plate having an impurity concentration grade which is low at a lower portion adjacent to the circuit element and which is high at the top surface region, the capacitor lower plate having concav'ities and convexities in the form of hemi-spherical grains formed on at least the top surface, the capacitor lower plate being covered with a capacitor insulating film, which is covered with a capacitor upper plate.

According to a third aspect of the present invention, there is provided a method for forming a capacitor incorporated in a semiconductor device, the capacitor lower plate being in contact with an interlayer insulator film, the method including the steps of:

forming a first amorphous silicon layer on the interlayer insulator film; is forming on the first amorphous silicon layer a crystallization prevI-nting film having a thickness smaller than thL,,,L of the first amorphous silicon layer; forming a second, impurity-containing, amorphous -,,.3,;-con layer on the crystallization preventing film; patterning a stacked structure composed of the first and second amorphous silicon layers and the crystallization preventing film, into a capacitor lower plate having a predetermined shape; heat-treating the capacitor lower plate so as to form concavities and convexities in the form of hemi-spherical grains on a surface of the capacitor lower plate, the crystallization preventing film preventing advancement of crystallization starting at a boundary between the interlayer insulator and the first amorphous silicon layer of the capacitor lower plate; forming a capacitor insulator film to cover the capacitor lower plate; and forming a capacitor upper plate to cover the capacitor insu'atot,, film.

According to a fourth aspect of the present invention, there is, provided a method for forming a capacitor incorporated in. a, semiconductor device, the capacitor lower plate being in contact witi an, interlayer insulator film, the method including the steps of formiag a first amorphous silicon layer on the interlayer insulat& film; forming on the first amorphous silicon layer a secc nd,, impurity-containing, amorphous silicon layer having an impu ity concentration higher than that of the first amorphous silicon layer; patterning a stacked structure composed of the first and secDLd amorphous flicon layers, into a capacitor lower plate having a predetermined shap%-, heat-treating the capacitor lower plate so as to form concaves and convexes in the form of hemi-spherical gtains on a surface of the;i capacitor lower plate, the first amorphous silicon layer having suci a impurity concentration as to prevent advancement of crystallization starting at a boundary between the interlayer insulator and the f ixst amorphous silicon layer of the capacitor lower plate; forming a capacitor insulator film to cover the capacitor lo er plate; and 8_ forming a capacitor upper plate to cover the capacitor insulator film.

Two capacitors and methods of making them will now be described, by way of example, with reference to the drawings, in which:

Figs. 1 to 7 are diagrammatic sectional views of a part of semiconductor devices, showing a method of forming a capacitor in a semiconductor device; Fig. 8 and 9 are views similar to those of Figs. 4 and 5 showing a variation of the method; and Fig. 10 is a graph illustrating the fraction of defective capacitors manufactured in accordance with the prior art method and the present embodiments.

Fig. 1 shows an N-type silicon substrate 10.

various impurity diffused regions and various circuit elements, including, , MO5FETs (not shown), other than a capacitor element, are formed in and, on the silicon substrate 10, and electrically connected to realize vailouS functions. However, for representing those impurity diffused regions and various circuit elements, only an impurity diffused region 30 is shown for simplicity.

On the silicon substrate 10, a silicon oxide fil---11; having a thickness of 300 wn is selectively formed by a LOCUS. (loc&Li oxidation of silicon) process, as a field oxide, namely, as a device isolation', rexyion. The silicon substrate is partially exposed in a device formation region including the diffused region 30.

Then, as shown in Fig. 2, an interlayer insulator film 12 having al 15 thickness of 600 nm formed of a silicon oxide or a. BIW! 0 (borophosphosilicate glass), is deposited to cover le silicon substrate 1 and the silicon oxide film 11, by an atmospheric pressure CVD processAfter the interlayer insulator film 12 is,'CDosited, a contact hole, 11 is formed to penetrate through the interlayer insulator film 12 at a:w ? 0 predetermined position as shown in-Fig. 3 by use of dry or wet etching. In the example shown, Ahe contact hole 13 is formei t expose a surface of the diffused region 30 of the silicon substrate 10.

The contact hole 13 has an opening diameter of 400 nm an bottom diameter of 200 nm.

2 5 After formation of the contact hole 13, the silicon substrate M, (with the silicon oxide film 11 and the interlayer insulator film 12:

having the contact hole 13), is introduced into a reaction chamber 4ck f 10- CVD- process, for the purpose of forming a capacitor lower plate in the reaction chamber- In the example shown in Fig. 4, three amorphous silicon films 141, 142, and 143 are deposited:in sequence, and two silicon oxide films 151 and 152 are formed between the amorphous silicon films as shown.

Each of the amorphous silicon films is formed of a phosphorus doped amorphous silicon.

First, the first amorphous silicon film 141 was formed by conducting a film deposition for about one hour under film deposition conditions of silicon substrate temperature of 530T, reaction chamber pressure of LY X102Pa (1.0Torr), SiH4 flow rate of 1000 cc/min, and PH3 flow rate of 0.5 cc/min. Thus the obtained - " first amorphous silicon film 141 is a phosphorus doped amc-úPhous silicon film containing a phosphorus concentration of about 2X 1020 atom/cm3 and hw.; ing a thickness of 150 nm.

After formation of the first amorphoussiLi= film 141, the supply of the SW4gas and the PH3 gas were stopped, and the reaction chamber was evacuated. Thereafter, a nitroa-en gas containing 1% of oxygen was introduced into the reaction chamber at a flow rate of 1000 cc/min, for five minutes. As a result, a first silicon oxide film 151 having a thickness of 1 nm to 2 mn was formed on a surface of the first amorphous silicon 2 5film 14 1.

Succeedingly, underthe same film deposition condition as that for forming the first amorphous silicon film 141:,.-the second amorphous7 silicon film 142 was deposited. The deposited second:

amorphous silicon film 142 is thus a phosphorzs doped amorphous silicon film, similar to the first amorphous silicon film 141.

Thereafter, the reaction chamber was evacuated, aeain. Therea.er, 5 a nitrogen gas containing 1% of ox gen was introduced into the reactiow It> y chamber at a flow rate of 1000 cc/min, for five minutes, similarly to. formation of the first silicon oxide filin 151. Thus, a second silicon o:cide:; film 152 having a thickness of 1 nm to 2 nm was formedon the surfce of the second amorphous silicon film 142.

Then, the third amorphous silicon film 143 was formed by:

cond.unting the film deposition for about two hours under the same illm:, deposition condition as those for forming the first and second amorpt OUS i silicon films 141 and 142. Thus, the third amorphous silicon film 143: having a thickness of about 300 nm was formed., as a phosphorus doped amorphous silicon film, similar to the first and second amorphous silico n films.141 and 142. Thus the multilayer structure as shown in Fig. Z ir obtained.

In the above dF.scribed process, the silicon oxide films 15 1 ane.

152 were formed in the same reaction chamber as that in which the 2 0 silicon films were derosited.

However, the silicon oxide films 151 and 152 can be formed by taking out the silicon substrate from the chamber after each of the first and second amorphous silicon films 141 and 142 is deposited, so that the deposited amorphous silicon film is exposed to atmosphere, with the result that a natural oxide film is formed on a surface of the amorphous silicon film.

Here, the first amorphous silicon film 141 is in contact with the interlayer insulator film 12, and it has been found that when a heai treatment is conducted, a crystal grows from crystal nuclei on the interlayer insulator film 12. However, it has been found that, when the crystal grown from the crystal nuclei on the interlayer insulator film 12 reaches the first silicon oxide film 151, the crystal does not grow 5. further.. Accordingly, in the multilayer structure shown in Fig. 4, the first and second silicon oxide films 151 and 152 function as a crystaLlization preventing film. Incidentally, in the embodiment shown, two layers of crystallization preventing film composed of the first and second silicon oxide films 151 and 152 are provided, but a single layer of crystallization preventing film can be used. In this case, there will be only two layers oi amorphous silicon film After the third amorphous silicon film 143 is formed as shown in Fig. 4, the multilayer structure composed of the amorphous silicon films 141, 142 and 143 and the silicon oxide films 151 and 152, is etched to form a patterned multilayer structure (used as a capacitor lower plate) composed of the am-)rphous silicon films 141, 142 and 143 and the silic7bn oxide films 1.51 and 152, as. shown in Fig; 5. This patterned stacked structure is expolsed not only on its top surface but also on its side surface. In the as-patterned condition, the top surface and the side surface of the patterned multilayer structure are covered with a thin natural oxide film. This natuiul- oxide film will become a hindranc'e to silicon atom migration required to form hemi-spherical grains in a succeeding process, which will be conducted for forming hemi- spherical grains on a surface of the patterned multilayer structure. This process 2 5 will be called a MSG process" hereinafter.

Accordingly, the natural oxide film on the top surface and the side surface of the patterned multilayer structure is-removed by use of a dilute hydrofluoric acid or any other means. After the natural oxide film is removed, the HSG process is conducted in the reaction chamber.

In the MG process, first, to form nuclei on the patterned multi..aye structure, SM4 was irradiated onto the patterned multilayer structure at the flow rate of about 20 cc/min within the reaction chamber maintained at a temperature of 560'C under the pressure of 0.08 Pa (0.6 mTorr).

After the nuclei were formed on the top surface and the side suiacei of the patterned multilayer structure, the reaction chamber was evacuated to 1.3 X10-4 Pa (1.0x10-6 Torr), and then, a heat treatment was', conducted at the same temperature of 5.'PO for 40 minutes. As a result, as;, shown in Fig. 6, hemi-spherical grains MG were formed not only oin the:, top. surface of the patterned multilayer structure but also on the ide:.

surface of the patterned multilayer structure.

Here, the distribution of the hemispherical grains is extremely uniform on. the top surface and the side..ljurf,-,%-.e of the patterned'! multilayer structure, because.the crystalline growth from the cry tal nuclei at the boundary betweeti the interlayer insulator film 12 and the amorphous silicon layer is prevented by the first and second silicon o)de' 2 0 films 151 and 152. Thus, the patterned multilayer structure having thel hemi-spherical grains formed on its whole surface, can be used as a 1:

capacitor lower plate. This capacitor lower plate has a surface area which is not less than 1.8 times, and,Preferably, not less than 2 times, that of a plate which has no concave-convex surface given by the hemi-spherical grains HSG.

Thereafter,.as shown in Fig. 7, in accordance with the LKYD process under the condition of 650T and 0-93. X 102. Pa (0.7 Torr), SiH2.C12 was introduced at the flow rate of 40 cclinin and NH3 was introduced at the flow rate of 120 cc/min, for 20 minutes. Thus, a silicon nitride film 24 havina a thickness ot 7 nm was formed to cover the surface of the hemi-spherical grains HSG, as a capacitor insulator film, ie a capacitor dielectric filn After that, a phosphorus doped silicon film 25 having a thickness of 200 nm is formed to cover the capacitor insulator film 24, as a capacitor upper plate. Thus, a capacitor element is completed. Here, the silicon film 25 constituting the capa-citor upper plate can be formed of amorphous silicon film or a polysilicon film.

In tilis embodiment, each of the silicon oxide films 151 and 152 has a thickness of 1 nm to 2 nm, as mentioned above. Preferably, each of the silicon oxide films 151 and 152 has a thickness of not greater than 5 nm, in order that the amorphous silicon films 141, 142 and 143 are mutualy electrically connected through the silicon oxide films 151 and 152 but a sufficient crystaWzation preventing function can be ensured.

Now, referring to Figs. 8 and 9, a modified method will be described. This process is the same as the first for the steps shown in Fig. 1 for forming the silicon oxide film 11 on the silicon substrate 10, Fig. 2 for forming the interlayer insulator film 12 on the silicon substrate 10 and the silicon oxide film 11, Fig. 3 for forming the contact hole in the interlayer insulator film 12, and also in the MG forming step as shown in Fig.6 and in Fig. 7 for forming the -is- capacitor insulator film and the capacitor upper plate. In other words the..

second process is different from the first process only in thel steps as shown in Figs. 4 and 5 for forn-Ling the capacitor lower p.,ate.; :

Therefore, Figs. 8 and 9 illustrate only the steps for forming the.

capacitor lower plate Corresnonding reference numerals are used herd appropriate.

As shown in Fig. 8, a first.amorphous silicon film 31 having no; doped impurity or a low concentration of impurity is formed on the:

interlayer insulator film 12 and the diffused region -30-e-xposed in tile contact hole, and a second amorphous silicon film 32 having a high:, concentration of impurity is fonned on the amorphous silicon film 3 1, is In theexample shown, the first amorphous silicon film 31 was formed by conducting a film deposition for about 20 minutes under a Ailm deposition c6ndition of the silicon substrate temperature of 530T, the reaction chamber pressure of---1. 3 X 102 Pa (1. 0 Torr), and the S1 4 flow rate of 1000 cc/min. Thus, the non-doped first amorphous silicon film 31 having a thickness of about 30 nm to 50 nin was forTned.

When -PH3 was introduced at the flow rate of 0.2 cc/min together with introduction of SiH4, an amorphous silicon film containing a low phosphorus concentration of not greater than 7x1019 atomIcm3 could be obtained. This means that the flow rate of PH3 introduced as impurity at the time of forming the first amorph)us silicon film 31 is.preferably adjusted in the range of 0 cc/min to 0.2 cc/min.

Following the formation of the first amorphous silicon film 3 1, the second amorphous silicon fflim 32 having the impurity concentration higher than that of the first amorphous silicon film 31 is formed. As the second amorphous silicon ffim.32, an amorphous silicon film containing a phosphorus concentration of 2x1020 atona/cm3 was deposited to have a thickness of 550nin by introducing PH3 at the flow rate of 0.5 cc/min together with introduction of SM4,

The first and second deposited second amorphous silicon films 31 and 32 can be formed in the same reaction chamber b chanaina the flow y 1 o rate of PH3 for the purpose of changing the impurity concentration of the deposited film. However, the first and second deposited second amorphous silicon films 31 and 32 can also be formed in different reaction chambers which are set to different flow rates of PH3, respectively.

Furthermore, the first and second deposited second amorphous silicon films 31 and 32 can be formed in the same reaction chamber 15y continuously changing the flow rate of PH3 ft-.c)m 0 cc/min to 0.5 cc/min for the purp6se of continuously changing the impurity concentration of the deposited film. Furthermore, a crystallization preventing layer like layers 151 and 152 can be formed between the first and second deposited second amorphous silicon films 31 and 32 by utilizing the first process in combination with the second proces s.

Thereafter, the multilayer structure composed of the amorphous silicon films 31 and 32 is etched to form a patterned multilayer structure (usea as a capacitor lower plate), as shown in Fig. 9, which is electrically connected to the silicon' substrate 10 (and more specifically to the diffused region 30 formed.:in.the silicon substrate 10) and which is also in contact with the interlayer insulator film 12. Th 1; S pattern stacked structure is exposed not Only on its top surface but Iso: on its side surface.

In this as-patterned condition, simnarly to the step shown in Fig.

the HSG process was conductedon the top:surface and the side surface, of the patterned -multilayer structure, so that a capacitor lower plate is formed.

Following this., similarly to the step shown in Fig. 7, a capacitot dielectric film 24 and a capacitor upper plate 25 are formed. Thus, capacitor element is completed.

It has been found that the capacitor element thus formed has concavitiesand convexities in the form of hemi-spherical grains HSG on the top surface and the side surface of the capacitor lower plate, and the cmcavities and cmvexities are extremely uniformly distributed, because the"' 15 crystalline growth does not occur from the crystal nuclei at the bounlary, between the interlayer insulator film 12 and the amorphous silicon layer.

In this it was confirmed from experiments that, ifthel phospliorous concentration of---the first amorphous silicon film 3.1 in! contact with the interlayer insulator 12 is not greater thartl 7X1019 atom1CM3 crystal does not-grow from the crystal nuclei at thel interlayer insulator film 12. It was also found that, if the sec()nd amorphous silicon film 32 was formed of an amorphous silicon having a low concentration of impurity, a depletion layer extends from the capacitor lower plate surface, and when a positive bias is applied to the::

2 5 capacitor upper plate, the capacitance value drops 40% or more.

Iberefore, when the capacitor lower plate surface is formed of only an amorphous silicon having a low concentration. of impurity, the increas of 18- the capacitance obtained by the MG processing of the capacitor lower plate will be substantially cancelled.

On the other hand, if the capacitor lower plate surface is formed of only an amorphous silicon having a high concentration of impurity of greater than 7x 10 19 atomlcm3 (for example, 2x 1020 atom/cm3), the crystalline growth from the crystal nuclei at the interlayer insulator film 12 in the MG process reaches the surface to be formed with the hemi-spherical grains HSG, with the result that distribution of hemi-spherical grains MG becomes uneven.

The second Process shown in Figs. 8 and 9 has the features that the impurity concentration of the first amorplious sAlcon fihn 31 in contact with the interlayer insulator film 12 is low enough to prevent the crystalline growth from the interlayer insulator film, and on the other hand, the second amorphous silicon film 32 to be formed with the hemi-spherical grains HSG has a high impurity concentration sufficient to realize an increase of capacitance by the formation of hemi-spherical grains HSG ahd simultaneously. to prevent generation of a depletion layer.

0 The second prncess Prodibes the stacked structure of the first amorphous silicon layer having the low concentration of impurity and the second amorphous silicon layer having the high concentration of impurity. However, three or more amorphous silicon layers having different concentrations of impurity can be stacked, or alternatively, the stacked structure can be replaced by a single amorphous silicon layer having an impurit concentration gradient which continuously b=eases fmn th-region near to the interlayer insulator film. In either of these cases, a plurality of stacked amorphous silicon layers having having different concentrations of impurity are formed o equivalently formed.

Considering various impurities, in order to prevent crystallind, growth from the crystal nuclei at the interlayer insulator film 12, thdi impurity concentration of the first amorphous silicon film 31 'm contact' with the interlayer insulator 12 is preferred to be less -.han: 1 X 1020 atomICM3, and in order to prevent the depletion layer, the: impurity concentration of the second amorphous silicon film 3 is: preferred to be greater than 1 x 1020 atonVcn13.

Fig. 10 is a graph illustrating the fraction of defective of capacitors manufactured in accordance with the prioi art: method and the two present processes.

The prior art example was a capacitor having al, capacitor lower plate which is formed of a single layer of amorphous i silicon film and which has a top surface and a side surface both proce., sed by the HSG process to have ccncavi..t:ies and convexities in the fcrm f hen-d-sphericdl-gra.ins HSG. In addition, the capacitance of the capacitor' which is not subjected to the MG process is standardized to "1", and HSG-processed capacitors having capacitance magnification of less than 1.2 are classified to "case and HSG-processed capacitors hav ing capacitance magnification of not lesg than 1.2 but less than 1.8 are classified to "case As seen from the graph of Fig. 10, 500 capacitors manufactured in accordance with the prior art include 80 capacitors including a port on which has no concavelconvexities in the form of hemi-spherical graLns HSG, and 30 capacitors including no concavelconvexities in the fol m of,' hemi-spherical grains HSG.

On the other hand, the first embodiment shown in Figs. 1-7 having the crystallization preventing layer between the amorphous silicon films includes a few capacitors including a portion which has no concavelconvexities in the form of hemi-spherical grains HSG, per 500.

capacitors, but includes no capacitors including no concavelconvexi ties in the form of herni-spherical grains HSG. The second embodiment shown in Figs. 8-9 includes neither a capacitor including a portion which has no concavelconvexities in the form of hemi-spherical grains HSG, nor a capacitor including no concavelconveXities in the form of hemispherical grains HSG.

As seen from the above, the present capacitor lower plate has a surface area which is at least 1.8 times that of a capacitor lower plate which is not processed to have hemispherical grains HSG, and has a very low: fraction defective.

In the above mentioned embodiments, the amorphous silicon films were formed by using silane (SiH4), but disilane (Si2H6), trisilane (Si3H8), or dichlorosilane (SiH2C12) can be used to form the amorphous.silicon films. In addition, in place of phosphorus, As (arsenic) or B (boron) can be introduced by using arsine (AsH3), borane (BH4), diborane (B2H6), or triborane (B3H8).

As mentioned above, the present capacitor lower plate has concavities and convexities-in the form of hemi-spherical grains HSG, uniformly formed on not only the top surface- but alto:the tide surface of the capacitor lower plate, with the result that a remarkably increased capacitance can be obtained. In addition, the present 2 5 method " for manufacturing the capacitor lower plate can prevent the crystalline growth from the interlayer insulator hIm. - It, is therefore. pgssible to significantly increase the capacitance in comparison with a capacitor having a capacitor lower plate manufactured in accordance with the prior art process for the purpose of forming concay ities and convexities in the form of hemi-spherica'. ara'ins HSG, on not only the top surface but also the side surface of the capacitor lower plate, and in addition, the fraction defective can be areatl improved.

It will be understood that the present invention has been described above purely by way of example, and modifications of detail can be rr'ade:

within the scope of the invention.

Each feature disclosed in the description, and (where appropriate)' the claims and drawings may be provided independently or in any: appropriate combination.

The invention may also be described by the following numbered clauses:

1. A capacitor incorporated in a semiconductor device comprising a substrate covered by an insulating layer, the capacitor having: a lower plate in the form of a semiconductor layer deposited on the insulating layer, the semiconductor layer being treated to form concavities and convexities over its exposed surface; an insulating film formed over the exposed top and side surfaces thereof, and a top plate of semiconductor material formed over the insulatind film: wherein the semiconductor layer is formed with a laminate structure giving good -Conductivity to its top surface and promoting the formation of concavities and convexities over the side of its exposed surface.

2. A 'capacitor according to Clause 1 wherein the semiconductor layer extends through a hole in the insulating layer to the substrate.

3. A capacitor according to either previous clause wherein the semiconductor layer comprises a plurality of semiconductor films separated by crystallization- preventing films.

4. A capacitor according toClause3,whercin the semiconductor films are polysilicon or amorphous silicon.

5. A capacitor according to either of Clauses2 and 3 wherein the 0 semiconductor films contain impurity.

6. A capacitor according toclauseS wherein the impurity concentration of 0 the semiconductor films is hiaher for films closer to the top surface.

7. A capacitor according to either OfClauses 1 and 2 wherein te semiconductor layer has an impurity concentration gradient which increasps towards the top surface.

8. A capacitor according toClaus67 wherein the impurity gradient inc eases in steps.

9. A ca acitor according toclause8 wherein the semiconductor layer p consists of a plurality of films of polysilicon or amorphous silicon.

10. A capacitor according toclause 9 wherein the semiconductor layr consists of two films with the lower film having an impurity concentrat on Qt less than!W' ?tom/em'.

11. A 'ca acitor according to either ofclauses9 and 10 whereiri the; p C semiconductor layer consists of two films with the lower film having all impurity concentration of more than 10' atom/cm'.

12. A capacitor substantially as herein described with reference t, tho' drawings.

C 1.. A method for forming a capacitor incorporated in a semiconductor device, said capacitor lower plate being in contact with an interlayer insulator film, the method including the steps of:

forming a first amorphous silicon layer on said interlayer insulator film; formin 4 a on said first amorphous silicon layer a crystallization preventing film having a thickness smaller than that of said first amorphous silicon layer; forming a second, impurity-containing, amorphous silicon layer on said crystallization preventing film; patterning a stack,-.d slructure composed of said first and second amorphous silicon layers and said crystallization preventing film, into a capacitor lower plate having a predetermined shape; heat-treating said capacitor lower plate so as to form concaves and convexes in the form of hemi-spherical grains on a surface of said capacitor lower plate, said crystallization preventing film preventing advancemenf of crystallization starting at a boundary between said interlayer insulator and said-first amorphou.; silicon layer of said capacitor lower plate; forming a capacitor insulator- film to cover said capacitor lower plate; and forming a capacitor upper plate to cover said capacitor insulator film.

Claims (1)

1. 2. A method claimed in Claim 1 wherein said crystallization preventing

   fihn is formed of at least one layer of silicon oxide.

   3. A method claimed in Claim 2 wherein said crystalliz tion preventing film has a thickness of not greater than 5 nm.

   4. A method claimed in Claim 1 wherein said crystallization 5 preventing film has a thickness of not greater than 5 nm.

   5. A method for forming a capacitor incorporated in a semiconductor' device, said capacitor lower plate beina in contact with an inter] yer; insulator flIn-4 the method including the steps of forming a first amorphous silicon layer on said interlayer insulator film; forming on said first amorphous silicon layer a second,! impurity- containing, amorphous silicon layer having an impurity, concentration higher than that of the first amorphous silicon layer; patterffing a stacked structure composed of said first and. sec nd amorphous silicon layers,. into a capacitor lower plac havin a predetermined shape; heE,t,-txeating said capacitor lower plate so as to form cor-caves and convexes in the form of hemi-spherical grains on a surface of said:

   capacitor lower plate, said first amorphous silicon layer haviag such a', impurity concentration as to prevent advancement of crystallization starting at a boundary between said interlayer insulator and said f st amorphous silicon layer of the capacitor lower plate; forming a capacitor insulator film to cover said capacitor loi ver plate; and forming a capacitor upper plate to cov er said capacitor insul tor film.

   -26 6. A method claimed in Claim 5 wherein said patterning of said stacked structure is conducted to form a capacitor lower plate having an top surface and a side surface both exposed, and said heat-treating of said capacitor lower plate is conducted to form concaves and convexes in the form of hemi-spherical grains on not only said top surface and said side surface of said capacitor lower plate.

   7._ A method claimed in Claim 5 wherein said first amorphous silicon layer is formed to have a thickness of 20 nin.

   8. A method claimed in Claim 5 wherein said first amorphous silicon. layer has an impurity concentration of less than X 1020 atomlcm3.

   9. A method claimed in Claim 8 wherein said second amorphous silicon layer has an impurity concentration of greater than IX1020atoMICM3.

   10. A method claimed in Claim 5 wherein said first amorphous silicon layer contains no impurity, and said second amorphous silicon layer has an impurity concentration of greater than 1 x 1020 atom/cm3.

   11. A method for forming a capacitor incorporated in. a semiconductor device substantially as herein described with reference to the drawings.

   27 12- A capacitor incorporated in a semiconductor device and having a capacitor lower plate having a top surface region and connected to another circuit element formed in the semiconductor device, said capacitor lower plate having an imf urio concentration which is lower at a lower portion adjacent to the circuit elemen, thari at said top surface region, said capacitor lower plate including a first silicor film, having said lower impurity concentration and constituting said lower portioi 1 and a second film formed on said first silicon film having an impurity concentration higher than that of said first silicon film, said capacitor lower plate havingi, concavities, and convexities in the form of hemi- spherical grains formed on at, least said top surface, said capacitor lower plate being covered with an insulating: film which is covered with a capacitor upper plate.

   13. A capacitor according to Claiml 2 wherein said capacitor lower plate has a side surface continuous to said top service, and said concavities, and convey ities! in the form of herni-spherical grains are formed not only on said top surfac( but: also on said side surface.

   14. A capacitor according to Clairnl 2 - orClaiml.3 wherein the first silicon film. is formed of polysilicon.

   15. A capacitor according to Claim 12:oC.laim 13 wherein the first silicon film is formed of amorphous silicon.

   16, A capacitor according to any of Claims, 12t o 15 wherein the second silicon film is formed of polysilicon.

   17. A capacitor according to any of Claims 12 to 1 5Wherein the second silicon film is formed of amorphous silicon.

   -18. A capacitor according to any of Claim,51 2to.17 wherein each of the f st and second silicon films contains impurity.

   AM 19. A capacitor according to Clairnl 2 wherein the first silicon film has an impurity concentration of less than 10 atom/cm'.

   2Q. A capacitor according to Claim 1 2P r 19 wherein the second silicon film has an impurity concentration of more than 102' atom/em'.

   21. A capacitor substantially as either one herein described with reference to Figures 1 to 7 or Figures 1 to 3 and Figures 8 and 9 of the accompanying drawings.