GB2355110A - High voltage semiconductor device termination structure - Google Patents

High voltage semiconductor device termination structure Download PDF

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Publication number
GB2355110A
GB2355110A GB9918981A GB9918981A GB2355110A GB 2355110 A GB2355110 A GB 2355110A GB 9918981 A GB9918981 A GB 9918981A GB 9918981 A GB9918981 A GB 9918981A GB 2355110 A GB2355110 A GB 2355110A
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United Kingdom
Prior art keywords
termination
semiconductor device
semiconductor
edge portion
region
Prior art date
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Withdrawn
Application number
GB9918981A
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GB9918981D0 (en
Inventor
Tatjana Traijkovic
Florin Udrea
Gehan Anil Joseph Amaratunga
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Microsemi Semiconductor Ltd
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Mitel Semiconductor Ltd
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Publication date
Application filed by Mitel Semiconductor Ltd filed Critical Mitel Semiconductor Ltd
Priority to GB9918981A priority Critical patent/GB2355110A/en
Publication of GB9918981D0 publication Critical patent/GB9918981D0/en
Priority to EP00306255A priority patent/EP1076363A3/en
Priority to US09/636,353 priority patent/US6445054B1/en
Publication of GB2355110A publication Critical patent/GB2355110A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit comprises an active area containing a high voltage semiconductor device and a voltage termination structure located adjacent the active area. The edge portion comprises a substrate region of a first conductivity type; first termination regions of a second semiconductor type opposite to the first; each first termination region being provided with at least one of second and third termination regions 11a and 11b. The second and third termination regions may be of opposed conductivity type to the substrate, the first termination regions or each other. The second and third termination regions 11a and 11b have a higher semiconductor doping concentration that the substrate 12 but lower than the first termination regions 11.

Description

2355110 A SEMICONDUCTOR DEVICE This invention relates to a semiconductor
device, and in particular to a high to ultra-high voltage device such as a diode, a DMOSFET, a DMOS IGBT, a MOSFET 5 or a trench IGBT.
In order to prevent voltage breakdown at the edges of a high voltage semiconductor device, the device (which is typically built in a relatively large silicon wafer) is provided with a termination structure. A standard termination structure utilises a floating ring termination technique having, say, p-type regions (rings) in a surface layer surrounding the active region (of n-type material) of the device.
A typical prior art floating ring termination structure is shown in Figure 1. The termination structure includes a plurality of p+ floating rings I formed in a n- base layer
2. The rings I are formed just below a passivation layer 3 in the form of a surface field oxide layer, and in general alignment with a p- base 4 and a cathode 5 of the active area (not shown) of the semiconductor device associated with the termination structure. At the extreme edge, the termination structure has a field plate 6 and a channel stopper 7.
The purpose of the p+ floating rings 1 is gradually to release the depletion regioa, and thus the potential lines from the active area towards the edge of the device. If the separation and the depth of the p+ rings I are carefully controlled, the potential lines drop relatively uniformly at the surface between the p+ rings, or between the last p+ ring and the field plate 6, and the breakdown voltage can be close to its ideal value.
The termination is said to be successful if it can achieve a breakdown voltage of more than 90% of the bulk value.
The presence of parasitic charge in the passivation layer 3 in the termination area has a strong influence on the depletion layer at the surface, since this charge influences the charge in the depletion layer. It is, therefore, apparent that the higher the doping of the 2 n- base 2, the less severe the effect of the charge is, since the parasitic charge in the passivation layer 3 may not be sufficient to affect the charge equilibrium at the surface of the device. Hence, the effect of the charge is more pronounced in devices rated at higher voltages. A negative charge in the oxide or passivation layer causes a positive charge layer made of holes to form at the surface in the termination area, which positive charge pushes the potential lines away from the main surface, thus forcing the entire potential to drop at the very edge of the device next to the field plate 6. In other words, each ring 1 does not support effectively part of the breakdown voltage. A positive charge in the oxide or the passivation layer results in an accumulation of electrons at the main surface in the termination area. This tends to retard the spreading and the growth of the depletion layer in between the p+ rings 1, which further results in sharp electric field peaks at the p+ floating ring/n- surface junctions. This, in turn, leads to premature breakdown. Therefore, charge of either polarity in the oxide or passivation layer can lower the rated breakdown voltage.
The success of a controllable semiconductor device at high or ultra-high voltages is almost entirely determined by a successful implementation of the edge termination. There are three main reasons which make the termination problem more difficult as the voltage ratings increase. Firstly, the number of floating rings increases significantly, and thus the wasted area and the ratio between the wasted area and the active area increases. This results in a poorer yield and a higher on- state voltage. Secondly, as the voltage increases, and accordingly the doping concentration of the base decreases, the device is more prone to parasitic field charge or passivation. charge effects, which may cause premature breakdown. Thirdly, as the number of rings increases, the control of the depth and spacing between the rings becomes even tighter than that for a relatively-lower voltage ten-nination, and therefore the termination effectiveness is very susceptible to process variations.
The aim of the invention is to provide a semiconductor device having an edge 30 termination structure which has a substantially reduced parasitic charge in the passivation layer.
3 The present invention provides a semiconductor device comprising an active area with a voltage termimation structure located adjacent to the active area at an edge portion of the device, the edge portion comprising a substrate region of a first semiconductor type, wherein the voltage termination structure comprises at least one first ten-nination region of a second semiconductor type, the or each first termination region having at least one of either second and third termination regions of third and fourth semiconductor types located at substantially opposing edges thereof, the second and third termination regions respectively having a higher semiconductor doping concentration than the edge portion substrate region and a lower semiconductor doping concentration than the first termination region(s).
Advantageously, the edge portion surrounds the active area, the three termination regions of the voltage termination structure extending around the edge portion, and preferably the three termination regions are formed as rings substantially surrounding the active area. The three termination regions may be provided in the region of an upper surface of the edge portion substrate region, the upper edges of the three termination regions being in alignment with one another, and adjacent to the upper surface of the edge portion substrate region.
Preferably, the or each first termination region extends deeper into the edge portion substrate region than the second and third termination regions.
Conveniently, the second and third termination regions of the voltage termination structure are implanted into the edge portion substrate region, and a passivation layer is provided over the upper surface of the edge portion substrate region. Preferably, the passivation layer is an oxide layer.
The semiconductor device of the invention overcomes the problem of parasitic charge in the passivation layer, and so reduces considerably the affect of this charge on the breakdown voltage of the device.
4 Advantageously, a channel stopper is provided at an extreme edge of the edge portion substrate region, adjacent to the upper edge of the substrate region, and a field plate is provided above the channel stopper.
In a preferred embodiment, the edge portion substrate region is formed of an n-type semiconductor material, and the or each first termination region is formed of a p-type semiconductor material. In this case, the second and third termination regions are formed of n-type material and p-type material, respectively, the p-type material having a lower doping concentration than the p-type material forming the first termination region(s), and the n-type material having a higher doping concentration than the n-type material forming the edge portion substrate region. Preferably, the first semiconductor type material is n- material, the second semiconductor type material is p+ material, the third semiconductor type material is n material and the fourth semiconductor type material is p material.
The invention will now be described in greater detail, by way of example, with reference to the drawings, in which:
Figure 1 is a sectional view of a known edge termination structure of a high voltage semiconductor device; Figure 2 is a sectional view of an edge termination structure of a high voltage semiconductor device constructed in accordance with the invention; and Figure 3 is a graph showing the breakdown voltages for the edge termination structures of Figures 1 and 2.
Refening to the drawings, Figure 2 shows the edge termination structure of a high voltage semiconductor device, where the active area is not shown. As with the structure of Figure 1, the edge termination structure of the invention includes a plurality of p+ floating rings 11 formed in a ndrift (base) layer 12, the rings surrounding the active area. The rings 11 are formed just below a passivation. layer in the form of a surface field oxide layer 13 in general alignment with a p- base 14 and a cathode 15 of the active area. At the extreme edge, the termination structure has a field plate 16 and a channel stopper 17.
Respective additional n and p shallow rings I I a and I I b are formed on opposite sides of each of the main p+ floating rings 11. These rings 11 a and 11 b have a lower doping concentration than that of the p+ rings 11, but a higher doping concentration than that of the n- drift layer 12 such that, at the breakdown voltage, either the p rings lla orthe n rings llb are fully depleted. If no charge is present, it is possible that both the p rings Ila and the n rings llb are depleted, hence further enhancing the effectiveness of the termination. If a parasitic negative charge is present in the oxide layer 13, the n rings 1 lb stop the formation of hole channels between adjacent p+ rings 11, and allow effective drop of the potential lines between the p+ rings. In this case, the n rings 1 lb are fully depleted. If a positive charge is present in the oxide layer 13, the p rings 11 a obstruct the formation of the abrupt n+ (electron layer) /p ring junction that would occur in the conventional case, and therefore eliminates the high electric field peaks at the surface. In other words, each of the p rings 11 a depletes entirely, and allows a smoother transition of the electric field from the n- drift layer 12 into the p+ rings 11. In case the polarity of the charge is known, the termination may include only one set of the rings I I a and I I b. For a negative charge, the n rings I I b are needed; and, for a positive charge, the p rings I I a are needed.
Such a termination technique was simulated on a 1.4kV Trench IGBT device (TIGBT), but could be used for any class of TIGBT, for which there already exists an optimised geometry for field ring spacings, where no charge is present in the oxide. The presented technique successfully overcame the problem of severe deterioration of the device's breakdown characteristic, when there was either negative or positive charge in the oxide. The presence of charge has a strong influence on the depletion layer spreading at the surface, because this charge complemented the charge in the depletion layer. A negative surface charge caused a positive charge layer of holes to form at the surface, which layer pushed the potential lines away from the main surface, resulting in an accumulation of potential lines at the very edge of the device. Therefore, each ring did not effectively support part of the breakdown voltage. A positive charge tended to retard the spreading of the depletion layer, and resulted in an accumulation of electrons at the surface, which had the effect of increased pressure on the p+/n surface junction, 6 resulting in a premature breakdown. This demonstrated that parasitic charge of either polarity, in the oxide, could lower the breakdown voltage.
In the case of a 1.4kV TIGBT, the optimum field ring spacings were determined for the case of having no charge in the oxide. The simulated breakdown voltage, for this case, was 1580V. When charge of either polarity was present in the oxide, the breakdown voltage deteriorated considerably. The values of breakdown voltage (Vbr) for different charges are given in the table below.
Charge -lel2 -5el I No Charge +5el I +lel2 Vbr 1180V 1100V 1580V 1500V 870V In order to reduce the influence of the negative interface charge, a continuous shallow (Imicron) ii-implant was provided between the first and the last p+ ring. This resulted in an increased breakdown voltage when compared with a device having no additional implant. Unfortmately, this n-implant had a negative influence on the breakdown voltage when a positive charge in the oxide was present. Accordingly, this method could only be used in the case where the value and sign of the interface charge had already been determined. A trade-off can be achieved when a selective n- implant is performed through the mask, so that it helps to reduce the influence of the negative charge on the breakdown voltage, and not greatly to deteriorate the breakdown characteristics, if there is a positive interface charge. Different placement of this shallow ii-implant, when simulated, had a different influence on the breakdown voltage, and as expected, the best placement of the n-islands was found to be on the side of the p+ field ring which is closer to the active area (the right-hand side in Figure 2). The mask openings were found to be dependent on the spacing between the two adjacent p+ rings. The spacing was chosen so as to be large enough to complement the charge in the oxide, and, on the other hand, small enough not greatly to deteriorate the breakdown characteristic, in the case of a positive interface charge. However, if, together with the shallow n-ring implanted on the side of the p+ ring which is closer to the active area (the right-hand side in Figure 2), there is also provided a shallow, 7 lowly-doped p-implant (2 microns, lel6) on the other side of the p+ field ring, the breakdown voltage was found to be little affected by the presence of either positive or negative charge in the oxide.
Figure 3 is a graph showing the breakdown voltage for the termination structure of structure of Figure I compared with that of Figure 2 against the charge level in the field oxide layer 3, 13 for a 1.4 kV IGBT, curve A being representative of the known termination structure, and curve B being representative of that described above with reference to Figure 2. As will be seen, the rings I I a and I lb optirnise the p+ rings I I to give a breakdown voltage of around 1.6 W. In the case of the known termination structure illustrated in curve A, both a positive sweep and a negative sweep in the oxide layer 3 results in a very significant degradation of the breakdown capability. In contrast, the termination structure of Figure 2 results in a variation of the breakdown voltage with the parasitic charge which, although present, is far less significant than that which is prevalent in the case of the conventional termination structure of Figure 1.
It will be apparent that modifications could be made to the semiconductor device described above. For example, in some cases, the termination structure could have a single floating ring 11. Moreover, the or each ring 11 need not be circular in form, any suitable configuration being possible. It is also possible for the ring(s) I I to extend only partially around the associated active area.
8

Claims (1)

  1. Claims
    1. A semiconductor device comprising an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device, the edge portion comprising a substrate region of a first semiconductor type, wherein the voltage termination structure comprises at least one first termination region of a second semiconductor type, the or each first termination region having at least one of either second and third termination regions of third and fourth semiconductor types located at substantially opposing edges thereof, the second and third termination regions respectively having a higher semiconductor doping concentration than the edge portion substrate region and a lower semiconductor doping concentration than the first termination region(s).
    2. A semiconductor device according to claim 1, wherein the edge portion surrounds the active area, the three termination regions of the voltage termination structure extending around the edge portion.
    3. A semiconductor device according to claim 2, wherein the three termination regions are found as rings substantially surrounding the active area.
    4. A semiconductor device according to any preceding claim, wherein the three termination regions are provided in the region of an upper surface of the edge portion substrate region.
    5. A semiconductor device according to claim 4, wherein the upper edges of the three termination regions are in alignment with one another.
    6. A semiconductor device according to claim 4 or claim 5, wherein the upper edges of the three termination regions are adjacent to the upper surface of the edge portion substrate region.
    9 7. A semiconductor device according to claim 5 or claim 6, wherein the or each first termination region extends deeper into the edge portion substrate region than the second and third termination regions.
    8. A semiconductor device according to any preceding claim, wherein the second and third termination regions of the voltage termination structure are implanted into the edge portion substrate region. 9. A semiconductor device according to any preceding claim, wherein a 10 passivation layer is provided over the upper surface of the edge portion substrate region. 10. A semiconductor device according to claim 9, wherein the passivation layer is an oxide layer. 15 11. A semiconductor device according to any preceding claim, wherein a channel stopper is provided at an extreme edge of the edge portion substrate region, adjacent to the upper edge of the substrate region. 20 12. A semiconductor device according to claim 11, wherein a field plate is provided above the channel stopper. 13. A semiconductor device according to any preceding claim, wherein the edge portion substrate region is formed of an n-type semiconductor material, and the or each 25 first termination region is formed of a p-type semiconductor material.
    14. A semiconductor device according to claim 13, wherein the second and third termination regions are formed of n-type material and p-type material, respectively, the p-type material having a lower doping concentration than the p-type material forming the first termination region(s), and the n-type material having a higher doping concentration than the n-type material forming the edge portion substrate region.
    15. A semiconductor device according to claim 14, wherein the first semiconductor type material is n- material, the second semiconductor type material is p+ material, the third semiconductor type material is n material and the fourth semiconductor type material is p material.
    16. A semiconductor device according to any preceding claim, wherein the device performs as a diode, a DMOSFET, a DMOS, IGBT, a MOSFET, a trench IGBT, or an MOS controllable power device.
    17 A semiconductor device constructed and arranged substantially as hereinbefore described with reference to Figures 2 and 3 of the drawings.
GB9918981A 1999-08-11 1999-08-11 High voltage semiconductor device termination structure Withdrawn GB2355110A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9918981A GB2355110A (en) 1999-08-11 1999-08-11 High voltage semiconductor device termination structure
EP00306255A EP1076363A3 (en) 1999-08-11 2000-07-24 High voltage semiconductor device
US09/636,353 US6445054B1 (en) 1999-08-11 2000-08-10 Semiconductor device

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GB9918981A GB2355110A (en) 1999-08-11 1999-08-11 High voltage semiconductor device termination structure

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GB2355110A true GB2355110A (en) 2001-04-11

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