GB2353635A

GB2353635A - A semiconductor device with quantum dots

Info

Publication number: GB2353635A
Application number: GB9916184A
Authority: GB
Inventors: Andrew James Shields
Original assignee: Toshiba Research Europe Ltd
Current assignee: Toshiba Europe Ltd
Priority date: 1999-07-10
Filing date: 1999-07-10
Publication date: 2001-02-28
Anticipated expiration: 2019-07-10
Also published as: GB2353635B; GB9916184D0

Abstract

A semiconductor device for example, a memory structure, bi-polar transistor, or a holographic type of optical storage device, comprises first 107 and second 103 dot layers separated by a first barrier 105 . Each of the first 107 and second 103 dot layers comprises at least one quantum dot. There is at least one aligned quantum dot provided by a quantum dot in the first dot layer aligned with a quantum dot in the second dot layer. The device further comprises means for separating an electron hole pair in an aligned quantum dot, and dipole detection means for detecting the presence of a dipole in at least one aligned double quantum dot. The dipole detection means may be a two dimensional carrier gas. An electric field may be used to separate the electron hole pair. A method of operating the semiconductor device is also disclosed. A memory device may comprise a grid of bit lines and word lines addressing a plurality of pixels. Each pixel being addressable by applying appropriate potentials to the bit line and/or the word line. At least one pixel may comprise a device having a plurality of optical storage means. At least one optical storage means may be capable of storing data due to an optical activation at a different wavelength than that of at least one other optical storage means.

Description

2353635 Optical Device

The present invention relates to the field of optical semiconductor devices, more specifically, the present invention relates to so-called low dimensional optical memory devices.

The electrons and holes in an ideal bulk semiconductor have a continuous spectrum of energy states. Confinement of the carriers in one or more dimensions modifies this energy spectrum by a quantisation of the kvector along the confinement direction(s). In a quantum dot the motion of the carriers is restricted in all three spatial dimenions. Consequently, the energy spectrum of the dots consists of a series of discrete levels. As the size of the quantum dot reduces, the energy spacing between these discrete levels increases. The Fermi exclusion principle dictates that no two electrons (or no two holes) can occupy the same quantum state. Thus, the maximum number of electrons which can occupy each electron level is two, corresponding to the up and down spin states. Similarly, each hole level has an occupancy of two. Optical transitions can occur between the discrete electron and discrete hole levels.

A quantum dot can be used to store charge to develop a memory structure for example, Imamura et al. Jpn. J. Appl. Phys. Vol. 34 (1995) L 1445L1447. Here, the device has a plurality of InAs quantum dot of different sizes. Upon illumination, an electron-hole pair is excited in the quantum dot. Due to the biasing of the structure, the electron is swept vertically down through the structure into an ohmic metal contact. The hole is trapped in the quantum dot. Due to the movement of electrons, a photocurrent flows. Only a finite number of holes can be stored in a dot. If this finite number is reached, no further holes-can be stored in the dots and hence no photocurrent due to dissociated electrons can flow. Thus, stored charge can by detected by a lack of photocurrent.

2 The carrier trapping properties of quantum dots is also illustrated in Yusa et al Appl. Phys. Lett. 70 (1997) 345. Here, a plurality of quantum dots are used to show trapping effects which occur when a two dimensional electron gas (2DEG) is illuminated.

Recently, a memory structure has been developed by Shields et al Appl Phys. Lett Vol 74, pp 735 (1999) and UK patent application number GB 9820192.4.

The memory structure disclosed in the above patent application and paper has a quantum dot layer and a two dimensional carrier gas layer which are separated by a barrier layer. For the purposes of this explanation, the two dimensional carrier is thought as being a two dimensional electron gas and the trapped carriers will be thought of as holes. However, a man skilled in the art will appreciate that the device can work with a two dimensional hole gas or where the carriers are either trapped electrons or holes regardless of the plurality of the two dimensional carrier gas.

During a write operation, i.e. to set a bit equal to 1, a quantum dot is illuminated with radiation of a predetermined wavelength corresponding to an optical transition of the quantum dot such that an electron-hole pair is created in the quantum dot. The electron is excited into the conduction band and the hole in the valence band. An appropriate electric field is present across the device such that the electron tunnels out of the quantum dot while the hole remains trapped. Without wishing to be bound by any theory, it is believed that a second electron-hole pair may also be photo-excited in the dot. After tunnelling of the electron out of the dot, this leaves two holes trapped within the quantum dot, thereby completely filling this valence band level.

During a read operation, the quantum dot is again illuminated with radiation of a predetermined wavelength. Consider, firstly, the case where holes have already been stored in the quantum dot by a write operation. If the valence band level of the dot is already fully occupied with holes, the Fermi exclusion principle prevents the excitation of electron-hole pairs by the incident light. Hence, there is no change in the charge state of the quantum dot due to illumination. On the other hand, if there are no holes 3 stored in the dot, the incident light will be able to excite electron- hole pairs with the dot. The photo-excited electrons will again be able to tunnel out of the quantum dot, leaving a hole trapped within the dot. Thus illumination leads to a change in the charge state of the dot. This change in the charge state of the dot can be sensed by a change in the characteristics of the two dimensional electron gas (2DEG). For example, the change in charge state of the dot has been shown to affect the conductivity. Thus, if a change in the characteristic of the 2DEG is observed after illumination, this can be interpreted as '0' and if no change is detected as 'I'.

Possible mechanisms for the way in which the disassociated charge affects the. characteristics of the 2DEG are discussed below:

The applicant does not wish to be bound by a particular theory or explanation. However, it is believed that characteristics of the first active layer can be affected by the trapped carriers through two main mechanisms. In the first mechanism, the excess carriers in the active layer have an opposing polarity to the carriers which are stored in the dots. In the second mechanism, the carriers in the active layer and the carriers trapped in the dots are of the same type.

The first mechanism will be explained using holes as the stored carrier and a detecting mean consisting of a 2DEG. However, it will be apparent to a person skilled in the art either electrons or holes can be stored in the quantum dots depending on the layer thickness and composition, doping polarities and applied biases.

A quantum dot is illuminated with a beam of radiation. The structure is biased so that it is energetically favourable for the electron to tunnel through the barrier to a 2DEG in the quantum well layer, leaving behind a hole stored in the quantum dot. This effects a change in the conductivity of the 2DEG.

Without wishing to be bound by any particular theory or explanation, the applicant believes that the change in conductivity is predominantly due to the positive charge 4 stored in the barrier which alters the band bending and hence persistently alters the conductivity of the 2DEG. Thus, depending on the actual configuration of the device, the conductivity of the 2DEG can either increase or decrease. It is also believed that where the stored carriers are electrons, the negative charge stored in the barrier will change the conductivity of the quantum well layer. In the case where the stored charges are electrons, the quantum well will support a two dimensional hole gas.

In the second mechanism, the carriers stored in the dots are of the same type as the carriers stored in the well. In the situation where the carriers in the quantum well are electrons, the stored carriers in the quantum dots are electrons. The applicant does not wish to be bound by any theory or explanation. However, it is believed that the dots contain excess electrons prior to illumination. The charged dots act as scattering centres for the electrons in the 2DEG, which consequently has a relatively low mobility. After illumination, the number of excess electrons in the quantum dots is reduced and the number of electrons in the 2DEG increases. A decrease in the negative charge in the dots results in an increase in the 2DEG conductivity. Also, the increase in the carrier concentration of the 2DEG causes an increase in the conductivity of the 2DEG.

However, there is a problem with the above structure in that it is a onceonly read memory, as the reading process will overwrite the previously stored data. This is because the read operation performed on an empty quantum dot (bit 0) will itself lead to holes being trapped in the dot and thus set the bit to be 1.

The present invention addresses the above problems and, in a first aspect, provides a semiconductor device comprising first and second dot layers separated by a first barrier layer, each of the first and second dot layers comprising at least one quantum dot and there being at least one aligned double quantum dot provided by a quantum dot in the first dot layer being aligned with a quantum dot in the second dot layer, the device further comprising means for separating an electron hole pair in an aligned quantum dot and dipole detection means for detecting the presence of a dipole in at least one aligned double quantum dot.

The means for separating an electron hole pair preferably comprises means for applying an electric field normal to the first and second dot layers. The separating means may also be provided by an internal field in the device due to band-gap engineering.

The applicant does not wish to be bound by any particular theory or explanation, however, it is believed that the high density memory operates in the following manner:

Generally, there will be a plurality of aligned quantum dots between the first and second dot layers, however, to aid explanation, the device will be described just with one aligned quantum dot. The quantum dot in the first layer will be called a storage dot. The quantum dot in the second layer will be called a sense dot.

Write Operation During a write operation, the storage quantum dot is irradiated with radiation of a predetermined wavelength such that electron hole pairs are photo-excited within the storage quantum dot. Electrons are created in the conduction band and holes in the valence band. The electric field across the device is set so that electrons tunnel from the conduction band of the storage quantum dot and escape from the region of the two quantum dots, while the holes remain trapped by the storage quantum dot. The quantum dot is illuminated so as to fill the valence band level with holes, which corresponds to bit 'I' being written to this dot.

Read Operation In a read operation, a lower electric field is applied across the device; lower than that for the write operation and the device is again illuminated with radiation of a predetermined wavelength. If bit '1' has previously been written to this quantum dot, so that the appropriate valence band level is fully occupied with holes, the illumination

6 is unable to excite electron-hole pairs within the quantum dot. Therefore, there is no variation in the charge state of either the storage quantum dot or the sense quantum dot.

On the other hand, if bit '0' has previously been written to the quantum dot, so that it is empty of holes, the incident light is able to excite electron-hole pairs within the quantum dot. The electric field is set so that holes are trapped within the storage quantum dot, while the photoexcited electrons are swept into the sense quantum dot. Since the electric field for reading is lower than the electric field for writing, the electrons are not swept out of the storage quantum dot, instead there are trapped within the storage quantum dot. Thus, a dipole is formed between the electrons trapped in the sense quantum dot and the holes are trapped in the storage quantum dot. This dipole is detected by the means described below.

Thus detection of an electrical dipole under optical illumination at the predetermined wavelength means that the dot was storage dot was empty of holes and corresponds to bit V. On the other hand, if no dipole is detected under illumination by the predetermined wavelength, the dot must have been occupied by holes and corresponds to bit I 1 1.

A dipole detection means, for example, a means for detecting a variation in the characteristics of a carrier gas in the vicinity of the first and second quantum dot layers, can be used to detect the presence of a dipole and hence can be used to detect whether or not the quantum dot has previously been written with bit 1.

After the read operation, the electric field across the dot layers can be reduced to allow the electrons trapped within the sense quantum dot and the holes trapped within the storage quantum dot to recombine. Also, the electrons trapped in the sense quantum dot will combine with holes in the storage quantum dot over time, after the illumination is switched off. It, should be noted, because the electron and holes which are excited during the read operation are able to recombine with one another after the read operation, this will not overwrite the previously stored information.

7 For optimum operation, it is highly preferable that during the read or the write operations, carriers are not photo-excited in the sense quantum dot. Therefore, preferably, the band gap energy of the sense quantum dot is larger than the band gap energy of the storage quantum dot, so that the sense quantum dot is transparent to light with an energy equal to the band gap of the storage quantum dot. The sense quantum dot can be between the storage quantum dot and the active layer, it may also be located on an opposite side of the storage quantum dot to the active layer.

This variation in the band gap between the quantum dots of the first dot layer and the second dot layer can be achieved in a number of ways. For example, the first and second dot layers can be made out of different materials or materials with different alloy compositions. Also, the strain environment of the dots in thefirst and second layers could also be varied to provide a difference in the band gap of the quantum dots. Preferably, the first dot layer forms a type I heterojunction with its barrier materials and the second dot forms a type II heterojunction with its barrier material..

The detecting means can either measure a change in the transport characteristics of the active layer or the optical characteristics of the active layer. For example, a change in the optical characteristics due to a change in the carrier concentration or electric field across the layer induced by a dipole in an aligned double quantum dot could be detected. Changing the carrier density in the active layer alters its absorption or emission spectrum. A change in the electric field across the active layer will cause a change in the energy or intensity of its absorption or emission spectrum. Changes in the carrier concentration, mobility or field across the layer also manifest themselves in the transport characteristics of the layer.

The first barrier layer will generally have a larger band gap than the first dot layer and the second dot layer.

8 Preferably, there will also be a second barrier layer located between the active layer and the closest of the dot layers to the active layer. However, this is not always required. For example, in certain device configurations, both the first active layer and the second "barrier layer" may be the same material e.g. GaAs. The GaAs barrier layer is an effective barrier layer even though it has the same band gap as the active layer.

There may also be provided a third barrier layer, which is located on an opposite side of the first dot layer to the second dot layer. This third barrier layer will have a larger band gap than the first dot layer. It may also have a larger band gap than the first barrier layer. The third barrier layer prevents trapped carriers tunnelling out of the first dot layer. The third barrier layer may be doped to provide excess charge for the first dot layer.

Preferably, excess carriers are supplied to the active layer from a fourth doped barrier layer. More preferably, the fourth barrier layer is provided on an opposing side of the active layer to the dot layers. The fourth barrier layer may preferably be a modulation doped barrier layer comprising an undoped spacer layer adjacent the active layer and a doped layer adjacent the undoped spacer layer.

Barrier layers may be located adjacent to either or both of the first and/or second dot layers. However, in some cases, a thin layer may be formed between a barrier layer and a dot layer to aid smooth growth of the dots during fabrication. Such a thin layer will be referred to s a growth smoothing layer. Typically, if the dots are formed by depositing InAs or InGaAs, the layer may be GaAs.

To produce a memory structure with a good retention time, it is preferable if there is a large confining potential for the trapped carriers. The confining potential is largely dependent on the characteristics of the second and third barrier layer.

To produce a large confining potential, it is advantageous to maximise the carrier potential discontinuity between the dot layers and the barrier layers. The 'size' of the 9 confining potential is dependent on both the potential height of the barrier layer and the width of the barrier layer itself. A large barrier is taken to mean a barrier which has a large carrier potential discontinuity with respect to the quantum dot layer and/or a barrier which is relatively wide.

For example, if the holes are stored in InAs quantum dots, a large trapping potential can be created by choosing AlAs or Al,,Gal-,,As as the barrier material both above, below and between the dot layers.

The electric field normal to the layers can be varied to control the tunnelling of photo excited electrons and holes through the structure.

The first barrier layer can be fairly thin, for example less than 30nm. The width of the first barrier is generally determined by the limits of the fabrication technology available to produce InAs aligned quantum dots, at present, good aligned quantum dots can be produced with a first barrier width of about 15nm.

More preferably, the active layer and the second dot layer are coupled layers, preferably, weakly coupled layers. The coupling between the layers needs to be sufficiently strong to allow tunnelling of some carriers from the dot layer closest to the active layer. However, the coupling must also be sufficiently weak to suppress the tunnelling of carriers from the active layer back to the dot layers.

The quantum well can be thought of as a sheet of charge located within the active layer. The position of the quantum well within the active layer, with respect to the adjacent layers of the active layer is dependent on the band structure. In order to achieve sufficiently weak coupling between the quantum well and the second dot layer, it is preferable if the separation between the quantum well and the second dot layer is between 10 rim-and 500 rim.

For example, if the plurality of quantum dots in for the second dot layer are InAs (or AlInAs) and the active InGaAs (or GaAs), the second barrier layer could be AlAs or Al.,Gal-,As or GaAs with a width of between 10 nm and 500 nm. More preferably between 10 nm and 200 nm.

To detect the presence of a dipole formed in an aligned double quantum dot, it is preferable if at least two ohmic contacts are provided to the active layer. A voltage will be measured between these two contacts or a current flowing between the two contacts. For an accurate reading, it is more preferable if a four-terminal voltage measurement is used.

Preferably, the measured characteristic from the active layer will be differentiated with respect to time or the change in the characteristic will be measured with respect to time. When the signal is differentiated, the differentiated signal comprises a plurality of pulses, these pulses can be counted by a pulse counter.

Devices according to a first aspect of the present invention either with or without a doped barrier layer overlying the first dot layer, can also be used where the tunnelling carriers are holes.

If the electron hole pair is separated by an externally applied electric field normal to the dot layers, this can be provided by a front-gate overlying the structure. More preferably, a back-gate is also provided in addition to or instead of the front gate. Either or both of the front or back gates can be metal or a doped semiconductor. It is preferable if the front-gate is transparent to radiation with an energy close to that of the quantum dot band-gap of the first dot layer.

The means for applying electric fields may also comprise a p-type terminal and n-type terminal located on opposite sides of the first and second dot layers. In other words, the structure is sandwiched between doped p and n-type layers.

I I The energy spectrum of the quantum dots is dependent on the dot size, shape and local environment. Hence, different quantum dots possess different ground state energies and different optical transition energies. Preferably, as mentioned previously, there may be a difference between the size of the dots in the first and second dot layers. The device may also comprise quantum dots of different sizes within each layer which require radiation of different frequencies to excite an electron-hole pair.

A convenient method of forming a layer of quantum dots is by using the StranskiKrastanow growth mode wherein a first layer is grown on a substrate with a different lattice constant to the first layer. The first layer proceeds by three dimensional island growth and small quantum dots can be produced with a lateral size typically less than 50 nm. A preferable material system for producing this device uses the growth of InAs, InGaAs or InAlAs quantum dots with GaAs or (A]Ga)As barriers. For instance, high quality quantum dots can be formed by depositing 1.7 - 3 monolayers of InAs on AI,,Gaj_,,As.

The device may be formed such that the active layer is grown before the quantum dot layer. However, the ordering may be reversed i.e. the active layer formed overlying the dot layer. Other lattice mismatched systems can be used such as InGaN or AJGaN. This material has a shorter wavelength, allowing a smaller diffraction limited light spot size and therefore a greater storage density. Another.possible system for producing the dots uses strained SiGe Heterostructures.

The Stranski-Krastanow growth mode can also be used to produce aligned double quantum dots. This involves depositing a first strained layer which self-assembles into a layer of quantum dots. This is followed by a first barrier layer. Then a second strained layer is deposited which selfassembles into a second layer of quantum dots. It has been found that if the first barrier layer is thinner than a certain thickness, the quantum dots in the second quantum dot layer spatially align above the dots in the first. This is thought to be because the strain created by the dots in the first quantum dot layer seeds the growth of quantum.dots in the second quantum dot layer. For the growth of 12 InAs dots on Al,,Gal,As, for instance, the second barrier layer should be no more than about 15= thick. Conveniently, it has been found that the dots in the second quantum dot layer have a larger band gap energy than those in the first.

The above description of growth has used the terms "first quantum dof' layer etc. The terms ":First" and "second" in the above paragraph refer to the layers in order of growth and are not intended to suggest that the storage dot layer must be grown before the sense dot layer. The dot layers may be fabricated in any order. However, due to the dots in the second grown layer having a larger hand gap than the dots in the first grown layer, if the dots in the first and second dot layers are fabricated from the same material, the dots in the second grown dot layer lend themselves more easily to sense dots which preferably require a larger band gap.

The device may also be fabricated from an Si02/Si based system.

The device of the first aspect of the present invention could also be used as a holographic type of optical storage device. Here, the optical beam is split into a signal beam and a reference beam. The signal beam is passed through a spatial light modulator in order to encode the information to be stored. The signal and reference beams are focused onto the surface of the sample where they produce an interference pattern. This creates a spatial variation in the carrier occupancy of the dots which acts to store information in the dots, The information can be recalled by illuminating the same area of the sample by the reference beam. The stored variation in the dot occupancy acts to diffract the reference beam and thereby to recover the signal beam which is detected by a suitable means, such as a charge coupled device array.

The structure may be provided with upper and lower cladding layers to channel light in a direction parallel to the plane of the first active layer. The structure may also be provided with guide means to confine light to a region of the active layer, for example, a stripe type waveguide could be used.

13 The device may also be illuminated in the plane of the dot layers instead of or in addition to illuminating generally perpendicular to the layers.

The present invention is primarily intended for use as an optical memory. Therefore, preferably, an optical memory is provided comprising a plurality of pixels wherein each pixel comprises a device according to the first aspect of the present invention.

Each device can be addressed by applying a voltage to a word-line or a bit-line, or both, in the conventional manner. However, the present invention provides yet another dimension to the memory as each pixel can comprise a plurality of quantum dots each of which have a different predetermined excitation energy. Therefore, not only is it possible to address each pixel by varying the voltages on the bit-line and the wordlines, it is. also possible to address a single quantum dot by illuminating a pixel with a specific wavelength. Preferably a monochromatic light source should be used for this excitation such as a laser diode. Each of these pixels may contain one or more switching transistors for addressing of the appropriate device.

The bit-line and word-line voltage can be applied directly to the semiconductor device to provide the field for either reading or writing to the quantum dot. The array of pixels can be illuminated by a relatively broad beam of light, which can illuminate more than one, or all, of the pixels simultaneously. However, in this case only the active pixel i.e. the pixel with the correct word and bit-line voltages applied to it will store or provide data. Also, if the wavelength of the input beam can be varied then another dimension of storage is provided since a plurality of dots may be provided with different band gaps and hence different excitation energies.

Therefore, it is preferable if the optical device of the first aspect of the present invention used in the pixel comprises a plurality of aligned double quantum dots, wherein at least one aligned quantum dot has a different excitation energy to that of the other aligned quantum dots.

14 A device according to a first aspect of the present invention is a subset of such an addressable optically active memory. Therefore, to a second aspect the present invention provides a memory structure comprising a grid of bit-lines and word-lines defining a plurality of pixels, each pixel being addressable by applying potentials to the bit- line or word-line, at least one pixel comprising a device having a plurality of optical storage means, wherein at least one optical storage means capable of storing data due to optical activation at a different wavelength to that of at least one other optical storage means.

Therefore, the memory according to a second aspect of the present invention is addressable via two voltages and a wavelength. A method of operating such a device could comprise the steps of applying one or both of the voltages to select the pixel and illuminating with light with a wavelength which can excite a transition in the required memory element of the pixel.

The terms bit-lines and word lines have been used as these are well understood in the art to mean a grid of wires, which can be used to address a pixel.

The device having optical storage means may be provided by any optically activated memory structure. Preferably, the optical device of the first aspect of the present invention is the optical storage means.

Alternatively, the device may be addressed by a focused light source which can be scanned over the surface of the device into different pixels.Preferably this is a monochromatic light source such as a laser diode. Preferably the light is focused to a spot with a diameter of 10 microns or less. In this case it is possible to deflect the focused laser spot across the surface of the device using a pair of mirrors mounted on galvanometers.

Therefore, a method of operating such a device using a broad beam which would illuminate more than one pixel comprises the steps of setting the word-line and/or the bit line voltage to switch a pixel into a read mode or a write mode; illuminating a plurality of pixels including the pixel which is in the read mode or the write mode.

A method of operating the above device where the beam diameter is such that a single pixel could be illuminated could comprise the steps ofsetting the word and/or bit line voltage to switch a pixel into a read mode or a write mode; scanning a read/write beam across the device to the position of the pixel which is in the read mode or write mode, and illuminating the said pixel.

The step of scanning the read/write beam could be performed by moving the beam via moving mirrors. The mirrors could be controlled by galvanometers.

In a third aspect, the present invention provides a method of operating the device of the first aspect of the present invention, the method comprising the steps ofapplying a field across the dot layers sufficient to allow carriers of a predetermined polarity to tunnel from the first dot layer to the second dot layer under illumination; selectively illuminating one or more of the plurality of quantum dots with a beam of radiation to excite at least one electron-hole pair such that at least one carrier can tunnel from the first dot layer to the second dot layer; and detecting the presence of a dipole in an aligned double quantum dot.

The method according to a third aspect of the present invention is primarily intended as a "read" operation.

More preferably, the method also comprises a "write operation" which can be performed before or even after a read operation.

16 Therefore, it is preferable if the method also comprises a step of changing the electric field across the device such that the field can be changed between a field configured to allow a carrier to tunnel from the first dot layer to the second dot layer wherein the carrier becomes trapped in the second dot layer and a field configured to allow a carrier to tunnel from the first dot layer such that the carrier does not become trapped in the second dot layer.

For a "write" operation the carrier does not become trapped in the second dot layer.

The device has been described with just two dot layers, a sense dot layer and a storage dot layer. However, the device could be fabricated with a plurality of dot layers such that one layer acts as a storage dot layer and one or more of the plurality of dot layers acts as a sense dot layer. In some cases, this might be useful to enhance confinement between the storage dot layer and the sense dot layer during the read operation.

The device may also comprise a plurality of first and second dot layers separated by a tunnel layer and means for each of the plurality of first and second dot layers of detecting a dipole between the first and second dot layers.

The present invention will now be described a way of example and with reference to the accompanying figures in which:

Figure I shows a schematic band structure of a device with a storage quantum dot and a sense quantum dot; Figure 2 shows a schematic band structure of the device in Figure I with an electric field applied;

Figure 3 shows the device of Figures I and 2 with a dipole detecting means in the write mode; 17 Figure 4 shows the device of Figure 3 in an inactive mode; Figure 5 shows the device of Figures 3 and 4 during reading of an empty dot; Figure 6 shows the device of Figures 3 to 5 during reading of an occupied dot; Figure 7 shows the device of Figures 3 to 6 in the re-set mode-, Figure 8 shows a schematic band structure of a semiconductor device for which the two quantum dot layers are made of different materials, Figure 9 shows the device of Figure 8 in operation; Figure 10 shows a pixel of a memory device using a semiconductor device as described with reference to any of Figures I to 10; Figure I I shows a device according to an embodiment of the present invention in situ with a laser beam; Figure 12 shows a part of absorption of a laser beam by the storage dots against wavelengths of the laser beam; Figure 13 shows a layer structure of a device in accordance with an embodiment of the present invention; Figure 14 shows the device of Figure 13 when charged in a read mode; Figure 15 shows possible variations in the layer structure of a device in accordance with an embodiment of the present invention; 18 Figure 16 shows an embodiment of the device configured as a field effect transistor;

Figure 17 shows a band structure of the device of Figure 16; Figure 18 shows a schematic view of the design configured as a hetero junction bi-polar transistor; Figure 19 shows the band structure of the device of Figure 18; Figure 20 shows a semiconductor device in accordance with an embodiment of the present invention fabricated from silicon; and Figure 21 shows the semiconductor device of Figure 21 configured as a field effect transistor.

Figure I shows a quantum dot or a storage dot I separated from a second quantum dot or sense dot 3 via a barrier layer 5. The band gap Egi of the storage dot I is smaller than the band gap Eg2 of the sense dot 3. It is desirable if the sense quantum dot has a larger band gap energy than the storage quantum dot as there should be a radiation energy which can only excite carriers in the storage quantum dot and not the sense dot.

Figure 2 shows the structure of Figure I with an electric field applied. Initially the device will be described with electrons as the tunnelling carrier. However, it will be appreciated by those skilled in the art and explained hereinafter that holes could also be the tunnelling carrier. Holes can form the tunnelling carrier if the electric field is applied in the opposite direction.

Upon illumination with radiation of a predetermined energy, an electron hole pair is excited in the storage quantum dot 1. The energy of the radiation is low enough not to excite electron-hole pairs in the sense quantum dot. The electron hole pair is created such that the hole is excited in the valence band layer 7 of quantum dot I and the 19 electron is excited in the conduction band layer 9 of quantum dot 1. Due to the electric field, the electron in layer 9 tunnels through barrier 5 into the conduction band 11 of the sense quantum dot 3.

Depending on the magnitude of the applied electric field across the dots 1 and 3, the electron will either be trapped within the conduction band 11 of the sense quantum dot 3 or it will tunnel again out of the conduction band of the sense quantum dot 3.

If the electric field is such that the electron becomes trapped in conduction band 11, a dipole is formed by the positive charge in the storage quantum dot 1 and the negative charge in the sense quantum dot 3. In the present invention this dipole is detected.

Figure 3 shows a write operation. In this device, a two dimensional electron gas is used both to detect the dipole between the sense 1 and storage 3 quantum dots and also to receive the tunnelling carriers.

As described in relation to Figures 1 and 2, a storage quantum dot and a sense quantum dot are separated by a tunnel barrier 5. A second tunnel barrier 13 separates the 2DEG layer 15 from the sense quantum dot 3. When the storage quantum dot 1 is irradiated with illumination near the band gap of the first quantum dot 1 (but less than the band gap of the sense quantum dot 3), an electron - hole pair is excited in the storage dot 1. The electric field is set so that it is energetically favourable for an electron to tunnel from the conduction band 9 of the storage quantum dot 1 to the conduction band 11 of the sense quantum dot 3 and through to the conduction band 17 of the 2DEG 15. A hole 19 is trapped in the valence band of the storage quantum dot 1. Further illumination results in the trapping of a second hole within the valence band of storage dot 1. Due to the Pauli exclusion principle, it is not possible to add more than two holes into this valence band level of the storage quantum dot 1.

A "blocking" layer 10 is provided overlaying the storage dot layer 9. This is a large barrier layer which prevent carriers trapped in the storage dot 9 from tunnelling out of the storage dot.

Figure 4 shows the same device as Figure 3 but here, the electric field is such that tunnelling of the electron from the conduction band 9 of the storage I quantum dot to the conduction band 3 of the sense quantum dot is suppressed. This is because the conduction band I I of the sense quantum dot has a higher energy level than that of the conduction band 9 of the storage quantum dot. A device with this electric field would not allow a write (or even a read) operation.

Figure 5 shows the device configured for a read operation. Here, the storage dot I which is being read is an empty dot. The storage quantum dot I is irradiated and an electron hole pair is photo-excited. The electron is excited into the conduction band 9 of the storage dot I and tunnels due to the electric field into the conduction band I I of the sense quantum dot 3. However, the electric field here is not large enough to allow tunnelling from the conduction band I I of the sense quantum dot into the conduction band 17 of the quantum well 15. Therefore, the electron becomes trapped in the conduction band I I of the sense quantum dot 3. Meanwhile the photo-excited hole is trapped in the valence band of the storage dot 1.

Thus, a dipole is formed by the positive charge in the storage quantum dot I and the negative charge in the sense quantum dot 11. This dipole affects the characteristics of the quantum well 15. Hence, the presence of the dipole can be detected by measuring a characteristic of the quantum well 15, such as its conductivity.

After reading the device is returned to inactive mode, for which the electric field is such that the electron and hole photo created in the reading process in the storage and sense quantum dots recombine. However, this field does not allow electrons to tunnel from the 2DEG to recombine with hole trapped in the storage dot due to a write process.

21 Figure 6 shows the read operation for an occupied dot i.e. a dot which has been previously written to. Here, the valence band of the storage quantum dot has been filled during the write operation. Subsequent illumination will not cause electron-holes to be photo-excited as the valence band of the storage dot is full and cannot accommodate any more holes. Hence, illumination does not change the charge trapped within the storage or sense quantum dots. Consequently no change is observed in the characteristic of the quantum well, such as its conductivity.

Although it is not desirable to erase or change the data in the device during the read operation, it is preferable to provide a memory whereby the memory can be re-set. This can be done as shown in Figure 7 by varying the field across the device so that electrons tunnel from the conduction band of the quantum well layer 15 into the storage quantum dot I and re-combine with the holes trapped in the storage quantum dot 1.

As previously mentioned, the dot layers do not have to have the same composition. Figure 8 shows a double dot layer where one has a type I band gap and dot layer 3 has a type H band gap. There is no confining potential or trap electrons in dot layer 3 as the conduction band level I I of the sense quantum dot is higher than the conduction band level of the barrier layer 5. The valence band edge of the sense quantum dot 3 is higher than the valence bandage of the storage quantum dot 1, thus it is energetically favourable for holes to tunnel from the storage quantum dot to the sense quantum dot 3 as shown in Figure 9.

Figure 10 shows a pixel or element of a memory structure using the devices described above. The memory device would consist of an array of such pixels. Each pixel can be addressed individually by applying biases of the appropriate levels to the appropriate word 307 and bit 309 lines. Applying a voltage to the word line 307, turns the switching transistor 302 on, and thus applies the voltage on the bit line 309 to the gate of the device 303. The value of this voltage determines whether the pixel is in write, read, inactive or reset mode. Thus an appropriate voltage level should be applied to the bit line 309 to ensure the desired function of the pixel. In this way it is possible to operate 22 the device by illuminating all the pixels simultaneously. Only the pixel which is addressed by the appropriate word and bit line voltages will be sensitive to the incident light. Hence only this pixel will have data written to the pixel, or data written from the pixel, depending upon value of the voltage applied to the bit line. The advantage of this method is that it avoids having to scan the illumination between different pixels. Thus this addressing method allows for faster reading and writing operation of the device.

Figure I IA shows a memory structure 701 comprising a plurality of pixels 703. Each pixel is addressable by a word-line or a bit-line (not shown). The irradiating beam 705, which can either be writing or reading data illuminates a plurality of pixels. However, only the active pixel 707 which has the current voltages applied on the word and bitlines to allow the device to read or write as required can store or provide data.

Figure I IB shows a variation on the device of Figure I IA. Here, again, the device comprises a plurality of pixels 703. Except here, the read/write beam 705 is focused onto a specific pixel to read and write data to that pixel. The beam is guided via mirrors 709 and 711 which are actuated by galvanometers. The laser 705 is focused to a spot size of roughly the same as the pixel at the sample surface. For this configuration, the pixel might have dimensions of about 10Lms or less. This forms an x-y deflection system in the plane of the array which permits fast random access to a large data volume. The system could consist of several such laser beams formed by using several laser diodes or alternatively by optically splitting a single laser beam.

It will be apparent to those skilled in the art that the pixel can be designed in other ways to achieve a similar function.

As an alternative, the device may be addressed optically by focusing the light source to a spot of similar diameter to the pixel and scanning the illumination source between the different pixels of the device. The illumination source might correspond to a laser diode focused to a spot diameter of preferably between 0.25 and 10 microns. The 23 illumination source may be scanned in the plane of the surface of the device using two mirrors attached to galvanometers.

Figure 12 shows a graph of the absorption of the storage dot layer against wavelength. The dots are of different sizes and hence, have a plurality of different transition energies.

Figure 13 shows an example of a structure which can be used for the memory device of the present invention. In the structure of Figure 13, the 2DEG is omitted for clarity. On top of the 2DEG layer (not shown) is a lower barrier layer 101. On top of the lower barrier layer is formed the second dot layer 103. This layer will form the sense dots. As previously mentioned, this layer can be formed by the Stranski-Krastanow growth technique. On top of the first dot layer is formed a middle barrier layer 105. On top of the middle barrier layer is formed an upper dot layer 107. At least some of the dots in the upper dot layer 107 align with the dots in the lower dot layer 103 to form aligned double quantum dots. An upper barrier layer 109 is formed overlaying the storage dot layer.

Figure 14 shows the structure of Figure 13 after a dot has been illuminated, following the description accompanying the read operation, an electron hole pair is excited in a dot in the storage dot layer 107, the electron is excited into the conduction band and tunnels into the conduction band of the aligned sense quantum dot in the sense dot layer 103. This leaves a positive charge (due to the disassociated hole trapped in the valence band) in the storage dot layer 107 and a negative charge due to the trapped electron in the conduction band of the sense dot layer. These charges set up a dipole which can be detected by, for example, a 2DEG.

Figure 15 shows typical layer structures and their conduction band profiles which may be used to fabricate the devices of the first aspect of the present invention. There are many methods for producing quantum dots. For example, they can be produced by photolithographic techniques, electron lithography etc. A preferable method is to use 24 the Stranski-Krastanow growth mode. When a first layer is grown on top of a layer with a different lattice constant from the first layer, the first layer forms into islands. In other words, 3D islands are formed on the growth surface, which when capped with a barrier material, produces a plurality of quantum dots. The device according to the first aspect of the present invention requires two layers of quantum dots and at least one of these dots must be aligned. The alignment of two layers of quantum dots can also be achieved by using the Stranski-Krastanow growth mode. If a second layer of dots is grown on top of the barrier layer (which is grown on top of the first layer) then the spatial positions of the dots in the second layer will align with those in the first layer. It has been found that the dots in the second layer are larger than the dots in the first layer and have a lower band gap energy. Thus this provides a very convenient method for producing two coupled layers of quantum dots, in which the average band gap energy of the dots in each layer is different.

In Figure 15A, a doped barrier layer 41 of AlGaAs is formed on top of a substrate or buffer layer 43. An undoped space layer 45 is then formed on an upper surface of the doped barrier layer 4 1. This undoped space layer 45 and the doped barrier layer 41 together form a modulation doped barTier layer. A 2DEG layer 47 of GaAs is formed overlaying the undoped space layer 45. An undoped AlGaAs layer 49 is formed overlaying the GaAs 2DEG layer 47.

A doped layer 51 is then epitaxially grown on an upper surface of the barrier layer. This layer is InAlAs which has a substantially different lattice constant from AlGaAs. Thus, a plurality of quantum dots are formed. A further barrier layer 53 of AlGaAs is formed overlaying the quantum dot layer 5 1. Then, a further layer of InAlAs is epitaxially grown on the upper surface of barrier layer 53. This layer 55 also forms a plurality of dots and these dots substantially align with the dots in the first dot layer 5 1. The structure is then finished with a barrier layer of A]GaAs. Thus, two layers of quantum dots 5 1 and 5 5 are formed.

A schematic band structure for Figure 15A is shown in the right of the diagram. In the "write" mode, carriers can tunnel from a dot in layer 55 through a dot in quantum dot layer 51 and into the 2DEG in layer 47.

Figure 15B shows a similar structure to that of 15A. For comparison, the layers are numbered the same as Figure 15A. Here, an AlAs (or a A]GaAs) tunnel barrier 49 is present between the first dot layer 51 and the 2DEG layer 47. The schematic band structure shows that the tunnel barrier 49 is higher in this case than in the structure of Figure 15A. The AlGaAs tunnel barrier 49 has a different Al content to layer 49 in Figure 15A or layers 41 and 53 in Figure 15B.

Figure 15C shows again a variation on the structure of Figure 15A. The barrier layers 41, 49 and 53 and the space layer 45 GaAs and the 2DEG layer 47 is InGaAs. The dot layers 51 and 55 are formed from either InAlAs or InAs.

Figure 15D shows again a slight modification on the structure of Figure 15C. Here, the tunnel barrier 49 is either AlAs or AlGaAs. This provides a larger tunnel barrier 49 as can be seen by comparing the band structures of Figure 15C and Figure 15D.

Figure 15E shows a slight modification on the structure shown in Figure 15C. Here, the doped barrier layer 41 and the undoped space layer 45 are AlGaAs. These layers have a larger band gap than GaAs. Therefore, it can be seen in the band structure of Figure 15A that the conduction of band edge is higher for these layers.

Figure 15F shows a further modification on the structure shown in Figure 15A. Here, the tunnel barrier 49 is also AlGaAs. The band structure shows a larger tunnel barrier 49 than that shown for the structure in Figure 15E.

Although all the structures shown in Figure 15 show dot layers of InAs, it should be appreciated that the dots can be made from different materials, for example, the storage dot can be made from InAs, the sense dot could be made from GaSb.

26 Figure 16 shows an embodiment of the present invention. Here, thefield normal to the active layers is controlled by a front-gate and a back-gate. Essentially, the structure is a field effect transistor. A p+ back-gate 73 is formed on the upper surface of a buffer layer or a substrate 71. An undoped barrier layer 75 is formed overlaying an upper surface of the back-gate 73. A modulation doped barrier layer 81 is formed overlaying an upper surface of the undoped barrier layer 75. The modulation doped barrier layer has a doped barrier layer and an undoped space layer. A quantum well layer is formed on the upper surface of the space layer 8 1. A tunnel barrier layer 85 is then formed on the upper surface of the quantum well layer 83. A double dot layer 87 is then formed on the upper surface of the tunnel barrier layer 85. The upper dot layer comprises a layer of sense dots (87B in Figure 17) which are formed overlaying the upper surface of the tunnel barrier layer 85 and a layer of storage dots (87A) which is separated from the layer of sense dots by a tunnel barrier 88. A barrier layer 89 is then formed overlaying the layer of storage dots 87A. Then a capping layer is formed over the layer of storage dots 87A. A semi-transparent Schottky gate is evaporated on the surface of the sample to form a front gate. A Schottky gate is often preferable for this type of structure as the structure is in an inactive mode when the Schottky gate is earthed. In a memory device comprising a plurality of pixels, it is preferable if the inactive state of the device corresponds to zero applied volts.

Two ohmic contacts 93 and 95 which form a source and drain respectively are made to both the quantum well layer 83 and the dot layers 87. A backgate contact 97 is made to the back-gate 73 and a front-gate contact 99 is made to the front-gate 9 1. A bias can be applied between the front- gate 91 and the back-gate 73 so as to modulate the electric field normal to the quantum well layer 83 and the dot layers 87.

Figure 17 shows the band structure of the device of Figure 16. For simplicity, the layers in the -band structure have retained the same reference numerals as for Figure 16. The diagram shows the device in its inactive state, as described earlier, where the device can not be written to, or read from under illumination. For the arrangement 27 shown, the inactive state has been designed to occur when the potential of the front gate and 2DEG are the same, i.e. with OV applied between the gate and an Ohmic contact. For the biased conditions shown, the conduction band edge 10 1 of the quantum well layer 83 lies below that of the first electron level 103 of the sense dot layer 87B. Also, the lowest electron level 105 of the storage dot layer 87A lies above the conduction band edge of the 2DEG 83 and below the lowest electron level 103 of the sense dot layer 87B.

The device can be placed into read mode, or into write mode, by applying an appropriate bias between the front gate contact and an Ohmic contact to the 2DEG. In this case a negative bias is applied to the gate in read mode, in order to allow electrons photo-excited in the storage dot to tunnel into the sense dot, but not into the 2DEG. Applying a negative bias to the front gate has the effect of raising the potential of the back gate, thereby increasing the electric field across the double quantum dot region. For write mode, a larger negative bias is applied to the front gate with respect to one of the Ohmics, so that electrons photo- excited in the storage quantum dot are able to tunnel into the 2DEG layer. The device can be reset by applying a positive bias to the front gate with respect to one of the Ohmic contacts, so that electrons tunnel from the 2DEG into the storage dot, where they recombine with trapped holes.

Figure 18 shows a hetero junction bi-polar transistor structure. The simplified structure shown in Figure 18 has a semi-insulating substrate or buffer 120 with an emitter layer 122 formed in its upper surface. A base 124 comprising a plurality of layers (which will be described with reference to Figure 19) are formed on an upper surface of the emitter layer 122. A lightly doped p- type collector 126 and a heavily doped p+ collector 128 are formed on the upper surface of the base 124.

Two ohmic contacts 130 and 132 corresponding to a source and drain are provided to the base. A collector contact 134 is made to the p+ collector 128 and an emitter contact 126 is made to the emitter layer 122.

28 The conduction and valence band profile of this device are shown in more detail in Figure 19. The collector layers 126 and 128 are p-type. The base layer 124 is n-type and the emitter layer is p-type. The base section 124 comprises an undoped section 138, an n+ barrier region 140, a quantum well layer 142 which is separated from the sense quantum dot layer 144 via a barrier layer 146. A storage dot quantum layer 148 is separated from the sense quantum dot layer 144 via a barrier layer 150. The field across the base can be modulated by applying appropriate biases across the emitter and collector with respect to the Ohmic contacts to the 2DEG. By varying the bias between the collector contact 136 and one of the Ohmic contacts to the 2DEG it is possible to control the electric field across the double quantum dot region. The device can thus be set into the inactive, read, write and reset modes in a similar manner to the FET device described above.

Figures 20 and 21 show the fabrication stages of a device according to the present invention made insilicon. A silicon base layer (for example a silicon wafer) is formed as layer 201. Next, a thermal oxide Of Si02 203 is formed at the surface of silicon base layer 201.

On top of the thermal oxide, an amorphous layer of silicon is deposited on the oxide using UNV-CVD (chemical vapour disposition) for instance. Silicon quantum dots are formed on this layer by annealing the sample at 800'C under LTHV conditions. Alternatively, another semiconductor material, for example, germanium, can be used to form the quantum dot layer in a similar manner. After formation of the quantum dot layer 205, a further SiO2 layer 207 is deposited on the top of the quantum dots. A second quantum dot layer 209 is then formed on top of the Si02 layer and the layer is finished with a final Si02 layer 211.

The structure is then processed into a field effect structure as shown in Figure 21. First, a semi-transparent metal gate 213 is formed overlaying Si02 layer 211. The areas outside of the gates are etched to expose the Si base layer 201. N-type ohmic contacts 215 and 217 are then formed into the exposed Si region on either side of the gated

29 region. By biasing the gates, a 2DEG conduction channel is induced between contact 215 and 217.

Claims

CLAIMS:

1. A semiconductor device comprising first and second dot layers separated by a first barrier layer, each of the first and second dot layers comprising at least one quantum dot and there being at least one aligned quantum dot provided by a quantum dot in the first dot layer being aligned with a quantum dot in the second dot layer, the device further comprising means for separating an electron-hole pair in an aligned quantum dot and dipole detection means for detecting the presence of a dipole in at least one aligned double quantum dot.

2. A semiconductor device according to claim 1 wherein the means for separating an electron-hole pair comprises means for applying an electric field normal to the dot layers.

3. A semiconductor device according to either of claims 1 or 2, wherein in at least one quantum dot, the band-gap of the quantum dot in the first dot layer is different to that of the band-gap of the quantum dot in the second dot layer.

4. A semiconductor device according to any preceding claim, wherein at least one aligned double quantum dot, the band gap of the quantum dot in the first dot layer is greater than the band gap of the quantum dot in the second dot layer.

5. A semiconductor device according to any preceding claim, wherein the dipole detection means comprises an active layer capable of supporting a two dimensional carrier gas and means for measuring a variation in a characteristic of the active layer.

6. A semiconductor device according to claim 5, wherein the means for measuring a variation in a characteristic of the active layer comprises means for detecting a change in a transport characteristic of the active layer.

31 7. A semiconductor device according to claim 6, wherein the means for measuring the transport characteristic of the active layer comprises at least two ohmic contacts provided to the active layer.

8. A semiconductor device according to claim 5, wherein the means for measuring a variation in a characteristic of the active layer comprises means for detecting a change in an optical characteristic of the layer.

9. A semiconductor device according to any of claims 5 to 8, wherein the means for measuring a characteristic of the active layer comprises means for differentiating an output from the active layer with respect to time or means for detecting a change in a characteristic of the active layer with time.

10. A semiconductor device according to claim 9, wherein the means for measuring a characteristic of the active layer comprises means for counting pulses from the differentiated output from the active layer.

11. A semiconductor device according to any of claims 5 to 10, further comprising a second barrier layer, provided between the active layer and the closest of the first and second dot layers to the active layer.

12. A semiconductor device according to any preceding claim, wherein excess carriers are provided to the active layer.

13. A semiconductor device according to claim 12, wherein the carriers are provided to the active layer by means of a doped fourth barrier layer.

14. A semiconductor device according to claim 13, wherein the fourth barrier layer is a modulation doped barrier layer comprises a doped layer and a spacer layer, the spacer layer being provided adjacent the active layer.

32 15. A semiconductor device according to any of claims 12 to 14, wherein the excess carriers are electrons.

16. A semiconductor device according to any preceding claim, wherein the device further comprises a third barrier layer provided on an opposing side of the first dot layer to the second dot layer.

17. A semiconductor device according to claim 16, wherein the third barrier layer is a doped barrier layer.

18. A semiconductor device according to claim 17, wherein the third barrier layer is AlAs or A1GaAs.

19. A semiconductor device according to either of claims 17 or 18, wherein the barrier is n-doped.

20. A semiconductor device according to any preceding claim, wherein the means for applying afield normal to the first and second dot layers comprises a front gate provided overlying the first dot layer.

21. A semiconductor device according to claim 20, wherein the front-gate is semitransparent to radiation of a predetermined frequency.

22. A semiconductor device according to any preceding claim, wherein the means for applying a field normal to the first and second dot layers further comprises a backgate.

23. A semiconductor device according to any of claims 1 to 19, wherein the means for applying a field normal to the first and second dot layers comprises a p-type terminal on one side of the dot layers and an n-type terminal located on the opposite side of the first and second dot layers.

33 24. A serniconductorkdevice according to any preceding claim, wherein at least one of the dot layers comprises quantum dots with a distribution of optical transition energies.

25. A semiconductor device according to any preceding claim, wherein the first and second dot layers are formed by depositing InAs or InGaAs.

26. A semiconductor device according to any preceding claim, wherein the first barrier layers is AlAs, AlGaAs or GaAs.

27. A semiconductor device according to any preceding claim, wherein a beam of radiation is incident on a surface of the device.

28. A semiconductor device according to any preceding claim, wherein a beam of radiation is incident on the device parallel to the plane of the layers.

29. A semiconductor device according to any preceding claim, wherein the device further comprises upper and lower cladding layers.

30. A semiconductor device according to any preceding claim, wherein the device further comprises guide means for confining light in a predetermined region of the active layer.

31. A semiconductor device according to any preceding claim, wherein the first and second dot layers are formed from different materials.

32. A semiconductor device according to claim 3 1, wherein the first dot layer forms a type I heterojunction with its barrier materials and the second dot forms a type II heterojunction with its barrier material.

34 33. A semiconductor device according to any preceding claim wherein the strain environment in the first dot layer is different to the strain environment of the second dot layer.

34. A semiconductor device according to claim 3 1, wherein the first dot layer has a different alloy composition to the second dot layer.

35. A semiconductor device according to any preceding claim, wherein a growth smoothing layer is formed adjacent to any dot layer.

36. A semiconductor device according to any preceding claim comprising at least three dot layers.

37. A semiconductor device according to any preceding claim comprising a plurality of first and second dot layers separated by a first barrier layer and a plurality of dipole detection means for detecting the presence of aligned dipoles in each of the plurality of first and second layers.

38, A memory device comprising a plurality of pixels and each of said pixels comprises a semiconductor device according to any of claims I to 37.

39. A memory device according to claim 38, wherein each pixel is addressable by providing a voltage along a word-line and/or a bit-line.

40. A memory device according to claim 39, wherein the voltage along the wordlines and the bit-lines are being configured to be part of the means for separating an electron hole pair in an aligned quantum dot.

41. A memory device according to claim 40, wherein at least one semiconductor device in a pixel comprises a plurality of aligned double quantum dots, wherein at least one aligned quantum dot has a different excitation energy than that of the other aligned quantum dots in the device.

42. A memory device comprising a grid of bit-lines and word-lines addressing a plurality of pixels, each pixel being addressable by applying appropriate potentials to the bit-line and/or the word-line, at least one pixel comprising a device having a plurality of optical storage means, wherein at least one optical storage means is capable of storing data due to an optical activation at a different wavelength than that of at least one other optical storage means.

43. A method of operating the semiconductor device according to any of claims I to 37, the method comprising the steps of. applying a field across the dot layer sufficient to allow carriers of a predetermined plurality to tunnel out of the first dot layer to the second dot layer under illumination; selectively illuminating one or more of the plurality of quantum dots with a beam of radiation to excite at least one electronhole pair such that at least one carrier can tunnel out of the first dot layer to the second dot layer.

44. A method according to claim 43, further comprising the step of changing the electric field across the device between a field which is configured to allow a carrier to tunnel from the first dot layer to the second dot layer and a field configured to allow a carrier to tunnel from the first dot layer such that the carrier does not become trapped in the second dot layer.

45. A method of operating the memory device of claims 38 to 42, the method comprising the steps of: setting the word-line and/or the bit line voltage to switch a pixel into a read mode or a write mode; illuminating a plurality of pixels including the pixel which is in the read mode or the write mode.

36 46. A method of operating the memory device of claims 38 to 42, the method comprising the steps of. setting the word and/or bit line voltage to switch a pixel into a read mode or a write mode; scanning a read/write beam across the device to the position of the pixel which is in the read mode or write mode, and illuminating the said pixel.

47. A method according to claim 46, wherein the step of scanning the read/write beam is performed by moving the beam via moving mirrors.

48. A semiconductor device as substantially hereinbefore described with reference to any of the accompanying figures.

49. A memory device as substantially hereinbefore described with reference to any of the accompany figures.

50. A method of operating a semiconductor device as substantially hereinbefore described with reference of any of the accompanying figures.