GB2351622A

GB2351622A - Programmable fuse ID circuit with static current paths which may be disabled

Info

Publication number: GB2351622A
Application number: GB0022585A
Authority: GB
Inventors: Michael J Bennett; Robert W Proulx
Original assignee: Hewlett Packard Co
Current assignee: HP Inc
Priority date: 1996-07-18
Filing date: 1997-06-19
Publication date: 2001-01-03
Anticipated expiration: 2017-06-19
Also published as: GB2351622B; GB0022585D0

Abstract

A plurality of programmable fuse circuits 20 is provided with a disabling static current path configured on an integrated circuit to correspond to a serial number. Each one of the programmable fuse circuits 20 includes a controllable switch 26, a load device 24 and at least one fuse 22, all of which are connected in series between a source VDD and ground GND so as to share a static current path. The controllable switch 26 is preferably a transistor and can be selectively controlled to enable or disable the current path of the programmable fuse circuit 20. When the controllable switches 26 are conductive, the logical state of the programmable fuse circuits can be read such that the serial number can be determined. When the controllable switches 26 are non-conductive, the programmable fuse circuits 20 are disabled to save power.

Description

2351622 SYSTEM AND METHOD FOR DISABUNG STATIC CURRENT PATHS IN FUSE LOGIC

1NEID OF TEE RDN The present invention. generally relates to programmable fuse circuits in an integrated circuit, and more particularly, to a programmable fuse circuit having a controllable switch for disabling a static current path through the fuse circuit.

BACKQROIM OF THE ENVENTION An integrated circuit is a microelectronic semiconductor device consisting of many interconnected transistors and other components. A single integrated circuit may comprise as few as one to two components, ref&red to as small-scaled integration (SSI), to as many as a thousand or more components, referred to as very large-scaled integration tVT-;SI). Integrated circuits are typically fabricated on a wafer formed out of a suitable material such as silicon. On a single wafer, there may be to 100 integrated circuits. Once fabricated, the wafer is cut into small rectangular dies comprising the individual integrated cifcuits. Each die is then packaged in a manner to protect the integrated circuit thereon.

For a variety of reasons, a certain percentage of the integrated circuits manufactured on a wafer will have manufacturing defects rendering the integrated circuits useless unless the circuits can be repaired. Such manufacturing defects may be attributed to material imperfections, technician error, oreven the presence of a foreign object such as dust or dirt. Regardless of the cause of the defect, it is imperative that the defect be detected as early as possible in the final assembly process in order to preserve quality standards and to prevent any cost associated with the further processing of a defective product. Consequently, several tests are usually performed on an integrated circuit prior to the cutting of the wafer so that defective 0.

1 integrated circuits can be identified and repaired, if possible, before final assembly.

An important aspect of the testing performed on integrated circuits is that certain defects in the circuit are repairable if found prior to the packaging of the integrated circuit. For example, memory banks are typicaJly designed to include redundant memory elements that may be mapped into and out of the circuit in order to replace defective memory elements. The defective memory elements are likewise mapped out of the memory bank so as to be rendered nonconsequential. The mapping in and mapping out of memory elements is typically done with a plurality of programmable fuse circuits that are configured to provide a control logic signal to a fuse logic circuit connected to the memory bank so as to program the operation of the memory bank by mapping in and mapping out elements. With reference to Fig.

1, a conventional programmable fuse circuit 12 utilized in rogramnung memory is illustrated. In the fuse circuit 12, a fuse 14 is connected in series between ground (GND) and a load device 16. The load devioe 16 is also connected in series with a voltage supply (VDD). The -resulting voltage divider is used to produce a logic output level that is dependent upon the state of the fuse. For instance, if the fuse is blown, the logical output level is high. Alternatively, if the fuse is not blown, the logical output level is low. Therefore, the programmable fuse circuit can be used to permanently program the operation of the memory bank.

One t3W of testing performd on integrated circuits during fabrication is functional logic testing. In functional logic testing, a stimulus in the form of a test pattern is applied to the input of an integrated circuit. The output of the integrated circuit is then observed and compared to a desired response pattem which would be expected if the integrated circuit is functioning property. Preferably, numerous patterns areengineered and applied to the integrated circuit in order to thoroughly test the oper-ation of the integrated circuit. Similarly, functional logic testing can be used to perform timing test by toggling the input signal to an integrated circuit in order to determine whether the integrated circuit meets the performance requirements for setup k ' j times, hold times, and propagation delays.

While functional logic testing is suitable for testing most integrated circuits, it is recognized that with complicated integrated circuits, particularly sub-circuits thereof, it may be difficult. to stimulate the circuit with an input pattern and/or difficult to observe a response pattern which finds the fault. The sub- circuits may also be so deeply buried in multiple layers of surrounding circuitry that it is virtually impossible to physically access, much less apply the test pattern and/or observe an appropriate response pattern. Moreover, complicated integrated circuits such as application specific integrated4circuits (ASIC's) are non-regular, and therefore, it is often Impractical to engineer the large number of test patterns required to adequately test the ASIC in order to find all the.combinations of faults and defects possible.

Another type of testing performed on integrated circuits is static current testing. In static current testing, the current drawn by an integrated circuit under test is measured when in the ciFcuit is in a quiescent state. If a defect exists in the integrated circuit, a higher than normal static current (also referred to as quiescent current) flow is detected due to current paths -caused by the defect. An advantage of this testing technique is that the current is observed through the power and ground corintx1ions of the integrated circuit which are accessible and easy to observe. In addition, this technique does not rely on the functional output of the integrated circuit or any sub-circuit thereof. Presently, static current testing is limited primarily to testing complimentary metal-oxide semiconductor (CMOS) circuits. This is because CMOS circuitry produces -essentially no current while in a quiescent state. 17heref6re, if a cumnt above a predetermined threshold is detected when the circuit is in a quiescent state, then a defect exists within the circuit.

However, a disadvantage of static current testing is that many types of integrated circuits are not characterized by having essentially nocurrent flow while in a quiescent state as is the case with CMOS circuits. For example, the programmable fusecircuit 12 (Fig. 1) has a cont inuous static (i.e., quiescent) current 1 k path unless the fuse 14 is blown. Consequently, any integrated circuit incorporating the programmable fuse circuit 12 is not static current testable. This is a significant disadvantage since programmable fuse circuits like the one illustrated in Fig. 1 are commonly used in conjunction with fuse logic circuitry for permanently programming the operations of memory banks comprising random access memory (R, erasable programmable read only memory (EPROW, flash EPROM and numerous other suitable memory configurations, as discussed above.

In addition to the aforementioned needs in the industry, it has recently become desirable to have a unique machine readable serial number applied to integrated circuits for identification purposes. By providing a unique serial number on an integrated circuit, a variety of functions can be served. For instance, a data base of information regarding the origination, sale, specifications, etc. of an integrated circuit can be maintained. A plurality of programmable fuse circuits such as the one illustrated in Fig. 1 have been used to provide a binary serial number created by selectively blowing the fuses of respective fuse circuits. However, this method is undesirable because the programmable fuse circuits used for the serial number would be a constant power drain which is a critical design concern in most integrated circuit applications.

Ibus, a heretofore need existed in the industry for a programmable fuse circuit with a static current path that can be selectively disabled.

SUMMARY OF THE UqNT21MON

The present invention overcomes the inadequacies and the deficiencies of the prior art as disclosed herein and as well known in the industry. The present invention provides for a programmable fuse circuit having a disabling static current path. The programmable fuse-circuit can beemployed in an integrated circuit to serve a variety of functional purposes such as allowing static current testing of a rnemory bank that employs programmable fuse circuits for programming fuse logic circuitry to map in c 1 or map out memory elements.

Briefly stated, the programmable fuse circuit of present invention provides for a controllable switch that can be selectively actuated to enable or disable a static current (i.e., quiescent current) path through the circuit. The controllable switch is preferably a transistor configured to receive an input signal that is either a logic high or logic low. Based upon the state of the input signal, the transistor will either enable or disable thecurmnt flow through the transistor, and thus, the current flow through the fuse logic circuit.

Accordingly, an integrated circuit that was previously not testable with static cur-rent techniques because of the static current of the programmable fuse circuits can now be tested with static current techniques by incorporating programmable fuse circuits in accordance with the principles of the present invention. By disabling the cumnt path in the programmable fuse circuit via the controllable switch, the amount of static current in the integrated circuit can be observed in order to determine if a is Ofect is present. This is particularly advantageous because the integrated circuits which were previously not staticcurrent testable may be static current tested, thereby providing more thorough testing of the integrated circuit. Further, certain defects can be com if identified such as done with mapping memory banks in order to replace defective memory elements with redundant memory elements as described hercinbefore." Therefore, the present invention not only increases quality but reduces production costs by minimizing the number of defective products that must be discarded.

Another function of a programmable fuse circuit in accordance with the principles of the present invention is in marking integrated circuits with serial numbers for identification purposes without having to continually power., the programmable fuse circuits. As an example, the output of a plurality of programmable fuse circuits placed on an integrated circuit can be programmed to provide a unique binary serial number by selectively blowing the fuses. In this 1 1 configuration, the present invention provides the advantage of having the controllable switches disabled until the serial number of the integrated circuits is to be read so that the programmable fuse circuits do not consume any power. When the serial number is to be read, the controllable switches are enabled so that current flows in the respective programmable fusecircuits that do not have a blown fuse, and the serial number can be read. Then the controllable switches can subsequently be disabled until it is once again desirable to read the serial number of the integrated circuit.

This is particularly useful in the design of integrated circuits where power consumption is a critical design feature.

In a first -embodiment, the programmable fuse circuit comprises a load device and a fuse -device connected in series. The load device is further connected to a power supply (VDD) and the fuse device is hirther connected in series to a controllable switch that is connected to ground. In this embodiment, the controllable switch is an n-channel metal oxide semiconductor field effect transistor (NMOS FEM configured as a pull-down device. The use of an NMOS FEr is preferred in P-doped silicon substrate fabrication processes due to its increased charge mobility. The output Of the programmable fuse circuit is taken at the connection between the load device and the fuse. Ibus, when the fuse is blown or the NMOS FU disabled, the output is a logic high level. Otherwise, the output is a logic level low.

In an alternative configuration of the first embodiment, multiple fuses can be connected in series between the load device and the NMOS F9BT in order to Provide for multiple outputs, as is often desired. In this alternative configuration, the outputs are typically taken at each connection between the adjacent ftises and the connection between the load device and the adjacent fuse. Typically, only one fuse may be blown in this series fuse circuit. As with the previous configuration, the logic level of the respective outputs depends upon the state of the fuses. Particularly, any fuse on the ground 04D)'side of a blown fuse win have a low logic level output, while any fuses on the voltage supply (VDD) side of a blown fuse will have a high logic level output.

In a second,embodiment, a programmable fuse circuit of the present invention comprises a load device and a fuse device connected in series as with the previous embodiment. However, with this embodiment, the load device is further connected in series to ground (GND) and the fuse device connected in series to a controllable switch that is connected to a power supply (VDD). In this embodiment, the controllable switch is a p-channel metal oxide semiconductor field effect transistor

PMOS FET) corifigured as a pull-up device. The PMOS FET is preferred in N doped silicon substrate fabrication process or in a circuit that desires its output to be at a nomally high logic level unless programmed. The output of the programmable fuse circuit is taken at a connection between the load device and the fuse. Opposite of the flust embodiment, the output of the fuse logic circuit is a logic high unless the fuse is blown or the PMOS FEr is disabled.

As with the -Fust -embodiment, the second embodiment can also be configured with multiple fuses in an alternative configuration whereby the fuses are connected in a series between the PMOS FEr and the load device in order to provide multiple outputs. In this configuration, the outputs are talmn at any of the connections between the adjacent fuses and the connection between the load device and the adjacent fuse.

An advantage of a programmable fuse circuit in accordance with the present invention is that it provides a programmable fuse circuit that is static current testable.

Specifically, such a programmable fuse circuit would not prevent an integrated circuit from being testable with static current techniques. This allows for.more thorough testing of the integrated circuits that incorporate programmable fusecircuits.

Another advantage of a programmable fuse circuit in aocordance with the present invention is that it provides a programmable fuse circuit that does not consume any power when the output of the circuit is not needed.

Another advantage of a programmable fuse circuit in accordance with the 1 1 present invention is that it provides a programmable fuse circuit that is simple to implement and efficient in operation.

Other features and advantages of the present invention will become apparent to one with ordinary skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as defined by the appended claims.

BRIEF DES N OF THE DRAMWGS The present invention can be better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention.

Furthermore, like reference numerals designate corresponding parts throughout the several views.

fig. I is a schematic circuit diagram of a prior art programmable fuse circuit;

Fig. 2 is a schematic circuit diagram of a fuu embodiment of a programmable fuse circuit with a single output in accordance with the present invention; Fig. 3 is a schematic circuit diagram of an alternative configuration of the first embodiment with multiple outputs; Fig. 4 is a schematic circuit diagram of a second embodiment of a programmable fuse circuit with a single, output in accordance with the present invention; and Fig. 5 is a schematic circuit diagram of an alternative configuration of the second embodiment with multiple outputs.

DETAILED DESCRIPTION OF THE PREFERRED EMEBOD

The following description is of the best contemplative mode of carrying out the present invention. The description is not to be taken in a limiting sense but is

1 made merely for the purpose of describing the general principles of the invention.

Therefore, the scope of the invention should be determined by referencing the appended claims.

1. Circuit Design Referring now to the drawings, Fig. 2 illustrates a first embodiment of a programmable fuse circuit 20 in accordance with the present invention. The programmable fuse circuit 20 includes a fuse device 22 and a load device 24 connected in series. The load device 24 is further connected in series to a power supply (VDD), and the fuse device 22 is further connected in series to a - controllable switch 26 which is further connected to ground (GND). A control line 28 connected to the controllable switch 26 provides a control signal for enabling and disabling the controllable switch 26. The output of the programmable fuse circuit 20 is taken at an output line 30.

In this embodiment, the fuse device 22 preferably comprises a metal layer Which is either conductive or not, depending on whether it has been blown.

Alternatively, a polysilicon or silicide layer can also be used instead of a metal layer.

The load device can be implemented by any resistive device, but is preferably implemented as either- an - N-doped WELL resistor or a p-channel metal- oxide semiconductor field e ff-ect transistor (PMOS FET). The controllable switch 26 is preferably an n-channel metal-oxide semiconductor field effect transistor (NMOS

FEI) configured as a pull-down device. However, it should be noted at this point that the controllable switch 26 can be implemented by any number of suitable devices configured as a controllable switch such as NPN and PNP bipolar junction transistors (BJT) devices, or junction -field effect transistor (JFEI) devices.

In the fust embodiment, the particular configuration of an NMOS FET as a pull-down device for controllable switch 26 would be apparent to one of ordinary skill in the art. However, in general, the NMOS FET should preferably beconfigured such that its drain is connected to the fuse, its source is connected to ground (GND), 1 and its gate connected to the control line 28. Therefore, if a control signal on the control line 28 is set to a logic high, then the controllable switch 26 is conductive.

Conversely, if the control signal on control line 28 is set to a logic low, then the controllable switch 26 is nonconductive and the static current path through the programmable fuse circuit 20 is disabled. It should also be noted that if fuse device 22 is blown, the static current. path of the programmable fuse circuit 20 is likewise disabled, regardless of the state of controllable switch 26.

With reference to Fig. 3, an alternative configuration of the fint embodiment is illustrated and denoted by reference numeral 32. The programmable fuse circuit 32 is configured substantially the same as that of the programmable fuse circuit 20 except that programmable fuse circuit 32 provides multiple outputs A, B, and C via respective output lines 34, 36, and 38. Corfesponding with each of the output lines 34, 36, and 38 is a respective fuse 40, 42, and 44, wherein said fuses are connected in series. As shown in Fig. 3, a load device 4-6 is connected in series between the fime 40 and voltage supply (VDD). In addition, a puU-down device 48 is connected in series between the fuse 44 and ground GND). As with the first embodiment, the controllable switch 48 is preferably a NMOS M configured as a pull-down device.

Accordingly, the NMOS FEr is configured such that its drain is connected to fuse 44, its source is connected to ground (,GND), and its gate is connected to a control line 50, as would be apparent to one of ordinary skill in the art.

Thus, when a control signal on the control line 50 is a logic high, the controllable switch 48 is conductive. Altematively, when the control signal on the control line 50 is a logic low, the controllable switch 48 is nonconductive, thereby disabling the static current path through the programmable fuse circuit 32. It is further noted that the outputs taken at respective output lines 34, 36, and 38, are dependent upon the state of fuses 40, 42, and 44, respectively, as described hereinbefore with regard to the programmable fuse circuit 20 (Fig. 2). Further, only one fuse device from the plurality of fuse devices 40, 42, and 44 will be blown in this 1 case.

In a second em bodiment, as illustrated in Fig. 4, a programmable fuse circuit comprises a load device 62 and fuse device 64 connected in series. The loaded device is further connected in series to ground (GND) and the fuse device 64 is further connected to a controllable switch 66 which is connected to a voltage supply (VDD). In this embodiment, the controllable switch 66 is a P-channel MOS FET (PMOS FEI) configured as a pull-up device. However, it should be noted that the controllable switch,66 can be implemented by any number of other suitable devices such as NPN and PNP BJT devices, or = devices. Associated with the controllable switch 66 is a control line 68 for controlling the operation of the -controllable switch 66 as described hereinbefore. The output of programmable fuse circuit 60 is taken on an output line 70 at the connection between the fuse device 64 and the load device 62.

Though the particular configuration of the PMOS FET for the controllable switch 66 is not illustrated in Fig. 4, the connections of the PMOS M would generally include connecting the source of the PMOS FET to the power supply (VDD), the gate of the PMOS FET to the control line 68, and the drain of the PMOS FET to the fuse device 64. Thus, when a control signal on the control line 68 is a logic IqW, the PMOS VET is conductive so that the static current path is not disabled at the control switch 66. Alternatively, if the control signal on thecontrol line 68 is a logic high, t1ten the PMOS FET is nonconductive, disabling the static current path through the programmable fuse -circuit 60.

With reference to Fig. 5, an alternative configuration of the second embodiment is illustrated and denoted by reference numeral 72. The programmable fusecircuit 72 is configured much like programmable fuse circuit 60 though modified in order to provide multiple outputs A', B', and C' via the outp ut lines 74, 76, and 78, respectively. Associated with,each output line 74, 76, and 78 are respective fuses 80, 82, and 84 connected in series. Connected between fuse. 80 and the voltage 1. 1 supply (VDD) is a controllable switch 86 configured as a pull-up device and preferably implemented via a PMOS FET. Associated with a controllable switch 86 is a control line 88 for controlling the operation of the controllable switch 86, as described hereiribefore. In addition, a load device 90 is connected between fuse 84 and ground (GND).

In accordance with the operation of a programmable fuse circuit with multiple outputs, the logic state of each output A', E', and C' at respective output lines 74, 76, and 7-8 depends on the state of fuses 80, 82, and 84, respectively, in addition to the state of controllable switch 86. As with the multiple output configuration of the first embodiment as illustrated in Fig. 3, only one fuse device from the plurality of fuse devices 80, 82, '84 will be blown in this case.

With particular reference to the operation of the controllable switch 86, when a control signal on the -control line 88 is a logic low, the PMOS = is conductive so that the static current path is not disabled at the control switch 86. Alternatively, if the control signal on the control line 88 is a logic high, then the PMOS FET is nonconductive, disabling the static current path through the programmable fuse circuit 72.

11. Circuit KhMofign For purposes of brevity, the preferred operation and sequenoe of events corresponding with a programmable fuse circuit in accordance with the present invention and the associated methodology are described hereafter with reference to the programmable fuse circuit 20 (Fig. 2). It would be obvious to one of ordinary skill in the art how the programmable fuse circuits 32, 60, and 72 operate based upon the following discussion and the present disclosure taken as a whole.

With oference to Fig. 2, the operation of the programmable fuse circuit 20 is -first discussed in the context of mapping memory elements out of and into a memory bank via fuse logic circuity. By programming the fuse logic circuity with the outputs from a plurality of programmable fusecircuits 20, the memory bank is 1 1 static current testable because the static current paths through the programmable fuse circuits 20 can be disabled via the controllable switch 26. As mentioned above, this is desirable in order to achieve more thorough testing of the integrated circuit.

In order to perform static current testing, the signal on the control line 28 for each respective programmable fuse circuit 20 is set to a logic low. Preferably, the control lines 28 of the programmable fuse circuits 20 are connected to one another.

This disables the static current path of each programmable fuse circuit. 20 by rendering the controllable switch 26 nonconductive. Accordingly, static current tesUng can be performed since substantially no static current can flow when the circuit is in a quiescent state other than that resulting from a defect.

Next, the operation of the programmable fuse circuit 20 is discussed in the context of providing a serial number on an integrated circuit for identifying the integrated circuit. SpecificaUy, this is achieved by providing multiple programmable -fuse circuits 20 on an integrated circuit (Le., a chip) and programming these programmable 'fuse circuits with a unique binary serial number identifying that integrated -circuit. A particular advantage of using the programmable fuse circuits ZO to provide a serial number is that the static current path of the programmable fuse circuits 20 can be disabled by the controllable switch 26 so that no power is consumed when the serial number is not needed. However, when it is desirable to read the serial number, the controllable switch can be enabled so as to be conductive, and thereby allow the serial number to be read.

The functionality described above with regard to the serial number is achieved by configuring a plurality of the programmable fuse circuits 20 so that their respective - controRable switches 26 can be actuated substantially simultaneously and their respective outputs read in a manner to form a serial number that uniquely identifies that integrated circuit. In operation, a logic level low signal is placed on the -control line 28 of each programmable fuse circuit 20 so that the static.current path of each circuit 20 -remains disabled and no direct current, (DC) flows in the respective 4 .1 progrummable fuse circuits 20. However, when the serial number is to be read, a logic high signal is placed on each control line 28 so as to enable the current path of each programmable fuse circuit 20 whose fuse 22 has not been blown. Accordingly, those fuse logic circuits whichIave not had their fuse blown will read a logic low at their output. Those prognmmable fuse circuits 20 which have had their fuse 22 blown will read a logic high at their output. Thus, the combination of the logic low and logic high outputs ffom the tive programmable fuse circuits 20 provides a unique binary serial number for identifying the integrated circuit.

In concluding the detailed d"cription, it should be noted that it will be obvious to those skilled in the art that many variations and modifications may be made to the pref embodiment without substantially departing fromthe principles of the invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.

Further, in the claims hereafter, the structures, materials, acts, and equivalents of all is means or step plus function elements are intended to include any structures, materials, or acts for perforTning the recited functions in combination with the other claimed elements as specifically claimed.

Claims

CLAIMS:

1. A method for identifying a device having a plurality of programmable fuse circuits that are disposed between voltage supply and ground and include a load device operating as a voltage divider and a fuse device that can be blown in order to-control a logic output level of said programmable fuse circuit, said methodcomprising the steps of controlling a switch device connected in series with said programmable fusecircuit, -said switch device being configured for selectively enabling and disabling a static current path through said switch device in order to prevent static current flow in said programmable fuse circuit; and blowing said fuse device in a particular number of said plurality of programmable fuse circuits in order to identify said device.

2. A method as clai m-ed in claim 1, further comprising the step of enabling said plurality of programmable fuse circuits only during particular time intervals.

3. A system residing on an integrated circuit for identifying an object, said system comprising:

a plurality of programmable fuse circuits configured to correspond to a binary serial number, each one of said programmable fuse circuits further comprising:

a fuse device; a load device coupled to said fuse device; a controllable switch coupled to said fuse device, said load device, said fuse device and said controllable switch forming a series circuit disposed between a power supply and a ground, such that, when said controllable switch is in a first state, said programmable fuse circuit is conductive, and such that, when said controllable switch is in a second state, said programmable fuse circuit is non-conductive, such that when said fuse device is in a conductive state and when said programmable fuse circuit is conductive, then said programmable fuse circuit is in a first logical state, and when said fuse device is in a blown state and when said programmable fuse circuit is conductive, then said programmable fuse circuit is in a second logical state.

4. A system asclaimed in claim 3, wherein, when said controllable switch is in said second state, said plurality of programmable fuse circuits do not consume power.

5. A system as claimed in claim 3 or claim 4, where at least one of said plurality of programmable fuse circuits further comprises a second fuse device coupled to said fuse devise and a third fuse device coupled to said second fuse device, such that said at least one programmable fuse circuit has a first output, a second output and a third output.

6. A method for identifying an object by a serial number, the method comprising the steps of disposing on an integrated circuit a plurality of programmable fuse circuits configured to represent a binary serial number, each one of said plurality of programmable fuse circuits having at least a series circuit comprising a fuse device, a load device and a controllable switch; and selectively blowing said fuse, devices such that, when said fuse device is blown, then said programmable fuse circuit represents a first logical state and, when said fuse device is not blown, then said programmable fuse circuit represents a second logical state.

7. A method as claimed in claim 6, further comprising the step of controlling said controllable switch such that, when said controllable switch is in a first state, said programmable fuse circuit is conductive, and such that, when said controllable switch is in a second state, said programmable fuse device is nonconductive and said programmable fuse circuit does not consume power. '

8. A method as claimed in claim 7, further comprising the step of reading a logical output on each one of said plurality of programmable fuse circuits when each one of said controllable switches is in said first state and each one of said programmable fuse circuits in conductive, wherein said logical output corresponds to said first logical state or said second logical state.

9. A method as claimed in claim 8, further comprising the step of reading a plurality of logical outputs on each one of said plurality of programmable fuse circuits.