GB2344682A

GB2344682A - Matrix type display with time division gradation

Info

Publication number: GB2344682A
Application number: GB9929022A
Authority: GB
Inventors: Takaji Numao; Shigetsugu Okamoto
Original assignee: UK Secretary of State for Defence; Sharp Corp
Current assignee: UK Secretary of State for Defence; Sharp Corp
Priority date: 1998-12-11
Filing date: 1999-12-09
Publication date: 2000-06-14
Anticipated expiration: 2019-12-09
Also published as: JP2000181395A; GB2344682B; GB9929022D0

Abstract

A display comprising a matrix of pixels has a control section providing grey scale display by controlling the number of times pixels are lit during a predetermined period. To avoid the 'dynamic false contour effect', the predetermined period is divided into two sub-periods and the combination of pixels which are lit in the first and second sub-periods are differentiated, with the same display information being used for both periods. The display may be a plasma display or a ferroelectric liquid crystal display.

Description

MATRIX-TYPE DISPLAY The present invention relates to a matrix-type display, such as a plasma display and a ferroelectric liquid crystal display, capable of carrying out time-division gradation display, and more particularly concerns a method for improving the display quality of such a matrix-type display.

Conventionally, ferroelectric liquid crystal displays (hereinafter, referred to as FLCD) have been expected to serve as simple-matrix displays capable of achieving a large screen display with a large display capacity.

In FLCDs, for example, displays with a large display capacity have been achieved by using, for example, a method published in"HIGH RESOLUTION, LARGE AREA FLC DISPLAY WITH GRAPHIC PERFORMANCE"by Canon in Ferroelectrics, 1991, Vol.

114, pp. 3-26. Specifically, in this method, pixels on the common electrodes, which include pixels at which the display state has changed due to mouse pointer MP, display window W, etc. within a screen in Fig. 22, are re-written by partial re-write scanning at a partial access area Ap, and at a refresh area Ar other than this area, the pixels on the common electrodes are refreshed by interlace scanning (rewrite the same display state as before).

Interlace scanning methods of this type have been disclosed in, for example, Japanese Laid-Open Patent Application No. 298286/1988 (Tokukaishou 63-298286, December 6,1988) and Japanese Laid-Open Patent Application No.

126224/1990 (Tokukaihei 2-126224, published on May 15, 1990). In the interlace scanning method disclosed in JP No.

298286/1988, among interlace signals received (or to be displayed), in the first field, data is written in only the pixel on the KN + A numbered common electrode (where K is an integer not less than 2, N is an arbitrary positive integer and A is an integer in the range of 0 5 A s K-1), and in the second field, data is written in only the pixel on the KN + B numbered common electrode (where B is an integer satisfying 0 s B s K-1 and A X B) ; that is, a so-called interlace scanning method of K: 1 is carried out (hereinafter, referred to as 63-298286 type interlace method).

The reason that this 63-298286 type interlace method is available is because the ferroelectric liquid crystal (hereinafter, referred to as FLC) has a memory property so that it is not necessary to replace all the pixels with a frequency such as 60Hz. that makes flickers less conspicuous. However, this memory property also results in the fact that only binary display is available in the FLCD.

In general, it is more difficult to construct a device having not less than three memory states than to construct a device having only two memory states. Therefore, with respect to devices having memory states, the number of the memory states is inherently limited to two.

Here, in the recent trend of displays, multiple gradation display has become an essential feature. In the field of FLCDs, the idea for introducing pixel-division gradation display has been disclosed in, for example, Japanese Laid-Open Patent Application No. 229430/1988 (Tokukaishou 63-229430, published September 26,1988), etc.

In this method, gradations are obtained by dividing one pixel into a plurality of partial pixels having different areas.

More specifically, as illustrated in Fig. 23, in a liquid crystal panel 101 provided with a plurality of common electrodes L and a plurality of segment electrodes S' intersecting these, pixels are formed at intersections between the common electrodes L and the segment electrodes S'. Moreover, since the segment electrode S'consists of three sub-data electrodes S1 to S3, the pixel is constituted by three sub-pixels (partial pixels) having different areas (for example, area ratios of 1: 2: 4). In such an arrangement, while the common electrodes L are being scanned by a scanning electrode driving circuit 102, appropriate display data is applied to the sub-data electrodes Si to S3 by a data electrode driving circuit 103; thus, it is possible to achieve gradation display in accordance with the area ratios of the sub-pixels.

Moreover, an idea for introducing time-division gradation display has been disclosed by Japanese Laid-Open Patent Application No. 69039/1986 (Tokukaishou 61-69039, published April 9,1986). As illustrated in Fig. 24, this method obtains gradations by dividing one frame period into a plurality of sub-frame (field) periods having time width ratios of, for example, 1: 2: 4.

Moreover, a method in which the above-mentioned two gradation display methods are combined has been proposed, in which, for example, one pixel is divided into two partial pixels having an area ratio of 1: 2 and one frame period is divided into a sub-frame periods having a time-width ratio of 1: 4; thus, gradation display is obtained.

As described above, it has become possible to realize multiple gradation display also in the FLCD; however, when the time division gradation display is used in the FLCD, the memory property for maintaining the same display state for several seconds, which is one advantage of the FLC, virtually is not utilized. In other words, since display has to be made within a period of (1/60) sec. in order to change the display state by scanning pixels a plurality of times, the 63-298286 type interlace method utilizing the memory property cannot be adopted. That is, in this method, the interlace scanning is carried out so as to eliminate the necessity of re-writing the states of all the pixels within one screen for a period of (1/60) sec. In contrast, the time-division gradation display is a method for scanning all the pixels within one screen a plurality of times within a period of (1/60) sec. Therefore, a problem arises in which the two methods conflicts with each other.

Here, interlace scanning methods which are carried out in TFT (Thin Film Transistor) liquid crystal displays using a nematic liquid crystal such as TN (Twisted-Nematic) have been disclosed by, for example, Japanese Laid-Open Patent Publication No. 305676/1989 (Tokukaihei 1-305676, published February 9,1989), Japanese Laid-Open Patent Publication No.

202597/1994 (Tokukaihei 6-202597, published July 22,1994), Japanese Laid-Open Patent Publication No. 336090/1996 (Tokukaihei 8-336090, December 17,1996), etc. In the interlace scanning used in these TFT liquid crystal displays, during the first field period, the same information derived from a received interlace signal is displayed on pixels controlled by the 2N numbered scanning line and 2N + 1 numbered scanning line (where N is an arbitrary positive integer), and during the succeeding second field, the same information is displayed on pixels controlled by the 2N-1 numbered scanning line and 2N numbered scanning line; thus, this scanning method lengthens the selection time per one scanning line (hereinafter, referred to as TFT type interlace method).

Different from the FLCD, multiple gradation display is easily carried out by these TFT liquid crystal displays; however, since the yield of the TFT decreases as the screen size becomes larger, the disadvantage of these displays is that they are difficult to be applied to large screens.

Here, in recent years, plasma display panels (hereinafter, referred as PDP) have received much attention as displays capable of achieving a large screen, a large display capacity and multiple gradations. In the PDP, a timedivision gradation display method, in which one field (or 1 frame) period is divided into a plurality of sub-field (or sub-frame) periods, and in which scanning is carried out in each period independently so as to provide gradation display by utilizing the accumulation effects, is mainly used as its driving method.

For example, in the PDP, as illustrated in Fig. 25, one field period is divided into 8 sub-field periods SF1 to SF8, each of the sub-field periods SF1 to SF8 is further divided into an address period and a display period, and the ratios of time widths for display periods corresponding to these sub-field periods SF1 to SF8 are set to 1: 2: 4 :... : 128 so that 256 gradations are achieved by independently turning ON/OFF the display of each sub-field period.

However, in such a time-division gradation display method, as shown in Fig. 26, in the case when, for example, a gradation level"127"is displayed, light-emitting periods of PDPs (where the light-emitting period is indicated by a portion with slanting lines) concentrate on the former half of one field period. Moreover, in contrast, in the case of a gradation level"128", light-emitting periods of PDPs concentrate on the latter half thereof.

Therefore, as illustrated in Fig. 27, in the case when an object 112 having a gradation level"128"in brightness is moving on a background 111 having a gradation level"127" in brightness, since the viewer's eyes follow the object 112, shifts from image 112a to image 112b are recognized as the object 112 by the viewer. Therefore, a phenomenon occurs in which the viewer recognizes the object 112 as if it were constituted by portions having gradation levels"0", "128", and"255"in brightness (the phenomenon being hereinafter referred to as"dynamic false contours").

The generation principle of such dynamic false contours has been explained by Mikoshiba et al in"Dynamic False Contours on PDPs-Fatal or Curable ?" in IDW'96.

In order to solve the problem of dynamic false contours, Japanese Laid-Open Patent Application No.

175439/1995 (Tokukaihei 7-175439, published July 14,1995), etc. have disclosed a method in which the sub-field period corresponding to the uppermost bit is divided into two.

This is a method for dividing a sub-field having a time width ratio of 128 in the conventional method shown in Fig.

25 into two sub-fields of 64: 64 (hereinafter, referred to as "upper-bit division method") as shown in Fig. 28.

Moreover, as described in the above-mentioned paper, there is another method in which a continuous 64 gradation period in Fig. 28 is re-divided into four 48 gradation periods, and re-arranged (hereinafter, referred to as "upper-bit re-arrangement method").

However, with respect to the PDP, taking account of the light-emitting efficiency, as well as the fact that at present, the minimum pixel pitch between pixels constituted by three colors of RGB is approximately 660 m, and that the panel is manufactured by using a printing method, it is impossible to further miniaturize the pixel pitch. For this reason, it is difficult to manufacture displays with higher precision (with a smaller pixel pitch) by using the PDP.

Therefore, the FLCD, which can miniaturize the pixel pitch since the printing method is not used in manufacturing panels (that is, at present, the pixel pitch of approximately 300 gm has been achieved), has a transmitting property, and is less susceptible to a reduction in the yield even in the case of a large screen since TFTs are not used, has been expected to provide displays having a large screen with a high display capacity. However, even when the FLCD is adopted, it is difficult to increase the number of pixel divisions since a structural limitation exists in the number of pixel divisions; therefore, it is inevitable to adopt the time-division gradation display in order to obtain multiple gradations.

Here, as a result of our review on the FLCD in which the time-division gradation display was carried out, it is confirmed that even the FLCD is susceptible to the occurrence of dynamic false contours. Conventionally, the problem of dynamic false contours is considered to be inherent to the PDP; however, the results of some experiments on the FLCD showed that this problem commonly occurs in displays that carry out the time-division gradation display.

For example, in the same manner as the PDP, in the case of the FLCD also, 8 gradation display is obtained by providing an arrangement in which: one field period is divided into three sub-field periods SF1 to SF3 as shown in Fig. 30, each of the sub-field period SF1 to SF3 is further divided into an erasing period and a display period, the ratios of time widths for display periods corresponding to these sub-field periods SF1 to SF3 are set to 1: 2: 4, and the display of each of the sub-field periods SF1 to SF3 is independently turned on/off. It has been confirmed that even in this gradation display, dynamic false contours occur in the same manner as the PDP.

Therefore, the applications of the upper-bit division method and the upper-bit re-arrangement method that are the currently proposed measures to eliminate dynamic false contours were examined; however, in order to divide the upper-bit, it is necessary to increase the number of scanning operations per one field period. For example, in the above-mentioned example, since one field period is divided into three sub-field periods, three scanning operations are carried out per one field period, and when the uppermost bit is divided into two, one field period is divided into four sub-field periods. Moreover, when the uppermost bit is divided into three, one field period is divided into five sub-field periods.

As described above, in order to address the problem of dynamic false contours, it is effective to increase the number of sub-fields per one field period. However, in order to increase the number of sub-fields, it is necessary to shorten one selection period (a period required to rewrite the stable state of the FLC constituting pixels on a common electrode) correspondingly. Here, in the FLCD, the minimum selection period is limited due to the material characteristics, etc. Moreover, in the case when a display which drives a capacitive load such as the FLC (that is, liquid crystal sandwiched between the opposing ITO electrodes is equivalent to a capacitor), even if the switching is made with a desired selection period, the shortening of the one selection period will raise the following serious problems.

As illustrated in Fig. 7, in the FLCD, common voltages (-Vb and Vs) are applied to the common electrodes, and segment voltages (Vd) are applied to the segment electrode, and a pixel voltage, which is the voltage difference, is applied to the FLC located between the common electrode and the segment electrode so as to determine the stable state of the FLC. In this case, the polarity inversion of the segment voltage inevitably occurs during one selection period; therefore, as one selection period is made shorter, the frequency (driving frequency) at which the voltage to be applied to the FLC is changed becomes higher, causing a greater waveform distortion at the end of the electrode.

Consequently, problems arise in which: the waveform distortion renders the FLCD inoperable in driving, and the high driving frequency causes an increase in the current flowing through the electrodes, resulting in generation of heat inside the panel.

The objective of the present invention is to provide a display which carries out time-division gradation display capable of reducing the occurrence of dynamic false contours (although not possible to eliminate them, it is possible to make them inconspicuous) without the need for increasing the number of sub-fields per one field.

The matrix-type display to which the present invention is applied has a construction in which: pixels arranged in a matrix format that consists of m number of them aligned in a first direction and n number of them aligned in a second direction (wherein both m and n are integers), and a display control means for providing gradation display by simultaneously controlling the display state of m number of pixels aligned in the first direction and allowing the same pixels to light on a plurality of times during a predetermined period.

In accordance with the present invention, the abovementioned matrix-type display is characterized in that the display control means differentiates the combination of pixels for determining the display state based upon the same display information during a first period of the predetermined period from the combination of pixels for determining the display state based upon the same display information during a second period succeeding the first period of the predetermined period.

In the above-mentioned arrangement, the display control means differentiates the combination of pixels that determines the display state between the first period and the second period; thus, for example, within one selection period, m number of pixels on different common electrodes adjacent in the second direction are allowed to have the same display state at the same time, and the combination of the common electrodes to be selected at the same time is changed between the first period and the succeeding second period so that the constitution of the pixels to be allowed to have the same display state at the same time is made different without the need for increasing a constant period, such as, for example, a frame period or a field period, that is required to control the display state of all the pixels.

More specifically, in the case when a pixel Aj, located on the KN + A numbered (where K is an integer not less than 2, N is an arbitrary positive integer, and A is an integer satisfying 0 s A s K-1) common electrode and the J numbered segment electrode, and an adjacent pixel Axi,,, A, 1, J located on the KN+A+1 numbered common electrode, which come to have the same display state during a certain field (or a frame) are positioned at a gradation transition point that is susceptible to the occurrence of dynamic false contours, the amounts of occurrence of dynamic false contours between the above-mentioned pixel Aj and the adjacent pixel AKN+A+ J are averaged or cancelled by subjecting them to a gradation transition so as to have different display states in the adjacent fields (or frames) so that it is possible to lower the peak value of the amount of occurrence of dynamic false contours.

With this arrangement in the present invention, it is possible to reduce the maximum peak of the amount of occurrence of dynamic false contours, and also to reduce the amount of occurrence thereof in some cases. Moreover, since this operation is carried out virtually without changing the width of one selection period, it is free from problems such as an increase in the amount of waveform distortion at the end of the electrode due to a shortened width of one selection period and an increase in heat generation within the panel. Therefore, this operation is particularly effective for display devices for driving a capacitive load such as FLCDs.

The present invention is particularly effective to improve image quality by reducing dynamic false contours in displays for providing time-division gradation display, such as, in particular, PDPs and FLCDs, and the effects thereof are clearly ensured.

The matrix-type display of the present invention comprises: n number of first electrodes that are aligned in a first direction and m number of second electrodes that are aligned in a second direction and display elements placed between the first and second electrodes, and the opposing sections of the two electrodes facing at each portion at which the first and second electrodes intersect each other and the portion of the display element sandwiched by these are allowed to constitute a pixel. In particular, a liquid crystal layer made of a ferroelectric liquid crystal is preferably used as this display element. Thus, it becomes possible to reduce the occurrence of dynamic false contours even in the case of a matrix-type liquid crystal display using a ferroelectric liquid crystal.

In the matrix-type display of the present invention which has m x n number of display pixels, even when the number of data pixels to be inputted to the display control means is close to m x n (slightly greater than m x n), the pixels can be thinned appropriately. However, taking account of degradation in the display quality due to the thinning of the data pixels, supposing that the number of data pixels assumed for the input signal is w x u (w, u are integers), the m x n number of display pixels are preferably set to satisfy the following relationship by using an integer K (K is an integer not less than 2): m w x K, n-u.

In the case when the number of display pixels is close to the number of data pixels to be inputted to the display control means, if such a number of display pixels is set upon thinning data pixels, the above-mentioned setting of the number of display pixels allows the present invention to exert its effects without causing degradation in the display quality.

In particular, it is more preferable to set K in the range of 2 to 4, so as to reduce the occurrence of line flickers, etc.

The display control means in the matrix-type display of the present invention is designed to have either of the following two constructions in accordance with the input signal.

In the first construction in which each image display position assumed for a signal inputted during the predetermined period (for example, frame period) is the same in all the frames, control is provided in such a manner that: during the first period (first frame period), based upon the P numbered pixel information assumed for the input signal, the K x P-q numbered to K x P + r numbered pixels (where q and r are integers satisfying q + r = K-1 and K is an integer not less than 2) that are adjacent in the second direction are allowed to have the same display state by controlling them at the same time; and during the second period (second frame period), based upon the P numbered to P + 1 numbered pixel information assumed for the input signal, interpolating information is formed by using, for example, an LPF (Low Pass Filter) and based upon this interpolating information, the K x P + B-q numbered to K x P + B + r numbered pixels (where B is an integer satisfying 1 s B s K-1) that are adjacent in the second direction are allowed to have the same display state by controlling them at the same time.

Here, this interpolating information is obtained more simply from the following expression: {P numbered pixel information x B + P+1 numbered pixel information x (K-B)}/K.

With the above-mentioned arrangement, the K x P numbered through K x P + K-1 numbered pixel information, assumed for the input signal, is displayed all through the K frames. Here, this construction is also applicable to the display control means of the aforementioned display using the ferroelectric liquid crystal or the display in which the pixels are thinned.

In the second construction in which, when each image display position assumed for a signal inputted during the predetermined period varies in a cycle given by integral multiples of the predetermined period, that is, when the number of pixel information in the second direction, inputted during one cycle, is K x w (= m), during the first period (the first field period), the K x P numbered pixel information in the second direction is outputted, and during the second period (the second field period), the K x P + B numbered image information is outputted, control is provided in such a manner that: during the first period, based upon the P numbered pixel information in the second direction assumed for the input signal, the K x P-q numbered to K x P + r numbered pixels (where q and r are integers satisfying q + r = K-1 and K is an integer not less than 2) that are adjacent in the second direction are allowed to have the same display state by controlling them at the same time; and during the second period, based upon the P numbered pixel information assumed for the input signal, the K x P + B-q numbered to K x P + B + r numbered pixels that are adjacent in the second direction are allowed to have the same display state by controlling them at the same time.

With the above-mentioned arrangement, the K x P numbered through K x P + K-1 numbered pixel information, assumed for the input signal, is displayed all through the K fields. Here, this construction is also applicable to the display control means of the aforementioned display including the first and second electrodes.

In the above-mentioned two constructions, the same scanning method as the aforementioned TFT interlace scanning is carried out, and the peak value of dynamic false contours is minimized by this scanning method. This is supposedly because, by the interlace scanning of the TFT type, the respective pixels on the K x P numbered common electrode and the K x P + K-1 numbered common electrode, displayed during the first period, come to have respectively different display states in the succeeding second period in such a manner that the pixels on the P numbered common electrode and pixels on the adjacent P-1 numbered and P + 1 numbered common electrodes are allowed to have different gradation transitions. With the matrix-type display of this type, even in the case of the application of TFT interlace scanning, it is possible to easily provide a gradation transition so as to reduce the amount of occurrence of dynamic false contours.

In a matrix-type display to which the display control means in any one of the above-mentioned matrix-type displays is applied, each pixel is preferably constituted by a plurality of sub-pixels. This arrangement makes it possible to provide not less than twice the number of gradations that can be displayed by each pixel during a predetermined period, thereby making it possible to easily increase the number of gradations.

In the above-mentioned display control means in any one of the aforementioned matrix-type displays, when provision is made to switch the display state of a desired pixel from any of the display states to a predetermined display state, the response time (hereinafter, referred to as sub-field period) is set shorter than the above-mentioned predetermined period; in this manner, the control process becomes more effective. This effect is anticipated by the fact that the dynamic false contours, which raise no problem in the case of displays of the cumulative response type such as TN liquid crystal, come to raise problems in the case of displays using time-division gradation display with high response speeds, such as ferroelectric liquid crystal displays and PDPs. In other words, the displays to which the present invention is applied are assumed as displays in which the time it takes for each pixel to change from any of the display states to a predetermined display state is shorter than one field period.

Moreover, taking the cause of the generation into consideration, those displays are assumed as displays in which the response time it takes to change the display state of each pixel of the display is set shorter than the subfield period having the minimum time width within a plurality of sub-field scanning periods.

In particular, the displays to which the present invention is applied are assumed as displays which can continuously maintain a display state that has been recorded through one sub-field period, such as plasma displays and ferroelectric liquid crystal displays.

With this arrangement, it is possible to reduce the adverse effects of dynamic false contours that raise problems in displays having high response speeds using a time-division display system, such as ferroelectric liquid crystal displays and PDPs.

The invention will now be more particularly described, by way of example only, with reference to the following drawings, in which: Fig. 1 is a plan view that shows a schematic construction of a ferroelectric liquid crystal display in accordance with one embodiment of the present invention; Fig. 2 is a cross-sectional view that shows a schematic construction of a ferroelectric liquid crystal panel in the above-mentioned ferroelectric liquid crystal display; Fig. 3 is a graph that shows the characteristic of the applied voltage to the switching pulse width of the ferroelectric liquid crystal panel; Figs. 4 (a) and 4 (b) are waveform diagrams that show pulse waveforms that are applied to a ferroelectric liquid crystal panel so as to measure the respective characteristics a and ss of Fig. 3; Fig. 5 (a) is a schematic view that shows a memory state of the ferroelectric liquid crystal molecules when viewed from the glass substrate side; and Fig. 5 (b) is a schematic view that shows a state of the ferroelectric liquid crystal molecules in a smectic C phase; Fig. 6 is a waveform diagram that shows a driving waveform used in a JOERS/ALVEY driving method that is applied to the ferroelectric liquid crystal panel; Fig. 7 is a waveform diagram that shows various waveforms that are used in a blanking driving method that is applied to the ferroelectric liquid crystal panel; Fig. 8 (a) is a schematic drawing that shows an image position assumed for an input signal used Embodiment 1 of the present invention; and Fig. 8 (b) is a schematic view that shows the relationship between display pixel information and pixel information of an input signal in the 2N field ; Fig. 9 (a) is an explanatory drawing that shows the relationship between the pixel position assumed for an interpolating signal of the 2N + 1 field and a pixel position assumed for the input signal; and Fig. 9 (b) is an explanatory drawing that shows the relationship between display pixel information and pixel information of the interpolating signal in the 2N + 1 field; Fig. 10 (a) is an explanatory view that shows an image position assumed for an input signal to a display device for comparative use shown in the above-mentioned Embodiment 1; and Fig. 10 (b) is an explanatory view that shows the relationship between display pixel information of the display device for comparative use and pixel information of the input signal; Fig. 11 is a block diagram that shows the construction of a digital filter for forming the interpolating signal; Fig. 12 (a) is a graph that shows the results of a theoretical simulation carried out on the amount of occurrence of dynamic false contours that appear in the pixel information display of Fig. 10 (b); and Fig. 12 (b) is a graph that shows the results of a theoretical simulation carried out on the amount of occurrence of dynamic false contours that appear in each of the pixel information displays of Fig. 8 (b) and Fig. 9 (b); Fig. 13 (a) is an explanatory drawing that shows an image position assumed for the input signal of the 2N field used in Embodiment 2 in the present invention; and Fig.

13 (b) is an explanatory drawing that shows the relationship between display pixel information of the display device and pixel information of an input signal in the 2N field; Fig. 14 (a) is an explanatory drawing that shows the relationship between a pixel position assumed for an input signal of the 2N + 1 field used in the above-mentioned Embodiment 2 and a pixel position assumed for the input signal; and Fig. 14 (b) is an explanatory drawing that shows the relationship between display pixel information of the 2N + 1 filed and pixel information of the interpolating signal; Fig. 15 is an image which is included in place of a drawing so as to confirm the occurrence of dynamic false contours in the case when a normal TV signal (NTSC signal) was actually applied to a ferroelectric liquid crystal panel in the above-mentioned Embodiment 2; Fig. 16 is a plan view that shows an electrode construction used for dividing a pixel into two sub-pixels in the FLCD of the above-mentioned Embodiment 2; Fig. 17 (a) is an explanatory drawing that shows an image position assumed for the input signal used in Embodiment 3 of the present invention; and Fig. 17 (b) is an explanatory drawing that shows the relationship between the display pixel information of the 3N field used in Embodiment 3 of the present invention and pixel information of the input signal; Fig. 18 (a) is an explanatory drawing that shows the relationship between a pixel position assumed for the interpolating signal of the 3N + 1 field used in the abovementioned Embodiment 3 and a pixel position assumed for the input signal; and Fig. 18 (b) is an explanatory drawing that shows the relationship between display pixel information of the 3N + 1 field and the pixel information of the interpolating signal; Fig. 19 (a) is an explanatory drawing that shows the relationship between a pixel position assumed for the interpolating signal of the 3N + 2 field used in the abovementioned Embodiment 3 and a pixel position assumed for the input signal; and Fig. 19 (b) is an explanatory drawing that shows the relationship between display pixel information of the 3N + 2 field and the pixel information of the interpolating signal; Fig. 20 (a) is an explanatory drawing that shows an image position assumed for the input signal used in Embodiment 4 of the present invention; and Fig. 20 (b) is an explanatory drawing that shows the relationship between the display pixel information of the 2N field used in Embodiment 4 of the present invention and pixel information of the input signal; Fig. 21 (a) is an explanatory drawing that shows the relationship between a pixel position assumed for the interpolating signal of the 2N + 1 field used in the abovementioned Embodiment 4 and a pixel position assumed for the input signal; and Fig. 21 (b) is an explanatory drawing that shows the relationship between display pixel information of the 2N + 1 field and the pixel information of the interpolating signal; Fig. 22 is an explanatory drawing that shows an arrangement of a display screen so as to explain the interlace scanning that has been conventionally used in the ferroelectric liquid crystal display.

Fig. 23 is a block diagram that explains a construction for providing pixel-division 8 gradation display that has been used in the conventional ferroelectric liquid crystal display; Fig. 24 is an explanatory drawing that shows an arrangement of a field for providing time-division 8 gradation display that has been used in the conventional ferroelectric liquid crystal display; Fig. 25 is an explanatory drawing that shows an arrangement of a field for providing time-division 256 gradation display that has been used in the conventional plasma display panel; Fig. 26 is an explanatory drawing that shows an arrangement of a field so as to explain problems with still images at the time of providing the above-mentioned timedivision 256 gradation display; Fig. 27 is a conceptual drawing that explains problems with moving images at the time of providing the abovementioned time-division 256 gradation display; Fig. 28 is an explanatory drawing that shows an arrangement of a field for providing time-division 256 gradation display by using the upper-bit division re arranging method that has been used in the conventional plasma display panel; Fig. 29 is an explanatory drawing that shows an arrangement of a field for providing time-division 256 gradation display by using the upper-bit division method that has been used in the conventional plasma display panel; and Fig. 30 is an explanatory drawing that shows an arrangement of another field for providing time-division 8 gradation display that has been used in the conventional ferroelectric liquid crystal display.

Referring to Figs. 1 through 21, the following description will discuss embodiments of the present invention.

[Basic Construction of Display Apparatus] First, an explanation will be given of the basic construction of a ferroelectric liquid crystal display (FLCD) used in the present embodiments.

As illustrated in Fig. 2, the present FLCD is provided with an FLC panel 1. In this FLC panel 1, two glass substrates 2 and 3 are placed face to face with each other, a plurality of transparent segment electrodes S, made of indium tin oxide (hereinafter, referred to as ITO), etc., are arranged in parallel with each other on the surface of one of the glass substrates, and this is coated with a transparent insulating film 4 made of SiO2, etc.

On the surface of the other glass substrate 3 facing the segment electrodes S, a plurality of transparent common electrodes L, made of ITO, etc., are arranged in parallel with each other in a direction orthogonal to the segment electrodes S, and this is coated with a transparent insulating film 5 made of SiO2, etc. Transparent alignment films 6 and 7, which have been subjected to a rubbing treatment, etc. and are made of polyvinyl alcohol, are formed on the insulating films 4 and 5 respectively. The two sheets of the glass substrates 2 and 3 are bonded to each other with a sealing agent 9 with an injection opening being left at one portion, and FLC is introduced into a space sandwiched by the alignment films 6 and 7 through the injection opening by vacuum injection, etc., and the injection opening is then sealed with the sealing agent 9.

Thus, a liquid crystal layer 8 is formed.

The two glass substrates 2 and 3 thus bonded to each other are sandwiched by two polarizing plates 18 and 19 that are placed with their polarization axes being orthogonal to each other.

Here, the gap between the common electrode L and the segment electrode S is approximately 1.0 to 1.5 ym.

In the present embodiment, a ferroelectric liquid crystal composition in which SCE-8 made by Merck & Co., Inc. and a composition FB-029 whose structural formula is shown below are blended in a ratio of 9: 1 is used, and an alignment film PSI-A-2101 (made by Chisso Corporation) is used as the alignment films 6 and 7.

[Formula 1]

Here, this ferroelectric liquid crystal has a negative dielectric anisotropy.

Moreover, Fig. 3 shows the relationship between the voltage of a pulse and the memory pulse width to be applied to the ferroelectric liquid crystal composition. In Fig. 3, the characteristic indicated by ss is based upon data measured by multiplexing a bias voltage of 7.5 V as shown in Fig. 4 (a), and in Fig. 3, the characteristic indicated by a is based upon data measured by multiplexing a bias voltage of 0 as shown in Fig. 4 (b).

FIG. 1 is a plan view that schematically shows the construction of an FLCD 20. In this FLCD 20, a common-side driving circuit 11 is connected to the common electrodes L of the FLC panel 1, and a segment-side driving circuit 12 is connected to the segment electrodes S thereof. Moreover, the common-side driving circuit 11 and the segment-side driving circuit 12 are controlled by a control section 31.

Here, n-number of common electrodes L defined as first electrodes are placed in a first direction (horizontal direction), and m-number of segment electrodes S defined as second electrodes are placed in a second direction orthogonal to the first direction. Thus, with respect to pixels formed at intersections between the common electrodes L and the segment electrodes S, m-number of pixels are formed in the first direction and n-number of pixels are formed in the second direction; thus, the FLC panel 1 has m x n number of pixels.

For convenience of explanation, Fig. 1 exemplifies a case in which 16 common electrodes L and 16 segment electrodes S are provided, that is, a case having 16 x 16 pixels. The respective common electrodes L are identified by applying subscript i (i = 0 to F) to reference symbol L, and the respective segment electrodes S are identified by applying subscript j (j = 0 to F) to reference symbol S.

Moreover, in the following explanation, a portion at which an arbitral common electrode Li and an arbitral segment electrode Sj intersect each other is defined as pixel Aij.

The common-side driving circuit 11 for applying a voltage to the common electrodes L is constituted by a shift register 13 and an analog switch array 14. In this commonside driving circuit 11, input data YI of 1 bit is transferred by the shift register 13 in response to a clock YCK. Here, when the value outputted to the output end of the shift register 13 is"1", the common-side driving circuit 11 applies a selection voltage Vcl to a common electrode Li that corresponds to the output end; when the above-mentioned value is"0", it applies a non-selection voltage Vco to a common electrode I.,., (k i) that corresponds to the output end; and when the above-mentioned value is "2", it applies an erasing voltage V to a common electrode Lh (h X k, h i) that corresponds to the output end.

Moreover, the segment-side driving circuit 12 for applying a voltage to the segment electrodes S is constituted by a shift register 15, a latch 16 and an analog switch array 17. In this segment-side driving circuit 12, input data XI is transferred by the shift register 15 in response to a clock XCK. Here, in the segment-side driving circuit 12, when the value of the corresponding input data XI is"2", a rewriting voltage Vs2 is applied to the segment electrode Sj ; when the value of the corresponding input data XI is"1", a holding voltage VS1 is applied to the segment electrode Sf (f j); and when the corresponding input data XI is"0", inactive voltage Vso is applied to the segment electrode Sg (g j, g f).

The control section 31 outputs input data XI, YI, clocks XCK, YCK, etc. so as to carry out a driving method and a display method, which will be described later.

As illustrated in Fig. 5 (b), FLC molecules 21 constituting a pixel Ai have a spontaneous polarization Ps that is perpendicular to the major axis direction.

Therefore, the FLC molecules 21 is subjected to a force that is proportional to a vector product between an electric field E exerted by an electrical potential difference between the common electrode L and the segment electrode S and the spontaneous polarization Ps, with the result that they are allowed to shift on the surface of a cone 24 having an apex angle with a doubled tilt angle 28. In the FLCD 20 having a narrow cell gap as described above, the FLC molecules 21 have bistable states Pi and P2 as shown in Fig.

5 (a), and consequently have a characteristic in which they exhibit the stable state PI when shifted to the axis 22 by the electric field E and also exhibit the stable state P2 when shifted to the axis 23 by the electric field E.

Moreover, the FLC molecules 21 have a restoring force for returning to the original stable state even when moved by the electric field E, as long as their acquired stable state has not changed.

Therefore, when one of the memory states of the FLC molecules 21 is made coincident with the polarization axis of the polarizing plate 18 and 19 shown in Fig. 2, a pixel constituted by the FLC molecules 21 in this memory state looks darker, while a pixel constituted by the FLC molecules 21 in the other memory state looks lighter.

[Driving method used in the present embodiment] Next, an explanation will be given of a driving method for the FLCD used in the present embodiment.

Figs. 6 (a) and 6 (b) show a JOERS/ALVEY driving method (hereinafter, referred to as J/A driving method) used in the present embodiment, and this driving method has been reported as"The JOERS/ALVEY Ferroelectric Multiplexing Scheme"by DRA (Defense Research Agency) in FLC'91 Society.

In the J/A driving method, a writing process for one screen is carried out by using two fields, and a driving waveform, shown in Fig. 6 (a), is applied in the first field, and another driving waveform, shown in Fig. 6 (b), is applied in the second field.

In other words, in the case when one stable state of the FLC molecules constituting a pixel Ait vis rewritten to the other stable state, a selection voltage VCAZ shown in Fig. 6 (a), is applied to the common electrode Li in the first field, and a voltage waveform Vsc, shown in Fig. 6 (a), is applied to the segment electrode Sj. At this time, a voltage waveform VA-c shown in Fig. 6 (a) is applied to the FLC molecules constituting the pixel Aij so that the stable state of the FLC molecules is rewritten to the other stable state. Moreover, in the second field, a selection voltage VCE shown in Fig. 6 (b), is applied to the common electrode Li, and a voltage waveform V,,,, shown in Fig. 6 (b), is applied to the segment electrode Sj. At this time, a voltage waveform VE~H, shown in Fig. 6 (b), is applied to the FLC molecules constituting the pixel Ait po that the stable state of the FLC molecules is maintained.

In the case when the stable state of the FLC molecules constituting a pixel Aij is rewritten to the other stable state, a selection voltage Va, show in Fig. 6 (a), is applied to the common electrode Li in the first field, and a voltage waveform VSG, shown in Fig. 6 (a), is applied to the segment electrode Si. At this time, a voltage waveform VA~G shown in Fig. 6 (a) is applied to the FLC molecules constituting the pixel Ail so that the stable state of the FLC molecules is not changed. Moreover, in the second field, a selection voltage Vice, shown in Fig. 6 (b), is applied to the common electrode Li, and a voltage waveform VSD, shown in Fig. 6 (b), is applied to the segment electrode si At this time, a voltage waveform VE DT shown in Fig.

6 (b), is applied to the FLC molecules constituting the pixel Aij so that the stable state of the FLC molecules is rewritten to the other stable state.

While the stable state of FLC molecules constituting another pixel Akj (k X 1) is being rewritten, a non-selection voltage Vu,,, shown in Fig. 6 (a), is applied to the common electrode Li in the first field. Since the voltage waveform Vsc or vs, shown in Fig. 6 (a), have been applied to the segment electrode Sj, the voltage waveform Vg ; ; or VB GZ shown in Fig. 6 (a), is applied to the FLC molecules constituting the pixel Aij so that the stable state of the FLC molecules is not changed. In the second field, a non-selection voltage V, shown in Fig. 6 (b), is applied to the common electrode Li. Since the voltage waveform VSD or Vgn, shown in Fig. 6 (b), is applied to the segment electrode Sj, a voltage waveform Vp~D or Vp~H, shown in Fig. 6 (b), is applied to the FLC molecules constituting the pixel Aij so that the stable state of the FLC molecules is not changed.

In the J/A driving method, a writing process of one screen is carried out by using the two fields, and the driving waveforms shown in Fig. 6 (a) are applied in the first field, and the driving waveform shown in Fig. 6 (b) are applied in the second field. Here, in a blanking driving method shown in Fig. 7 that was reported as"Colour Digital Ferroelectric Liquid Crystal Displays For Laptop Applications"in SID'92, a blanking pulse BP, which has a voltage-Vb (=-Vs/2) during a period from prior to 7 slot period to prior to 6 slot period, applies a selection voltage Vs to the common electrode for one slot period (time ts in Figs. 6 (a) and 6 (b)).

The application of this blanking pulse BP to the common electrode Li allows the voltage waveform shown in Fig. 7 to be applied to the FLC molecules constituting the pixel Aij ; therefore, even if the voltage waveform VSD or Vs shown in Fig. 6 (b), is applied to the segment electrode Sj, the stable state of the FLC molecules is forcefully rewritten to the other stable state independent of the voltage applied to the segment electrode Sj. Thereafter, the selection voltage VCE shown in Fig. 6 (b) is applied to the common electrode Li so that the voltage to be applied to the segment electrode Sj is set to the voltage waveform VSD or VSH shown in Fig.

6 (b); thus, the stable state of the FLC molecules can be either changed to the other stable state, or maintained in the same stable state selectively.

[Display device used in the Embodiment] The display device used in the present embodiment is an FLCD 20, shown in Fig. 1, to which the blanking driving method shown in Fig. 7 is applied.

More specifically, a selection voltage VCE having a J/A driving waveform shown in Fig. 6 (b) is applied as the selection voltage Vcl of the common-side driving circuit 11 of Fig. 1, a non-selection voltage VCF shown in Fig. 6 (b) is applied as the non-selection voltage Vco of the common-side driving circuit 11, and a blanking pulse BP (that is, voltage-Vs/2) of Fig. 7 is applied to the erasing voltage Vc2 of the common-side driving circuit 11 of Fig. 1. Thus, a common voltage shown in Fig. 7 is formed by inputting "... 0, 2,0,0,1,0..."as input data YI of the common-side driving circuit 11 in synchronism with the clock YCK.

Moreover, a re-writing voltage VSD of Fig. 6 (b) is applied as the re-writing voltage Vs2 of the segment-side driving circuit 12 of Fig. 1, a holding voltage VSH of Fig.

6 (b) is applied as the holding voltage Vsl of the segmentside driving circuit 12, and a non-selection voltage VCF of Fig. 6 (b) is applied as the inactive voltage Vso of the segment-side driving circuit 12 ; thus, a segment voltage shown in Fig. 7 is formed.

Here, in this case, Vgj, of Fig. 6 (b) is applied to the segment electrode Sj, and the polarizing plates 18 and 19 are positioned while they are rotated with respect to the FLC panel 1 with the polarization axes of the polarizing plates 18 and 19 of Fig. 2 being maintained orthogonal to each other so as to make the panel 1 darkest; therefore, after application of the blanking pulse BP, the FLC molecules are supposed to be set in one of the memory states.

Moreover, in the FLCD 20, by applying a common voltage of Fig. 7 to the common electrode Li of the FLC panel 1, the display state of the pixels placed on the common electrode Li can be controlled. For example, the application of the common voltage to the common electrode L1 makes the display state of the pixels placed on the common electrode Li controllable at the same time within the first selection period in Fig. 7, and the application of the common voltage to the common electrode L3 with one selection-period delay makes the display state of the pixels placed on the common electrode L3 controllable at the same time within the succeeding second selection period.

In the case when the FLCD 20 is driven under a voltage VS of 35 V and a voltage Vd of 6 V, it is expected that from the characteristic under the voltage V (= Vs-Vd = 29V) shown in Fig. 3, the switching time will be approximately 60 ps. In fact, since one selection period (hereinafter, sometimes referred to as 1 LAT: Line Address Time) corresponds to 2 slot time (2ts), it has been confirmed that the driving operation is available with 1 slot time ts being set at 30 pu [Display Method in the Present Invention] It is a premise in the present FLCD that m number of pixels are placed in the length direction (first direction) of the common electrodes L with n number of (both m and n are integers) pixels being placed in the length direction of the segment electrodes S (second direction) so that display states of the m number of pixels placed in the first direction and the n number of pixels placed in the second direction are controlled at the same time, and that gradation display is provided by allowing the same pixel to light on a plurality of times. Here, supposing that, although the number of pixels is m x n, the number of pixels that are to be assumed for signals inputted to the m x n number of pixels by the control section 31 is w x u (w and u are integers), the display control is carried out in a manner so as to satisfy the following relationship of m, n, w and u (K is an integer not less than 2): m w x K, and n u.

The display control of the control section 31 is carried out in the following two manners in accordance with the input signals.

(1) In the first display control, in the case when the image display positions to be assumed for input signals during each field (or frame) period, are the same in all fields, during the first period (first field period), based upon the P-numbered image information that is to be assumed for an input signal, the K x P-q through the K x P + r numbered pixels (where q and r are integers satisfying q + r = K-1) adjacent in the second direction of the display are simultaneously controlled so as to provide the same display state. In the succeeding second field period, interpolating information is formed based upon the P numbered and the P + 1 numbered pixel information that are to be assumed for input signals so that the K x P + B-q through the K x P + B + r numbered pixels (where B is an integer satisfying 1 s B s K-1) adjacent in the second direction are simultaneously controlled so as to provide the same display state.

(2) The second display control is carried out in the case when the image display positions to be assumed for input signals during each field (or frame) period, are changed with a cycle given by integral multiples of the given period, that is, in the case when the image display positions to be assumed for input signal during each field period, are offset for each field period. In this case, more specifically, supposing that the number of pieces of pixel information in the second direction to be inputted for one cycle is K x w (-m), the pixel information of the K x P numbered pixel information in the second direction is outputted in the first period (during the first field period), and the pixel information of the K x P + B numbered pixel in the second direction is outputted in the second period (during the second field period). In the second display control, during the first field period, based upon the P-numbered image information to be assumed for an input signal, the K x P-q through the K x P + r numbered pixels (where q and r are integers satisfying q + r = K-1) adjacent in the second direction of the display are simultaneously controlled so as to provide the same display state. In the succeeding second field period, based upon the P numbered pixel information to be assumed for an input signal so that the K x P + B-q through the K x P + B + r numbered pixels (where B is an integer corresponding to the display positional offset in the above-mentioned input signal) adjacent in the second direction are simultaneously controlled so as to provide the same display state.

Additionally, it is preferable to set the value of K at 2 to 4 in order to reduce the occurrence of line flickers, etc.

[EMBODIMENT 1] For convenience of explanation and simplicity of drawings, the construction of the FLCD 20 shown in Fig. 1, in which 16 (= m) pixels on the common side (16 common electrodes L) x 16 (= n) pixels on the segment side (16 segment electrodes S) are arrang scanning is carried out on 4 sub-fields obtained by dividing one field period with a time width ratio of 1: 8: 4: 8; thus, 64 gradations have been achieved in the display.

Fig. 8 (a) shows the number of pixels that are to be displayed on the FLCD having the above-mentioned 16 x 16 pixels and to be assumed for transmitted input signals, and in this case, the number of pixels is 8 x 16. The present embodiment will discuss a case in which the y-direction of pixel information to be displayed by the respective pixels of Fig. 8 (a) is made orthogonal to the length direction of the common electrodes of the FLCD of the present embodiment while the z-direction thereof is made orthogonal to the length direction of the segment electrodes of the FLCD of the present embodiment, so as to carry out a display operation. The same definitions as to the y-direction and z-direction are used in the following descriptions: In the present embodiment, the above-mentioned value K is set to 2, and as shown in Fig. 8 (b), in the 2 N field (N: an integer), based upon the P-numbered (P: integers from 0 to 7) pixel information DP, J (where J (integer of 0 to 15) represents an arbitral pixel number on the segment electrodes) in the y-direction of the sent image information, pixels A2P, J and A2P+1, J, located on the 2P numbered and the 2P + 1 numbered common electrodes of the FLCD, are displayed.

In the succeeding 2N + 1 field, as shown in Fig. 9 (a), based upon the pieces of pixel information DP, J and DP+1, J, that is, the P-numbered and P + 1 numbered (where P is an integer from 0 to 6) image information in the y-direction that has been temporarily transmitted, a piece of interpolating information CP, J is formed by using an LPF (Low-Pass Filter), etc.

More specifically, in the case of the application of an LPF, a digital filter 41 is preferably used as illustrated in Fig. 11. The digital filter 41 is provided with 1H delay circuits 42 to 45, multipliers 46 to 49 and an adder 50.

The 1H delay circuits (1HDL) 42 to 45, which are delay circuits for delaying inputted image information by 1H (1 horizontal scanning period), are connected in series with each other. The multipliers 46 to 49 multiply the pieces of image information outputted from the 1H delay circuits 42 to 45 by coefficients kas,, kB3, kB2 and k., respectively. The adder 50 adds the results of multiplication from the multipliers 46 to 49 so as to output interpolating information CP (B), J.

In the case of formation of the interpolating information CP, J based upon the pixel information DP, J and DP+1, J, the 1H delay circuits 43 and 44 and the multipliers 47 and 48 are normally used; however, in the present embodiment, since the value K is set to 2 as described earlier, the 1H delay circuits 42 and 45 and the multipliers 46 and 49 are further used. In this case, the abovementioned coefficients kB4, kB3, kB2 and kBl are set as follows: kB4 =-0. 13088 kB3 = 0. 630881 kB2 = 0.630881 kBi =-0. 13088 Here, in the case when only the pieces of image information DP, J and DP+1, J are used for simplicity, the coefficients kob4, kB3, kB2 and kBl are set as follows: kB4 = 0 kB3 = 0 5 kB2 = 0. 5 ksi = 0 Consequently, the interpolating information CP (B), J is obtained from the following operation: CP (B), J = (DP, J, DP+1, J)/2 Then, as shown in Fig. 9 (b), based upon the interpolating information CP, J, the pixels A 2P + 1, J, A 2P + 2, J on the 2P + 1 numbered and 2P + 2 numbered common electrodes of the FLCD are displayed.

In this case, since the interpolating information CP, J for the pixel AOJ or AFJ is not formed, original pixel information DP, J is given to these pixels.

Moreover, Fig. 10 (a) and Fig. 10 (b) show an input signal and a display state of the 2N field in the case when, in the FLCD having a pixel array of 8 pixels on the common side x 16 pixels on the segment side (hereinafter, referred to simply as 8 x 16 pixels), the P-numbered pixel information DP, J (P representing an integer of 0 to 7) in the y-direction of the image information that has been sent, as it is, is displayed on the pixel APJ on the P-numbered common electrode of the FLCD. Comparison was made on the amount of occurrence of dynamic false contours between the case in which display is made as described above and the case as shown in Figs. 8 (a) and 8 (b) or Figs. 9 (a) and 9 (b); and the results of the comparison are shown in Figs. 12 (a) and 12 (b).

Here, in general, it is difficult to actually measure dynamic false contours because of the characteristics of the dynamic false contours. This is because the occurrence of dynamic false contours is caused by the fact that human eyes naturally follow an object. When the line of sight follows an object in motion, unexpected fog occurs in an image gradation-displayed in a time-divided manner (see Fig. 27), resulting in dynamic false contours.

Therefore, it is difficult to mechanically measure the size of dynamic false contours, and instead of this, a method shown in"Dynamic False Contours on PDPs-Fatal or Curable ?" of IDW'96 that has been described as the prior art is used, in which the cause of the occurrence of dynamic false contours, that is, the motion of the line of sight, and the luminance state of the pixel located on the line of sight at the moment of each motion are taken into consideration so that, from calculations to obtain the accumulated data, the amount of occurrence of dynamic false contours (deviation between the gradation level that is supposed to be obtained and a gradation level that is actually observed) is theoretically calculated; and based upon the results of the calculations, an explanation will be given of the effects of the present invention only in a theoretical manner.

Figs. 12 (a) and 12 (b) show the results of the theoretical calculations. These Figures show examples of calculations in the case when scanning is carried out from top to bottom at a rate of 6 lines per field, and in this case, the driving scheme for scanning 4 sub-fields obtained by dividing one field period into time-width ratios of 1: 8: 4: 8 (4 bits). For convenience of explanation, in these theoretical calculations, it is assumed that a picture image, which makes a transition from the gradation level "31" (which makes dynamic false contours most conspicuous) to"32" (in this case, the 64 gradations have gradation levels of"0"to"63"), is shifted in the vertical direction (from bottom to top) at a rate of 3 lines per 1 field, that is, it is assumed that a picture image, located at D7J in Fig. 8 (b), is shifted to D4J.

Fig. 12 (a) shows a case in which non-interlace scanning is carried out so that pixel information of 8 x 16, shown in Fig. 10 (a), simply transmitted is displayed by using a pixel array consisting of 8 x 16 pixels shown in Fig. 10 (b). In contrast, Fig. 12 (b) shows a case in which interlace scanning is carried out so that pixel information of 8 x 16 of the present invention, shown in Fig. 8 (a), is displayed by using a pixel array consisting of 16 x 16 pixels shown in Fig. 8 (b).

In both of Figs. 12 (a) and 12 (b), thick solid lines indicate gradation levels that are originally supposed to be obtained, solid lines with symbols o indicate gradation levels displayed on the FLCD, and the difference of these corresponds the amount of occurrence of dynamic false contours. As clearly shown by these Figures, Fig. 12 (b) indicates a reduced amount of the occurrence of dynamic false contours achieved by the present invention.

As described above, in a display for gradationdisplaying images in a time divided manner, the application of interlace scanning of 2: 1 makes the peak value of dynamic false contours smaller. This is supposedly because, in the interlace scanning of the TFT type, the pixel on the 2N numbered common electrode and the pixel on the 2N + 1 numbered common electrode that are displayed in the first field period, come to exhibit mutually different display states in the succeeding second field with the result that the pixel on the N numbered common electrode has a different gradation transition from the adjacent pixels on the N-1 numbered common electrode and the N + 1 numbered common electrode.

Not limited to the interlace scanning of 2: 1 as shown in Fig. 12 (b), the same reasons for such effects are applicable to the interlace scanning of 3: 1 which will be explained later in Embodiment 3 (see Figs. 18 (a) and 18 (b) as well as Figs. 19 (a) and 19 (b)) and the interlace scanning having an arbitral ratio such as 4: 1, not shown. In addition, these processes are carried out without changing the width of one-selection period of the FLCD.

In the case when a 64 gradation displaying process is obtained by scanning the pixel array consisting of 8 x 16 pixels of Fig. 10 (b) by the use of 4 sub-fields with the time-width ratios of 1: 8: 4: 8, the width of one selection period (LAT) is found as follows: 1 LAT = (1/field frequency) x (1/8) x (1/number of sub-fields) = (1/60) x (1/8) x (1/4) = 520 [s] Here, in the case when a 64 gradation displaying process is obtained by scanning the pixel array consisting of 16 x 16 pixels of Fig. 9 (b) by the use of 4 sub-fields with the time-width ratios of 1: 8: 4: 8, the width of one selection period LAT is found as follows: 1 LAT = (1/field frequency) x (1/9) x (1/number of sub-fields) = (1/60) x (1/9) x (1/4) = 463 [s] In this manner, the width of one selection period 1 LAT virtually is not shortened.

In particular, in a pixel array consisting of 240 pixels on the common side x 320 pixels on the segment side that is actually used, the width of one selection period 1 LAT in the case of Fig. 10 (b) is found as follows: 1 LAT = (1/60) x (1/120) x (1/4) ~ 34. 7 [s] In the case of Fig. 9 (b) also, the width of one selection period 1 LAT virtually is not shortened.

1 LAT = (1/60) x (1/121) x (1/4) =-34. 4 [lis] As described above, the present invention is effective for addressing the problem of dynamic false contours in a display for scanning a plurality of sub-fields in one subfield period, such as PDPs and FLCDs.

In the present embodiment, one pixel of the FLCD is divided into partial pixels having an area ratio of 1: 2; however, it is clear that the present invention is effective independent of ratios of the pixel division.

[Embodiment 2] In the above-mentioned Embodiment 1, in the 2N + 1 numbered field, interpolating information CP, J is formed based upon the P numbered and P + 1 numbered (where P is an integer of 0 to 6) pixel information DP, J, DP+1, J in the ydirection of image information that has been temporarily sent, and based upon the interpolating information CP, J, the pixels A2P+1, J, A2P+2, J on the 2P + 1 numbered and 2P + 2 numbered common electrodes of the pixel array are displayed.

However, when the input signal is given as an interlace signal of 2: 1, as shown in Fig. 13 (a) and Fig. 14 (a), the assumed image position has already been offset in the ydirection by 1 line between the input signal for the 2N field and the input signal for the 2N + 1 field.

In such a case, the following arrangement has the same effects : As shown in Fig. 13 (b), in the 2N field (N: integer), based upon the P numbered (where P is an integer of 0 to 7) image information DP, J in the y-direction of the image information that has been sent, the pixels A2P, J, A2P + 1, J on the 2P numbered and 2P + 1 numbered common electrodes of the pixel array are displayed. As shown in Fig. 14 (a), in the succeeding 2N + 1 field, based upon the P numbered (where P is an integer of 0 to 7) image information DP, J in the y-direction of the image information that has been sent, the pixels A2 P + 1, J, A2 P + 2, J on the 2P + 1 numbered and 2P + 2 numbered common electrodes of the FLCD are displayed; this arrangement makes it possible to provide the same effects.

The present embodiment is similar to the interlace method of the TFT system that has been explained as the prior art. Specifically, in the case when by using the interlace method of the TFT system, scanning is carried out using an input signal that corresponds to an interlace signal of 2: 1, the same display state is obtained by simultaneously selecting pixels on the 2N numbered and 2N + 1 numbered common electrodes in the first field period, and in the succeeding second period, the same display state is obtained by simultaneously selecting pixels on the 2N-1 numbered and 2N numbered common electrodes. Thus, the interlace method of the TFT system is similar to the scanning method of the present embodiment.

However, conventionally, the above-mentioned interlace method of the TFT system has not been applied to the FLCD.

One of the reasons for this is that the TFT and the FLCD have a definite difference in the optical response speed.

Although it has a memory property, the TFT has an optical response time longer than two field period; therefore, since each line is not allowed to respond to each field, no problem arises even if the interlace scanning of 2: 1 is carried out on the TFT system. For this reason, it has been considered that in the case of a display having a memory property and a high response speed such as the FLC, the application of the interlace scanning of 2: 1 of the TFT system might cause a problem in image quality.

Moreover, probably, another reason for this is that it has been considered that the application of the interlace method of the TFT system to the FLCD having a memory property would be meaningless. In other words, probably, it has been considered that the interlace method as explained in JP 63-298286 in the Prior Art is effective for the FLCD having a memory property and that the interlace scanning method of the TFT system that does not effectively utilize the memory property of the FLCD is not suitable for the FLCD.

However, in the case when the interlace method of JP 63-298286 is applied to the FLCD using a time-division gradation display system that is related to the present invention, upon carrying out interlace scanning of 2: 1, data is written in the pixel on the 2N numbered common electrode in the first field, and in the second field, data is written in the pixel on the 2N + 1 numbered common electrode. In this case, a problem arises as to how to deal with pixels on the common electrodes that are not subjected to the writing operation in each field. For example, when these pixels are left in the same display state as written in the previous field, the display state in specific sub-field periods in the previous field remains in the next field, thereby causing abnormalities in images.

One solution for this is to change (erase) the display state of these pixels into a dark state; however, the quantity of transmitting light through the FLC panel is reduced by half, and the backlight has to be made brighter to compensate for the reduction. This results in another problem of an increase (two times) in the power consumption of the backlight and a temperature rise of the FLC panel due to light absorption of the FLC panel and heat generation of the backlight.

Here, instead of the interlace method of JP 63-298286, the interlace method of the TFT type becomes meaningful.

Actually, an FLC panel having 240 pixels on the common side x 320 pixels on the segment side (in which since the common side is divided into up and down sides, this case is actually coincident with the aforementioned case of calculations for driving 120 common electrodes) was manufactured, and a portrait, shown in Fig. 15, was displayed by using a common TV signal (NTSC signal) so as to confirm the case in which 64 gradation display was provided by the interlace scanning of 2: 1 of the TFT system.

First, the interlace scanning of the FLCD was stopped, and when a display was made by simultaneously selecting the combination of the same two common electrodes in the odd field and the even field, there was a difference between the assumed display position for the input signal and the display position in the FLCD. Consequently, it was confirmed that there was degradation in the image quality due to diagonal lines, or that, even except for this degradation, dynamic false contours occurred to a great degree.

Next, taking into consideration the offset in the display positions assumed for the input signal in the odd and the even fields resulting from the interlace scanning, the interlace scanning of the TFT system which changes the combination of the two common electrodes simultaneously selected in the odd and the even fields was carried out, and the results showed that the amount of occurrence of dynamic false contours with respect to movements in the vertical direction seemed to be reduced. Moreover, the reduction in the resolution in the vertical direction resulting from the interlace scanning of 2: 1, which had been feared, was not conspicuous. In particular, in the case of motionless images, it was not conspicuous at all.

Here, a slight reduction in the resolution was observed with respect to moving images; however, since the dynamic false contours gave more adverse effects on the image quality, the reduction in the resolution to such an extent was considered to be harmless.

As shown in Fig. 16, in the FLCD of the present embodiment, the segment electrode S is constituted by a pair of segment electrodes Sa and Sb the widths of which are represented by a ratio of 2: 1. Therefore, one pixel Aij is constituted by two sub-pixels Ai and AW having an area ratio of 2: 1. This arrangement is also applicable to the other embodiments.

[Embodiment 3] The above-mentioned embodiment exemplified a case in which K = 2 in the present invention, and this Embodiment exemplifies a case in which K = 3.

Fig. 17 (a) shows pixels the number of which is assumed by an input signal that is sent so as to display 16 x 16 pixels of Fig. 1 on the FLCD, and the number of the pixels is set to 16 x 16.

As shown in Fig. 17 (b), in the 3N field (N: integer), based upon the P numbered (where P is an integer of 0 to 5) image information DP, J in the y-direction of the image information that has been sent, the pixels A2P, J to A2P+2, J on the 2P numbered to 2P + 2 numbered common electrodes of the FLCD are displayed.

As shown in Fig. 18 (a), in the succeeding 3N + 1 field, based upon the P numbered and the P + 1 numbered (where P is an integer of 0 to 4) image information DP, J, DP+1, J in the y-direction of the pixel information that has been temporarily sent, first interpolating information CP, J is formed, and based upon the interpolating information CP, J, the pixels A2P+1, J to A2P+3, J on the 2P + 1 numbered to 2P + 3 numbered common electrodes of the FLCD are displayed.

As shown in Fig. 19 (a), in the succeeding 3N + 2 field, based upon the P numbered and the P + 1 numbered (where P is an integer of 0 to 4) pixel information DP, J, DP+1, J in the y-direction of the image information that has been temporarily sent, second interpolating information CP, J is formed, and as shown in Fig. 19 (b), based upon the interpolating information CP, J, the pixels A2P+1, J to A2P+3, J on the 2P + 2 numbered to 2P + 4 numbered common electrodes of the FLCD are displayed.

In this case, since the interpolating information CP, J for the pixels AOJ to A1J or AEJ to AFJ is not formed, original pixel information DP, J is given to these pixels.

In this case also, it is possible to reduce the amount of the occurrence of dynamic false contours in the same manner as Embodiment 1.

As described above, it is possible to increase the number of common electrodes K to be simultaneously scanned in each field, and the corresponding effects can be obtained; however, the following problems arise. For example, one of the problems is that, since the electrode pitch becomes finer due to the increase of the number of the common electrodes, it becomes difficult to manufacture the FLC panel. Another problem is that, since the gap between the common electrodes has a limitation in panel production so as to prevent leakage between ITOs (electrode material), the effective pixel area within a panel (an area at which the ITOs on the common side and the segment side intersect each other) becomes smaller when the gap is made constant.

In order to prevent such problems, it is preferable to set K in the range of 2 to 4 from the viewpoint of practical use.

[Embodiment 4] The above-mentioned Embodiment 3 has exemplified cases in which among pieces of pixel information that is sent so as to display the pixel array consisting of 16 pixels on the common side x 16 pixels on the segment side shown in Fig. 1, those pieces of information in the y-direction are smaller than those in the other directions; however, the present invention is also applicable to cases in which those pieces of information in the z-direction is smaller.

Fig. 20 (a) shows pixels the number of which is assumed by an input signal that is sent so as to display the abovementioned pixel array, and the number of the pixels is set to 16 x 8.

As shown in Fig. 20 (b), in the 2N field (N: integer), based upon the P numbered (where P is an integer of 0 to 7) image information DI, P in the z-direction of the image information that has been sent, the pixels AI, 2P, AI, 2P+1 on the 2P numbered to 2P + 1 numbered segment electrodes of the FLCD are displayed.

As shown in Fig. 21 (a), in the succeeding 2N + 1 field, based upon the P numbered and the P + 1 numbered (where P is an integer of 0 to 6) image information DI, J, DI, P+1 in the z-direction of the image information that has been temporarily sent, interpolating information CI, P is formed.

Then, as shown in Fig. 21 (b), based upon the interpolating information CI, P, the pixels AI, 2P+1, AI, 2P+2 on the 2P + 1 numbered and 2P + 2 numbered segment electrodes of the FLCD are displayed.

In this case, since the interpolating information CI, P for the pixel AIO or AIF is not formed, original pixel information DIP is given to these pixels.

Claims

CLAIMS:

1. A matrix-type display comprising: pixels arranged in a matrix format that consists of m number of them aligned in a first direction and n number of them aligned in a second direction (wherein both m and n are integers); and display control means for providing gradation display by simultaneously controlling the display state of m number of pixels aligned in the first direction and allowing the same pixels to light on a plurality of times during a predetermined period, wherein the display control means differentiates the combination of pixels for determining the display state based upon the same display information during a first period of the predetermined period from the combination of pixels for determining the display state based upon the same display information during a second period succeeding the first period of the predetermined period.

2. The matrix-type display according to claim 1, comprising: n number of first electrodes aligned in the first direction and m number of second electrodes aligned in the second direction, and a liquid crystal layer made of a ferroelectric liquid crystal interpolated between the first and second electrodes, wherein at each portion where the first electrode and the second electrode intersect each other, the opposing portions of the two electrodes and a portion of the liquid crystal layer sandwiched by these constitute a pixel.

3. The matrix-type display according to claim 1, wherein the display control means carries out display control in such a manner that supposing that the number of data pixels assumed for a signal inputted to m x n number of display pixels is w x u (where w and u are integers) and that K (where K is an integer of not less than 2) is used, the relationships among m, n, w and u satisfy the following equations: m w x K, and n u.

4. The matrix-type display according to claim 3, wherein K is set to any value in a range of 2 to 4.

5. The matrix-type display according to any one of claims 1 to 4, wherein, in the case when each image assumed for a signal inputted during the predetermined period always has the same display position, the display control means provides control in such a manner that: during the first period, based upon the P numbered pixel information assumed for the input signal, the K x P-q numbered to K x P + r numbered pixels (where q and r are integers satisfying q + r = K-1 and K is an integer not less than 2) that are adjacent in the second direction are allowed to have the same display state at the same time; and during the second period, based upon the P numbered and P + 1 numbered pixel information assumed for the input signal, interpolating information is formed and based upon this interpolating information, the K x P + B-q numbered to K x P + B + r numbered pixels (where B is an integer satisfying 1 s B s K -1) that are adjacent in the second direction are allowed to have the same display state at the same time.

6. The matrix-type display according to claim 5, wherein the display control means has a low-pass filter for forming the interpolating information.

7. The matrix-type display according to claim 6, wherein the low-pass filter is a digital filter which comprises a plurality of delay circuits, connected in series with each other, for delaying input image information respectively, by 1 horizontal scanning period, a plurality of multipliers for multiplying pieces of output information from the delay circuits by a predetermined coefficient, and an adder for adding the outputs of the multipliers.

8. The matrix-type display according to claim 1 or 2, wherein, in the case when each image assumed for a signal inputted during the predetermined period has a display position that varies in a cycle given by integral multiples of the predetermined period, the display control means provides control in such a manner that: during the first period, based upon the P numbered pixel information assumed for the input signal, the K x P-q numbered to K x P + r numbered pixels (where q and r are integers satisfying q + r = K-1 and K is an integer not less than 2) that are adjacent in the second direction are allowed to have the same display state at the same time; and during the second period, based upon the P numbered pixel information assumed for the input signal, the K x P + B-q numbered to K x P + B + r numbered pixels (where B is an integer representing a value corresponding to an offset in the display position of the input signal) that are adjacent in the second direction are allowed to have the same display state at the same time.

9. The matrix-type display according to any one of claims 1 to 8, wherein each pixel is constituted by a plurality of sub-pixels.

10. The matrix-type display according to any one of claims 1 to 9, wherein when the display control means controls any of the pixels so as to switch the display state thereof from any display state to a predetermined display state, its response time is made shorter than the predetermined period.