GB2344217A - Multichip module comprising stacked semiconductor chips - Google Patents

Multichip module comprising stacked semiconductor chips Download PDF

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Publication number
GB2344217A
GB2344217A GB9928115A GB9928115A GB2344217A GB 2344217 A GB2344217 A GB 2344217A GB 9928115 A GB9928115 A GB 9928115A GB 9928115 A GB9928115 A GB 9928115A GB 2344217 A GB2344217 A GB 2344217A
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United Kingdom
Prior art keywords
interconnection
semiconductor device
multichip module
pad
substrate
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GB9928115A
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GB9928115D0 (en
Inventor
Hiroshi Asazawa
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NEC Corp
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NEC Corp
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Publication of GB9928115D0 publication Critical patent/GB9928115D0/en
Publication of GB2344217A publication Critical patent/GB2344217A/en
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    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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Abstract

A multichip module, or MCM, comprises stacked chips 110, 120, and a substrate with two interconnection patterns 131, 132. One of the chips has interconnection pads on an upper surface, and the other has pads on a lower surface. In one embodiment, the bottom chip 110 is connected to pads on the substrate by solder bumps, and the top chip is connected via wire bonds 142. An alternative arrangement (fig. 9) has an upper chip connected to the lower chip by solder bumps, with connection to the substrate via wire bonds. The upper chip may be of equal or greater area than the lower chip (fig. 6).

Description

MULTICHIP MODULE BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multichip module, particularly to a stack-type multi-chip module having a plurality of stacked semiconductor chips.
2. Description of the Related Art Conventionally, a stack-type or a chip-on-chip configuration type multichip module having a plurality of stacked semiconductor chips, which may be large-scaled integrated circuits, is useful from the point of view that its occupation area on the implementation substrate in an electronic device is small, and high implementation density can be realized. Such kind of multichip module is disclosed in the technological report titled Start of Mass Production, First Development of"Stacked CSP"in the world', dated February 17, 1998.
As shown in Fig. 1, a conventional multichip module comprises stacked lower and upper semiconductor chips 310 and 320 and a package, with upward interconnection patterns 331 and 332 on the bottom substrate thereof, to house stacked lower and upper semiconductor chips 310 and 320. Only the upward interconnection patterns 331 and 332 are shown in Fig. 1 as parts of the package. As concerns the lower semiconductor chip 310, its interconnection pads 311 have been bonded to the interconnection patterns 331 by using bonding wires 341. On the other hand, as concerns the upper semiconductor chip, its interconnection pads 321 have been bonded to the interconnection patterns 332 by using bonding wires 342. with regard to the conventional stack-type multichip module as shown in Fig. 1, since both of the stacked semiconductor chips 310 and 320 are connected to the interconnection patterns 331 and 332 of the package in wire bonding configuration, it i9 necessary to design so that crossing and short circuit of the bonding wire are avoidable or preventable. That is, it is necessary to implement a design so as to make a pitch between the interconnection patterns and between the connection pads larger and/or to shift either one of mutually adjacent interconnection patterns outward. Such requirements on design give rise to a problem that, with regard to the conventional stack-type multichip modules, it is difficult to reduce occupied area, and difficult to heighten implementation density.
In addition, the upper semiconductor chip 320 needs to be comparatively small in its projection area for the purpose of providing bonding so that interconnection pads 311 of the lower semiconductor chip 310 are exposed, thus reduction of circuit size of upper semiconductor 320 is limited. As a result, there is a problem that it is difficult to further heighten density of stack-type multichip modules.
Moreover, the fact that the space to wire the bonding wiring is necessarily upward of the upper semiconductor chip 320 prevents conventional stacktype multichip modules from being made thinner.
SUMMARY OF THE INVENTION It is therefore an object of the preferred embodiment of the present invention to provide a multichip module which reduces occupied area.
Another object of the preferred embodiment of the present invention is to provide a multichip module with high density implementation.
Still another object of the preferred embodiments of the present invention is to provide a thinner multichip module.
A multichip module of the present invention comprises a substrate having a first interconnection pattern and a second interconnection pattern, a first semiconductor device having a first interconnection pad on a bottom surface thereof with respect to the substrate, and a second semiconductor device disposed on the first semiconductor device and havina a second interconnection pad on an upper surface thereof with respect to the substrate. In this multichip module, the first interconnection pattern is interconnected to the first interconnection pad on the bottom surface of the first semiconductor device, and the second interconnection pattern is interconnected to the second interconnection pad on the upper surface of the second semiconductor device.
Another multichip module of the present invention comprises a substrate having a first interconnection pattern and a second interconnection pattern, a first semiconductor device having a first and a second interconnection pads on an upper surface thereof with respect to the substrate, and a second semiconductor device disposed on the first semiconductor device and having a third interconnection pad on a bottom surface thereof with respect to the substrate. In this multichip module, the first interconnection pattern is interconnected to the first interconnection pad on the upper surface of said first semiconductor device, and the second interconnection pattern is interconnected to the third in. pad on the bottom surface of the second semiconductor device through the second interconnection pad on the upper surface of the first semiconductor device.
Still another multichip module of the present invention comprises a substrate having a first interconnection pattern and a second interconnection pattern, a first semiconductor device having a first interconnection pad on a bottom surface thereof with respect to the substrate, and a second semiconductor device having a second interconnection pad on an upper surface thereof with respect to the substrate.
In this multichip module, the first and second semiconductor devices are stacked on the substrate.
@ BRIEF DESCRIPTION OF THE DRAWINGS Preferred features of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which : Fig. 1 is a perspective view showing main portion of a conventional stack-type multichip module.
Fig. 2 is a perspective view showing main portion of a stack-type multichip module according to a first embodiment of the present invention.
Fig 3 is a perspective view showing interconnection patterns of a stack-type multichip module as shown in Fig. 2.
Fig. 4 is a cross section of a stack-type multichip module shown in Fig. 2.
Fig. 5 is a perspective view showing an example of a main portion of the stack-type multichip module according to the present invention.
Fig. 6 is a perspective view showing another example of a main portion of the stack-type multichip module of the present invention.
Fig. 7 is a perspective view showing main portion of a stack-type multichip module according to a second embodiment of the present invention.
Fig. 8 is a perspective view showing the lower semiconductor chip of the multichip module shown in Fig. 7.
Fig. 9 is a cross section of a stack-type multichip module as shown in Fig. 7.
Fig. 10 is a cross section showing another example of a stack-type multichip module according to a second embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, a multichip module according to preferred embodiments of the present invention will be explained.
With reference to Figs. 2, 3 and 4, the multichip module of the first embodiment of the present invention comprises stacked bottom and upper semiconductor chips 110 and 120. A package 150 houses the lower and upper semiconductor chips 110 and 120, and has upward interconnection patterns 131 and 132 on the upper surface of substrate 160 thereof. The lower semiconductor chip 110 is disposed on the substrate 160 and the upper semiconductor chip 120 is disposed on the lower semiconductor chip 110. The package 150 comprises downward interconnection pads 161 on the bottom surface of the substrate 160, and these downward interconnection pads 161 are interconnectable on an implementation substrate 170 of an electronic device in a bump configuration 171.
With regard to the lower semiconductor chip 110, its'interconnection pads 111 face downward on the bottom surface thereof. On the other hand, with regard to the upper semiconductor chip 120, its interconnection pads 121 face upward on the upper surface thereof.
With regard to the lower semiconductor chip 110, its interconnection pads 111 are interconnected to the interconnection pattern 131 in a bump configuration} wherein the bump configuration is formed by a plurality of metal balls 141 such as solder balls. On the other hand, with regard to the upper semiconductor chip 120, its interconnection pads 121 are interconnected to the interconnection pattern 132 in a wire bonding configuration using bonding wires 142 which are formed by metal wires such as gold wires.
In the present invention, as shown in Figs. 2, 3 and 4, since the downward interconnection pads 111 of the lower semiconductor chip 110 are interconnected to the interconnection pattern 131 in a bump configuration, the upper semiconductor chip 120 does not need to be comparatively small in its projection area so that interconnection pads 111 of the lower semiconductor chip are exposed as in the conventional cases.
Accordingly, as shown in Fig. 5, with regard to the upper semiconductor chip 120', its projection area with respect to the substrate 160 of the package 150 may be the same as the projection area of the lower semiconductor chip 110. Namely, the size of the upper semiconductor chip 120t may be equal to that of the lower semiconductor chip 110.
As shown in Fig. 6, with regard to the upper semiconductor chip 120", its projection area with respect to the substrate 160 of the package 150 may also be larger than the projection area of the lower semiconductor chip 110. Namely, the size of the upper semiconductor chip 120 may be larger than that of the lower semiconductor chip 110.
In these cases, as shown in Figs. 5 and 6, the wide projection area of the upper semiconductor chip makes it possible to realize a multichip module with circuit volume larger than a conventional module of the same size.
With reference to Figs. 7, 8 and 9, the multichip module according to a second embodiment of the present invention will be described. In Figs.
7, 8 and 9, the multichip module of the present invention comprises stacked lower and upper semiconductor chips 210 and 220 The lower and upper semiconductor chips 210 and 220 are housed by a package 250 having upward interconnection patterns 231 and 232 on the upper surface of a substrate 260 thereof.
With regard to the lower semiconductor chip 210, the interconnection pads 211 face upward on the upper surface thereof. On the other hand, with regard to the upper semiconductor chip 220, its interconnection pads 221 face downward on the bottom surface thereof.
With regard to the lower semiconductor chip 210, its interconnection pads 211 are interconnected to the interconnection patterns 231 and 232 in a wire bonding configuration using bonding wires 241.
On the other hand, with respect to the upper semiconductor chip 220, its interconnection pads 221 are interconnected to the interconnection pads 211, formed on the upper surface of the lower semiconductor chip 210, through interconnection pads 211a formed on the upper surface of the lower semiconductor chip 210, in a bump configuration formed by metal balls 242.
In the present invention, the interconnection pads 211a are interconnected to the interconnection pattern 232 via bonding wires 241. That is, the interconnection pads 221 of the upper semiconductor chip 220 can be indirectly interconnected to the upward interconnection pattern 232 formed on the upper surface of the substrate 260.
The lower and upper semiconductor chips 210 and 220 may be designed regarding the thickness thereof so that the height of the upper surface of the upper semiconductor chip 220 is not higher than the highest point of the bonding wires 241 as shown in Fig. 9 when the upper semiconductor chip 220 is stacked on the lower semiconductor chip 210. That enables efficient use of the space in the height direction inside the package, and consequently makes it possible to realize a further thinner-type module.
On the other hand, with respect to the bonding wires 241, their highest point may be wired to reach not higher than the upper surface of the upper semiconductor chip 220 as shown in Fig. 10.
That case also enables efficient use of the space in the height direction inside the package, and consequently makes it possible to realize a further thinner-type module.
The stack-type multichip module according to the present invention has small occupied area, lower height and high implementation density because it includes, as a plurality of semiconductor chips, the first semiconductor chip with downward interconnection pads and the second semiconductor chip with upward interconnection pads.
In particular, since in two semiconductor chips, interconnection with bonding wires is applied to one chip, no considerations to avoid crossing or short circuit oL bonding wires between the lower semiconductor chip and the upper semiconductor chip are required, in contrast to a conventional module where both the stacked semiconductor chips and interconnected with bonding wires.
In addition, in a conventional multichip module interconnecting both of the two laminated semiconductor chips with bonding wires, the sizes of the upper semiconductor chip are required to be smaller than the sizes of the lower semiconductor chip to a degree that there will be no inconveniences when bonding the lower semiconductor chip. But according to the present invention, no regulations on the size-related relationship of the two semiconductor chips size are necessary since the upper semiconductor chip and the lower semiconductor chip are also realizable even in the case where they have the same sizes, or where the upper semiconductor chip has a larger size than the lower semiconductor chip (to a degree that there are no inconveniences to bonding of the upper semiconductor chip).
Moreover, in contrast to conventional multichip \. module, the multichip module according to the present invention does not need space required for wire interconnection of the upper semiconductor chip in the conventional multichip-module. Thus, the multichip module according to the present invention can be lowered in terms of height, and the package of a multichip module can be made thin.
The invention may be embodied in other specific forms without departing from the sprit or essential characteristics thereof. The present invention embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other dislcosed and/or illustrated features.
The text of the abstract filed herewith is repeated here as part of the specification.
A multichip module according to the present invention comprises stacked semiconductor chips. A first chip has an interconnection pad on a bottom surface thereof. A second chip has an interconnection pad on an upper surface thereof. A package has first and second interconnection patterns, the first pattern being interconnected to the pad on the first chip in a bump configuration, and the second pattern being interconnected to the pad on the second chip in a wire bonding configuration.

Claims (28)

  1. CLAIMS : 1. A multichip module comprising a substrate, a first semiconductor device, and a second semiconductor device disposed on the first device, a first interconnection pattern on the substrate being connected to a first pad on a bottom surface of the first device, and a second interconnection pattern on the substrate being connected to a second pad on the upper surface of the second device.
  2. 2. A multichip module as in claim 1, wherein the first pad is connected to the first interconnection pattern in a bump configuration.
  3. 3. A multichip module as in claim 1, wherein the second pad is connected to the second interconnection pattern in a wire bonding configuration.
  4. 4. A multichip module comprising : a substrate having a first interconnection pattern and a second interconnection pattern ; a first semiconductor device having a first interconnection pad on a bottom surface thereof with respect to said substrate ; and, a second semiconductor device disposed on said first semiconductor device and having a second interconnection pad on an upper surface thereof with respect to said substrate ; wherein said first interconnection pattern is interconnected to said first interconnection pad on the bottom surface of said first semiconductor device, and said second interconnection pattern is interconnected to said second interconnection pad on the upper surface of said second semiconductor device.
  5. 5. A multichip module as in claim 4, wherein said first interconnection pattern is interconnected to said first interconnection pad on the bottom surface of said first semiconductor device in a bump configuration.
  6. 6. A multichip module as in claim 5, wherein said bump configuration is formed by a metal ball structure.
  7. 7. A multichip module as in claim 5, wherein said bump configuration is formed by a solder ball structure.
  8. 8. A multichip module as in claim 4, wherein said second interconnection pattern is interconnected to said second interconnection pad on the upper surface of said second semiconductor device in a wire bonding configuration.
  9. 9. A multichip module as in claim 8, wherein said wire bonding configuration is formed by a bonding wire structure.
  10. 10. A multichip module as in claim 4, wherein said first interconnection pattern is interconnected to said first interconnection pad on the bottom surface of said first semiconductor device in a bump configuration, and said second interconnection pattern is interconnected to said second interconnection pad on the upper surface of said second semiconductor device in a wire bonding configuration.
  11. 11. A multichip module as in claim 4, wherein a projection area with respect to said substrate of said second semiconductor device is equal to or greater than that of said first semiconductor device.
  12. 12. A multichip module as in claim 4, further comprising : a package having a portion of said substrate as a bottom thereof, for housing said first and second semiconductor devices.
  13. 13. A multichip module as claimed in claim 12, wherein said package has a downward interconncction pad on said substrate for interconnecting to an implementation substrate.
  14. 14. A multichip module comprising : a substrate having a first interconnection pattern and a second interconnection pattern ; a first semiconductor device having a first and a second interconnection pads on an upper surface thereof with respect to said substrate ; and a second semiconductor device disposed on said first semiconductor device and having a third interconnection pad on a bottom surface thereof with respect to said substrate ; wherein said first interconnection paciern is interconnected to said first interconnection pad on the upper surface of said first semiconductor device ; and said second interconnection pattern is interconnected to said third interconnection pad on the bottom surface of said second semiconductor device through said second interconnection pad on the upper surface of said first semiconductor device.
  15. 15. A multichip module as claimed in claim 14, wherein said first interconnection pattern is interconnected to said interconnection pad on the upper surface of said first semiconductor device in a wire bonding configuration.
  16. 16. A multichip module as claimed in claim 15, wherein an upper surface of said second semiconductor device has a height not higher than the highest point of said wire bonding configuration.
  17. 17. A module as claimed in claim 15, wherein the highest point of said wire bonding configuration has height lower than the upper surface of said second semiconductor device.
  18. 18. A multichip module as claimed in claim 14, wherein said third interconnection pad on the bottom surface of said second semiconductor device is interconnected to said second interconnection pad on the upper surface of said first semiconductor device in a bump configuration.
  19. 19. A multichip module as claimed in claim 18, wherein said bump configuration is formed by a metal ball structure.
  20. 20. A multichip module as claimed in claim 18, wherein said bump configuration is formed by a solder ball structure.
  21. 21. A multichip module as claimed in claim 14, wherein said first interconnection pattern is interconnected to said interconnection pad on the upper surface of said first semiconductor device in a wire bonding configuration and said thirdinterconnection pad on the bottom surface of said second semiconductor device is interconnected to said second interconnection pad on the upper surface of said first semiconductor device in a bump configuration.
  22. 22. A multichip module as claimed in claim 14, further comprising : a package having g a portion of said substrate as a bottom thereof, for housing said first and second semiconductor devices.
  23. 23. A multichip module as claimed in claim 22, wherein said package has a downward interconnection pad on said substrate for interconnecting to an implementation substrate.
  24. 24. A multichip module comprising : a substrate having a first interconnection pattern and a second interconnection pattern formed on a first surface thereof ; a first semiconductor device having a first interconnection pad on a bottom surface chereof with respect to said first surface of said substrate ; and a second semiconductor device having a second interconnection pad on an upper surface thereof with respect to said first surface of said substrate, wherein said first and second semiconductor devices are stacked on said first surface of said substrate.
  25. 25. A multichip module as claimed in claim 24, further comprising : @ a bump configuration for interconnecting said first interconnection pad to one of said second interconnection pad and said interconr. ection pattern : and a wire bonding configuration for interconnecting said second interconnection pad to said interconriection pattern.
  26. 26. A multichip module as claimed in claim 24, wherein said second semiconductor device having said second interconnection pad is-stacked on said first semiconductor device having said first interconnection pad, said first interconnection pad is interconnected to said interconnection pattern in a bump configuration, and said second interconnection pad is interconnected to said interconnection pattern in a wire bonding configuration.
  27. 27. A multichip module as in claim 24, wherein said first semiconductor device having said first interconnection pad is stacked on the second semiconductor device having said second interconnection pad, and said first interconnection pad is interconnected to said second interconnection pad using a bump configuration.
  28. 28. A multichip module substantially as herein described with reference to and as shown in Figures 2 to 10 of the accompanying drawings.
GB9928115A 1998-11-27 1999-11-26 Multichip module comprising stacked semiconductor chips Withdrawn GB2344217A (en)

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Cited By (3)

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DE10136655C1 (en) * 2001-07-20 2002-08-01 Optosys Technologies Gmbh Multichip module in COB design, in particular CompactFlash card with high storage capacity and method for producing the same
WO2002061591A1 (en) * 2001-01-31 2002-08-08 Hitachi,Ltd Data processing system and data processor
GB2416917A (en) * 2004-07-30 2006-02-08 Univ Kent Canterbury Multiple chip semiconductor device

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JP4538830B2 (en) * 2004-03-30 2010-09-08 ルネサスエレクトロニクス株式会社 Semiconductor device

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JPS61274332A (en) * 1985-05-29 1986-12-04 Toshiba Corp Semiconductor device
EP0782191A2 (en) * 1995-12-28 1997-07-02 Lucent Technologies Inc. Multi-level stacked integrated-circuit-chip assembly
WO1997037374A2 (en) * 1996-03-26 1997-10-09 Advanced Micro Devices, Inc. Method of packaging multiple integrated circuit chips in a standard semiconductor device package

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JPS61274332A (en) * 1985-05-29 1986-12-04 Toshiba Corp Semiconductor device
EP0782191A2 (en) * 1995-12-28 1997-07-02 Lucent Technologies Inc. Multi-level stacked integrated-circuit-chip assembly
WO1997037374A2 (en) * 1996-03-26 1997-10-09 Advanced Micro Devices, Inc. Method of packaging multiple integrated circuit chips in a standard semiconductor device package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002061591A1 (en) * 2001-01-31 2002-08-08 Hitachi,Ltd Data processing system and data processor
DE10136655C1 (en) * 2001-07-20 2002-08-01 Optosys Technologies Gmbh Multichip module in COB design, in particular CompactFlash card with high storage capacity and method for producing the same
GB2416917A (en) * 2004-07-30 2006-02-08 Univ Kent Canterbury Multiple chip semiconductor device

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JP2000164796A (en) 2000-06-16

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