GB2341023A

GB2341023A - High-speed switching circuit

Info

Publication number: GB2341023A
Application number: GB9927189A
Authority: GB
Inventors: Toshiro Takahashi; Shoji Niki; Takao Sakurai; Takayuki Nakajima
Original assignee: Advantest Corp
Current assignee: Advantest Corp
Priority date: 1998-03-18
Filing date: 1999-11-18
Publication date: 2000-03-01
Also published as: KR20010012438A; DE19980645T1; WO1999048215A1; JPH11266149A; GB9927189D0

Abstract

A high-speed switching circuit which operates at speed exceeding 20 GHz. High-speed light-activated switches (PSW1, PSW2) controlled by light are connected with a plurality of input terminals (D<SB>in1</SB>, D<SB>in2</SB>), and their outputs are connected commonly with one output terminal (D<SB>out</SB>). Alternatively, the high-speed switches (PSW1, PSW2) are connected commonly with one input terminal (D<SB>in</SB>), and their outputs are connected with the output terminals (D<SB>out1</SB>, D<SB>out2</SB>), respectively. Multiphase pulses are supplied to the same number of light-emitting elements (LD<SB>1</SB>, LD<SB>2</SB>) as the high-speed switches so that they sequentially emit light while the corresponding high-speed switches sequentially turn on. As a result, signals from a plurality of input terminals produce a single high-speed output signal at the input frequency multiplied by the number of switches at a common output terminal, or otherwise a high-speed signal to a common input terminal produces a plurality of low-speed output signals at the input frequency divided by the number of switches at a plurality of output terminals.

Description

2341023 HIGH-SPEED SWITCHING CIRCUIT

TECHNICAL FIELD

The present invention relates to a high-speed switching circuit that is suitable for use in an electronic device, apparatus, instrument or the like which requires a high-speed operation.

BACKGROUND AR

As a technology for writing a high-speed or high-rate signal in, for example, a memory operating at low speed or rate, there is, heretofore, a technique called interleaved method in this technical field, in which a plurality of memories are connected in parallel and data are sequentially written in these memories.

By way of example, there are some of conventional memory testing apparatus each for testing a semiconductor memory such as an IC memory (a memory constructed by a semiconductor integrated circuit) and provided with a failure analysis memory using a dynamic type RAM (DRAM) which operates at low speed. In such conventional memory testing apparatus, the interleaved method is applied to the failure analysismemory in order to write a high-rate signal in suc. h a low-speed memory.

In the case that the interleaved method is applied to a memory, there are prepared a plurality of memory blocks the storage capacities of which are usually same with one another (the memory block is also called bank) and the number of which is equal to the number of interleaves (parallel processing), and these memory blocks are sequentially operated at their timings shifted little by little in block by block basis. As a result, these memories become faster in the operating speed as a whole.

Fig. 12 is a block diagram showing an example of the failure analysis memory of the conventional memory testing apparatus, to which the interleaved method is applied, the failure analysis memory using a DRAM and hence operating at low speed. There are provided in the failure analysis memory FM a switching circuit MP and a plurality of (N) memory blocks BKI, BK2, BK3, - - -, BKN (where N is an integer equal to or greater than 2) to be interleaved. A failure data outputted from a logical comparator (not shown) and an address signal ADR outputted from a pattern generator (not shown) are inputted to the switching circuit MP. The failure data is outputted from the logical comparator (not shown) when a response signal read out from a memory under test does not coincide with an expected value signal supplied from the pattern generator. The switching circuit MP sequentially switches over the memory blocks BKI BKN, each time a failure data is inputted thereto, to supply the failure data to the corresponding memory block. The failure data is distributed in regular sequence to an address of corresponding one of the plurality of memory blocks BKI, BK2, BK3, - - -, BKN specified by the address signal ADR and is stored therein.

Fig. 13 shows an interleaved operation of the failure analysis memory FM in the case that the number of interleaves is 4, and accordingly, four memory blocks are provided. As can be easily understood from Fig. 13, a high-speed signal shown in Fig.

13A is switched and stored in regular sequence in the four memory blocks BK1 - BK4 shown in Figs. 13B - 13E, respectively. Therefore, each of the memory blocks BK1 - BK4 may operate at a speed of 1/4 of the operating speed of the memory under test. For example, in the case that each of the four memory blocks operates in the cycle of 100 ns (nano seconds), if these memory blocks are operated at their timings shifted 25 ns by 25 ns, they are equivalent to a memory operating in the cycle of 25 ns as a whole.

In this manner, by using a memory operating at low speed and operating the memory in an interleaved operation, writing and reading operations of a high-speed data are eventually made possible.

Incidentally, a switching circuit for switching a high speed signal generally distributes the high-speed signal, by switching operations of N (N is an integer equal to or greater than 2) switching elements the number of which is equal to the number of interleaves, to N channel data the number of.which is equal to the' number of interleaves, thereby to decrease the repetitive rate of each of these data distributed to the N channels to 11N.

On the contrary, there is also a conventional technique for converting data read out in regular sequence from N memories each operating at low speed into a high-speed signal having a speed of N times the speed of each memory by switching operations of N switching elements to transmit the high-speed signal.

Furthermore, in each of various kinds of electronic devices, apparatus, instruments or the like, there is often used not only a memory but also a logical signal generator for selectively taking out a voltage from a plurality of voltage sources by switching elements the number of which is the same as the number of the voltage sources and generating an arbitrary logical signal constituted by a logical L (logical low level) voltage and a logical H (logical high level) voltage.

However, in any one of the aforesaid cases, an electric switching element such as an FET (field effect transistor) has been conventionally used as each of the switching elements. In general, the operating speed of an electric switching element is on the order of 10 to 20 GHz at the most even in electric switching elements categorized in the class of the highest operating speed.

From now on, IC elements, various kinds of devices and is the like are desired to have their operating speeds increased more and more, and if the operating speed of a switching element is on the order of 20 GHz at the maximum, it is certain that such switching element cannot cope with the operating speeds of such elements or devices.

In addition, there is a tendency that an electric switching element capable of operating at high-speed becomes low in its withstand voltage characteristic in inverse proportion to its operating speed. Accordingly, if it is intended to generate a high-speed logical signal, there will occur a problem that a logical signal having a large amplitude value cannot be generated.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a high speed switching circuit which is operable even at high-speed of such as over 20 GHz.

It is another object of the present invention to provide a high-speed switching circuit which is capable of generating a logical signal having a large amplitude value.

In order to accomplish the above objects, in a first aspect of the present invention, there is provided a high-speed switching circuit which comprises: a plurality of input terminals; a plurality of switching elements controlled in their on/off states by light, and connected to the plurality of input terminals, respectively; and an output terminal connected in common to the output sides of the plurality of switching elements, and wherein the plurality of switching elements are sequentially controlled in their on/off states by light, thereby to output signals supplied to the plurality of input terminals in regular sequence to the common output terminal.

In a second aspect of the present invention, there is provided a high-speed switching circuit which comprises: an input terminal; a plurality of switching elements controlle in their on/off states by light, and connected in common to the input terminal; and a plurality of output terminals connected to the output sides of the plurality of switching elements, respectively, and wherein the plurality of switching elements are sequentially controlled in their on/off states by light, thereby to output a signal supplied to the common input terminal to corresponding one of the plurality of output terminals.

In a preferred embodiment, each of the aforesaid plurality of output terminals has a capacitance element connected thereto.

In a third embodiment of the present invention, there is provided a high-speed switching circuit which comprises: a plurality of input terminals; a plurality of switching elements controlled in their on/off states by light, and connected to the plurality of input terminals, respectively; an output terminal connected in common to the output sides of the plurality of switching elements, and a plurality of voltage applying means for applying predetermined voltages to the plurality of input terminals, respectively, and wherein the plurality of switching elements are sequentially controlled in their on/off states by light, thereby to output logical signals having voltages respectively supplied to the plurality of input terminals in is regular sequence to the common output terminal.

In a preferred embodiment, voltages different from one another are supplied to the aforesaid plurality of input terminals, respectively, from the aforesaid plurality of voltage applying means. In addition, each of the plurality of voltage applying means is a voltage variable type direct current voltage source.

In addition, the high-speed switching circuit in the aforesaid first through third aspects further includes: a plurality of light-emitting elements placed adjacent to the plurality of switching elements, respectively; and a multi-phase pulse generator for generating multi-phase pulses, and the multi-phase pulses generated from the multi-phase pulse generator are supplied to the plurality of light-emitting elements respectively, thereby to radiate lights from these light-emitting elements in regular sequence, and the plurality of switching elements are sequentially turned on by these lights radiated in regular sequence.

As the plurality of switching elements, either of photoconductors or phototransistors may be used.

All of the aforesaid switching circuits use a switching element which is operable at high speed exceeding 20 GHz and controlled in its on/off state by light. Therefore, the high-speed switching circuit of the present invention can operate at high speed much faster than the conventional signal switching circuit using an electric switching element which is controlled by an electric signal. Consequently, even if IC elements, various kinds of devices and the like each having its operating speed increased more and more appear from now on, there can be provided an extremely high-speed switching circuit which sufficiently copes with such high-speed elements or devices.

In addition, in the case of a switching element whose on/off state is controlled by light, it is easy to obtain a switching element having a higher withstand voltage characteristic.

Therefore, according to the high-speed switching circuit of the present invention, there can be obtained an advantage that not only the operating speed can be made faster but also a logical signal having a large amplitude value can be generated.

BRIEF DESCRIPEON OF THE DRAWINGS Fig. 1 is a schematic circuit diagram showing a first embodiment of the high-speed switching circuit according to the present invention; Fig. 2 is a timing chart for explaining the operation of the high-speed switching circuit shown in Fig. 1; Fig. 3 is a schematic circuit diagram showing a modified embodiment of the high-speed switching circuit shown in Fig. 1; Fig. 4 is a timing chart for explaining the operation of the high-speed switching circuit shown in Fig. 3; Fig. 5 is a schematic circuit diagram showing a second embodiment of the high-speed switching circuit according to the present invention; Fig. 6 is a timing chart for explaining the operation of the high-speed switching circuit shown in Fig. 5; Fig. 7 is a schematic circuit diagram showing a modified embodiment of the high-speed switching circuit shown in Fig. 5; Fig. 8 is a timing chart for explaining the operation of the high-speed switching circuit shown in Fig. 7; Fig. 9 is a schematic circuit diagram showing a third embodiment of the high-speed switching circuit according to the present invention; Fig. 10 is a schematic circuit diagram showing a modified embodiment of the high-speed switching circuit shown in Fig. 9; Fig. 11 is a timing chart for explaining the operation of the high-speed switching circuit shown in Fig. 9; Fig. 12 is a block diagram showing an example of the conventional failure analysis memory having an interleaved structure used in an IC testing apparatus; and Fig. 13 is a timing chart for explaining the operation of the failure analysis memory shown in Fig. 12 BEST MODES FQR CARRYING OUT THE INVENTION Now, the present invention will be described in regard to the preferred embodiments thereof in detail with reference to Figs. 1 to 11.

Fig. 1 is a schematic circuit diagram showing an outline of the first embodiment of the high-speed switching circuit according to the present invention. The illustrated high-speed switching circuit includes a first switching element PSWI which is controlled in its on/off state by light and is connected in series with a first input terminal Di,1, and a second switching element PSW2 which is controlled in its on/off state similarly by light and is connected in series with a second input terminal Din2. The output sides of these switching elements PSWI and PSW2 are connected in common to an output terminal D.,, In this embodiment, a first light-emitting element LDI and a second light-emitting element LD2 are alternately driven by multi-phase (two-phase) pulses PC1 and PC2 shown in Fig. 2B outputted from a multi-phase pulse generator CC. As illustrated, each of the first and the second light-emitting elements LDI and LD2 is placed adjacent to corresponding one of the switching elements PSWI and PSW2 so that the first and the second light emitting elements LDI and LD2 can supply the emitted lights to the switching elements PSWI and PSW2, respectively.

Accordingly, each of the switching elements PSWI and PSW2 is in on state during the time interval that the corresponding one of the light-emitting elements LDI and LD2 is in on state, and they output data DAT-1 and DAT-2 supplied to the input terminals Di,11 and Din2 respectively to the output terminal D,,,,t.

As the light-emitting elements LD, and LD2.laser diodes having quick response speed, for example, can be used. In addition, as the switching elements PSW1 and PSW2, photoconductors (photoconductive elements) POC having quick response speed, for example, can be used. In the embodiment shown in Fig. 1, two photoconductors POC are connected in inversely parallel connection so as to use them as a bidirectional conductive switching element. However, the switching elements are not limited to the photoconductors, and other high-speed switching elements may also be used.

By inputting the first and the second data DAT-1 and DAT-2 shown in Fig. 2C to the first and the second input terminals D,,,, and Din2, respectively, and generating, based on a driving signal PC shown in Fig. 2A supplied to the input terminal Ci,, of the multi-phase pulse generator CC, multi-phase pulses PC1 and PC2 which are different in their phases by 180' from each other as shown in Fig. 2B from the multiphase pulse generator CC, thereby to alternately control the first and the second switching elements PSW1 and PSW2 to turn on/off, a high-speed signal PHI constituted by the first half cycle of the first data DAT-1 and the second or latter half cycle of the second data DAT-2 is outputted to the output terminal D,,,,, as shown in Fig. 2D.

In the case that the photoconductors POC are used as the first and the second switching elements PSW1 and PSW2 respectively, these switching elements PSW1 and PSW1 are operable at a speed up to on the order of 70 to 80 GHz. As a result, there is provided a switching circuit that can operate at extremely high-speed.

By way of example, when a driving signal PC having 80 GHz frequency as shown in Fig. 2A is inputted to the input terminal Cin of the multi-phase pulse generator CC, thereby to generate from the multi-phase pulse generator CC multi-phase pulses PC 1 and PC2 having their phases shifted by 180' from each other as shown in Fig. 2B, that is, multi-phase pulses PC1 and PC2 having a relationship that the second pulse PC2 is delayed by half cycle from the first pulse PC1, and the first and the second light-emitting elements LD, and LD2 are operated by a frequency of 40 GHz which is half of the frequency of the driving signal PC, a high-speed signal PHI having a frequency of 90 GHz which is twice 40 GHz can be outputted to the output terminal Dout, As the switching elements PSW1 and PSW2 controlled in their on/off states by light, in addition to the aforementioned photoconductors, photo-couplers each being constituted by a combination of a laser diode and a phototransistor can be used.

Fig. 3 shows a modified embodiment of the high-speed switching circuit of the first embodiment shown in Fig. 1, in which switching elements PSW1, PSW2, PSW3 and PSW4 each controlled in its on/off state by light are connected to four input terminals Dj.1, Din2) Din3 and Din4, respectively, in series with one another in the correspondence of one to one, and the output sides of these switching elements are connected in common to an output terminal Dou, In this case, based on the driving signal PC shown in Fig. 4A supplied to the input terminal Cin of the multi phase pulse generator CC, multi-phase (four-phase) pulses PC1 to PC4 shown in Fig. 4B are generated from the multi-phase pulse generator CC, thereby to drive the first through the fourth light-emitting elements LD,-LD4 in regular sequence.

As illustrated, each of the first through the fourth light emitting elements LDI-LD4 is placed adjacent to corresponding one of the switching elements PSWI to PSW4 so that the first through the fourth light-emitting elements LD, to LD4 can supply their emitted lights to the switching elements PSWI- PSW4, respectively. Accordingly, each of the switching elements PSW1 to PSW4 is in on state during the time interval that the corresponding one of the light-emitting elements LDI to LD4 'S in on state, and they output data DAT-1 to DAT-4 supplied to the input terminals Dinl to Din4 respectively to the output terminal Dout, is In this manner, when the four switching elements PSWI to PSW4 are controlled in their on/off states by the multi-Phase (four-phase) pulses PCI to PC4 shown in Fig. 4B each having its period of twice the period of the driving signal PC shown in Fig.

4A and sequentially delayed in their phases by 1/2 of the period of the driving signal PC, the switching speed of each of the switching elements PSWI to PSW4 becomes 1/4 of the speed of the driving signal PC shown in Fig. 4A. Consequently, as shown in Fig. 4C, it is sufficient that input data DAT-1 to DAT-4 each having its rate of 1/4 of the speed of the driving signal PC (input M data each having its period of two times the period of the driving signal PC) may be supplied to the input terminals Dinl to Din4) respectively. I - On the other hand, the speed of the high-speed signal PHI outputted to the output terminal D,.t becomes, as shown in Fig.

4D, four times the speed of the input data DAT- I to DAT-4.

Accordingly, in the case that it is desired to obtain a high-speed signal PHI having, for example, a frequency of 80 GHz, the repetitive rate of each of the multi-phase pulses PCI to PC4 may be 20 GHz which is 1/4 of the speed of the signal PHI to be obtained. In addition, if the repetitive rate of each of the multi phase pulses PC 1 to PC4 is set, for example, to 40 GHz, it is possible to output to the output terminal Do,,, a high-speed signal PHI having 160 GHz which is four times the repetitive rate of the multi-phase pulses.

Fig. 5 is a schematic circuit diagram showing the second embodiment of the high-speed switching circuit according to the present invention, and shows a case in which the present invention is applied to a high-speed switching circuit for converting a high-speed signal PHI into two low-speed signals DAT-1 and DAT-2. In this second embodiment, the switching circuit is constructed such that the first and the second switching elements PSW1 and PSW2 each,controlled in its on/off state by light are connected in common to an input terminal Di, to which a high-speed signal PHI shown in Fig. 6C is supplied, the output sides of these switching elements PSWI and PSW2 are connected to output terminals D.,,,, and Dout2, respectively, and the switching elements PSWI and PSW2 are alternately controlled in their on/off states at the period of the high-speed signal PHI by the first and the second light-emitting elements LD, and LD2 each placed adjacent to corresponding one of the first and the second switching elements PSW1 and PSW2, respectively.

The first and the second light-emitting elements LD, and LD2 are alternately controlled in their on/off states by the multi phase pulses PC1 and PC2 shown in Fig. 6B generated from the multi-phase pulse generator CC based on the driving signal PC shown in Fig. 6A having its period of twice that of the high speed signal PHI, respectively. Since the phases of the multi phase pulses PC1 and PC2 are shifted by 180' from each other, the first and the second light-emitting elements LD, and LD2 are alternately turned on at the period of the high-speed signal PHI, and supply the emitted lights to the first and the second switching elements PSW1 and PSW2, respectively. Accordingly, each of the switchin'g elements PSW1 and PSW2 is in on state during the time interval that the corresponding one of the light emitting elements LD, and LD2 'S in on state, and alternately output the high-speed signal PHI shown in Fig. 6C supplied to the input terminal Di,, to the respective output terminals D,,,,,, and Dout2 In this embodiment, the circuit is constructed such that capacitance elements, for example, capacitors Cl and C2 are connected to the output terminals D,,ut, and Do.,2, respectively, and even if the first and the second switching elements PSW1 and PSW2 are turned off, the logical values outputted to the output terminals D.ut, and Dout2 at the time that these switching elements have been turned on are stored in these capacitors Cl and C2, respectively, so that the outputs of the output terminals and Dout2 are maintained. As a result, even if each of the switching elements PSW1 and PSW2 is turned off, the logical values A, C, E, - - - and B, D, F, - - - of the high-speed signal PHI already stored in the capacitors C I and C2 continue to be outputted to the output terminals D,,,,,, and DOut2) respectively, until the time that these switching elements are turned on next.

Therefore, the low-speed signals DAT-1 and DAT-2 shown in Fig.

6D each having its period of two times that of the high-speed signal PHI are outputted to the output terminals Dout, and Dout2 respectively. Consequently, each of the low-speed signals DAT I and DAT-2 has its speed which is 1/2 of the speed of the inputted high-speed signal PHI.

Fig. 7 shows a modified embodiment in which the present invention is applied to a high-speed switching circuit for converting a high-speed signal PHI into four low-speed signals DAT-1 to DAT-4. That is, the high-speed switching circuit shown in Fig. 5 is expanded to a four-phase system. In this modified embodiment, the switching circuit is constructed such that the first through the fourth switching elements PSWI, PSW2, PSW3 and PSW4 each controlled in its on/off state by light are connected in common to an input terminal Di,, to which the high speed signal PHI shown in Fig. 8A is supplied, the output sides of these switching elements PSWI to PSW4 are connected to output terminals Doutl) Dout2l D,,,, t, a n d DoutO respectively, nd the switching elements PSWl to PSW4 are sequentially controlled in their on/off states at the period of the high-speed signal PHI by the first through the fourth light-emitting elements C) LD, to LD4 each placed adjacent to corresponding one of the first through the fourth switching elements PSWl to PSW4, respectively.

The first through the fourth light-emitting elements LDI to LD4 are sequentially controlled in their on/off states at the period of the high-speed signal PHI by the multi-phase (four phase) pulses PCI to PC4 shown in Fig. 8B generated from the multi-phase pulse generator CC based on the driving signal PC having its period of twice that of the high-speed signal PHI, respectively. Since the multi-phase pulses PC1 to PC4 are delayed by the period of the high-speed signal PHI in regular sequence from one another, the first through the fourth light emitting elements LD, and LD2 are sequentially turned on at the period of four times that of the high-speed signal PHI, and supply the emitted lights to the first through the fourth switching elements PSW1 to PSW4, respectively. Accordingly, each of the switching elements PSWI to PSW4 is in on state during the time interval that corresponding one of the light-emitting elements LD, to LD4 is in on state, and they output the high-speed signal PHI shown in Fig. 8A supplied to the input terminal Di,, to the respective output terminals D,,,,,, to Dout4 in regular sequence.

In this embodiment, too, the circuit is constructed such that capacitors C1 to C4 are connected to the output terminals D,,ut, to Dout4, respectively, and even if the first through the fourth switching elements PSWI to PSW4 are turned off, the logical values outputted to the output terminals D,,u,l to Dout4 at the time that these switching elements have been turned on are stored in these capacitors Cl to C4, respectively, so that the outputs of the output terminals D,,,,,, to Dout4 are maintained. As a result, even if each of the switching elements PSWI to PSW4 is turned off, the logical values A, E, 1, M, - - -, B, F, J, N, - - -, C, G, K, OF, - - - and D, H, L, P, - - - of the high-speed signal PHI already stored in the capacitors Cl to C4 continue to be outputted to the output terminals D,,,,tl, Dout2) DouO and DoutO respectively, until the time that these switching elements are turned on next. Therefore, the low-speed signals DAT-1 to DAT 4 shown in Fig. 8C each having its period of four times that of the high-speed signal PHI are outputted to the output terminals D,,ut, to Dout4 respectively. Consequently, each of the low-speed signals DAT-1 to DAT-4 has its speed which is 1/4 of the speed of the inputted high-speed signal PHI.

For example, in the case that a high-speed signal PHI having 80 GHz frequency is inputted to the input terminal Dj, the repetitive rate of each of the multi-phase pulses PCI to PC4 may be 20 GHz which is 1/4 of the speed of the high-speed signal PHI, and the low-speed signals DAT-1 to DAT4 each having its speed of 20 GHz which is 1/4 of that of the high-speed signal PHI are outputted to the output terminals D,,,,tl to DoutO respectively. In addition, if the repetitive rate of each of the multi-phase pulses PC1 to PC4 is set, for example, to 40 GHz, a high-speed signal PHI having its speed of 160 GHz which is four times the repetitive rate of the multi-phase pulses PC1 to PC4 can be inputted to the input terminal Dj, Fig. 9 is a schematic circuit diagram showing a high-speed switching circuit of the third embodiment in which the present invention is applied to a logical signal generator that can operate at high-speed, is capable of setting voltage values of logical H and logical L to arbitrary voltages, and is able to set the voltage values to be set to much higher voltage values. The illustrated high-speed switching circuit includes a first switching element PSW1 controlled in its on/off state by light and connected in series with a first input terminal Din, to which a first voltage variable type direct current voltage source El is connected, and a second switching element PSW2 controlled in its on/off state by light and connected in series with a second input terminal Din2 to which a second voltage variable type direct current voltage source E2 is connected, and the output sides of these switching elements PSWl and PSW2 are connected in common to an output terminal Dout, In this embodiment, a first and a second two light-emitting elements LDI and LD2 are alternately driven by multi-phase (two-phase) p'ulses having their phases shifted by 180' from each other and outputted from a multi-phase pulse generator CC. As shown, each of the first and the second light-emitting elements is LD,and LD2 is placed adjacent to corresponding one of the first and the second switching elements PSW1 and PSW2 so that the first and the second light-emitting elements LDI and LD2 can supply the emitted lights to the switching elements PSWI and PSW2, respectively. Therefore, each of the switching elements PSWI and PSW2 is in on state during the time interval that the corresponding one of the light-emitting elements LD, and LD2 is in on state, and they alternately output the voltages El and E2 inputted to the input terminals Din, and Din2, respectively, to the output terminal Dout, That is, in this embodiment, the switching circuit is constructed such that the variable type direct current voltage sources El and E2 are connected to the first and the second input terminals Din, and Din2 respectively, to apply direct current voltages VI and V2 to the first and the second input terminals Di,,, and Din2, respectively, and in this condition, the first and the second switching elements PSW1 and PSW2 are alternately turned on and off, thereby to alternately output the voltages V1 and V2 to the output terminal D,,,,t.

By setting the voltages V1 and V2 to, for example, Vl>V2, it is possible to output to the output terminal D,,,,t as a logical signal having the voltage V2 as logical L and the voltage V1 as logical H. In this case, if the aforementioned photoconductors are used as the switching elements PSW1 and PSW2, the amplitude values of the voltages V1 and V2 can be set to on the order of several volts, and hence each of the amplitudes of the voltages V1 and V2 can be set to a value of a several times the amplitude of a logical signal outputted by the conventional high speed logical signal generator.

Further, since the driving signal to be inputted to the multi-phase pulse generator CC and the multi-phase (two phase) pulses having their phases shifted by 180' from each other outputted from the multi-phase pulse generator CC may be the same as the driving signal PC and the multi-phase pulses PCI and PC2 shown in Fig. 2, respectively, they are not shown here.

Fig. 10 is a schematic circuit diagram showing a modified embodiment in which the logical signal generator shown in Fig.

9 is expanded so as to operate in four-phase system. In this case, variable type direct current voltage sources El to E4 are connected to four input terminals Din, to DinO respectively, switching elements PSWI to PSW4 each controlled in its on/off state by light are connected in series with the input terminals Di,,, to Din4, respectively, and the output sides of these switching elements PSWI to PSW4 are connected in common to an output terminal Dout, In addition, multi-phase (four-phase) pulses PCI to PC4 sequentially delayed by 1/2 of the period of the driving signal PC from one annother are generated from the multi-phase pulse generator CC, and the first through the fourth light emitting elements LDI to LD4 each placed adjacent to corresponding one of the switching elements PSWl to PSW4 are driven in regular sequence by the multi-phase pulses PC 1 to PC4, ic respectively.

By such operation, each of the switching elements PSWI to PSW4 is in on state during the time interval that the corresponding one of the light-emitting elements LDI to LD4 is in on state, and they output the voltages El to E4 applied to the input terminals Dinl to Din4, respectively, to the output terminal Dout in regular sequence.

When the high-speed switching circuit thus constructed is used, if the voltages Vl to V4 of the respective direct current voltage sources El to E4 are selected to be Vl<V2<V3<V4, a stepwise wave can be generated as shown in Fig. 1 IA. In addition, if the voltages Vl to V4 of the respective direct Current voltage sources E I to E4 are selected to be V I <V2=V4<V3, a logical signal having three logical values can be generated as I.1-D shown in Fig. 11 B. Further, since the driving signal to be inputted to the multi-phase pulse generator CC and the multi-phase (four-phase) pulses outputted from the multi-phase pulse generator CC may be the same as the driving signal PC and the multi-phase pulses PC I to PC4 shown in Fig. 4, respectively, they are not shown here.

In the aforesaid embodiments, the explanation was given by showing, by way of example, the high-speed switching circuit in which two switching elements are used and the high-speed switching circuit in which four switching elements are used.

However, the present invention can equally be applied to all of the high-speed switching circuits each using two or more switching elements. Accordingly, it could easily be understood that the number of switching elements may be two or greater than two and is not limited to any one of the numbers shown in the illustrated embodiments. In addition, it is needless to say that the high-speed switching circuit according to the present invention can suitably be used not only in an IC testing apparatus but also in various kinds of electronic devices, apparatus, instruments and the like each requiring a high-speed operation.

As is apparent from the foregoing description, according to the present invention, since a plurality of switching elements each of which is turned on/off by light are used in the high-speed switching circuit, a high-speed operation exceeding 20 GHz is made possible, and an extremely high-speed operation can be performed as compared with the conventional switchin g circuit using electric switching elements. Therefore, there is an ' advantage that even if IC elements, various kinds of devices-and the like the operating speed of which is greatly increased more and more appear from now on, the switching circuit can cope with these IC elements and devices.

Accordingly, there is obtained an advantage that not only the operating speed can be made faster but also a logical signal having a large amplitude value can be generated.

While the present invention has been described with regard to the preferred some embodiments shown by way of example, it will be apparent to those skilled in the art that various modifications, alterations, changes, and/or minor improvements of the embodiments described above can be made without departing from the spirit and the scope of the present invention. Accordingly, it should be understood that the present invention is not limited to the illustrated embodiments, and is intended to encompass all such modifications, alterations, changes, and/or minor improvements falling within the scope of the invention defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A high-speed switching circuit comprising: a plurality of input terminals; a plurality of switching elements controlled in their on/off states by light, and connected to said plurality of input terminals, respectively; and an output terminal connected in common to the output sides of said plurality of switching elements, and wherein said plurality of switching elements are sequentially controlled in their on/off states by light, thereby to output signals supplied to said plurality of input terminals in regular sequence to said common output terminal.

2. A high-speed switching circuit comprising: an input terminal; a plurality of switching elements controlled in their on/off states by light, and connected in common to said input terminal; and a plurality of output terminals connected to the output sides of said plurality of switching elements, respectively, and wherein said plurality of switching elements are sequentially controlled in their on/off states by light, thereby to output a signal supplied to said common input terminal to corresponding one of said plurality of output terminals.

3. A high-speed switching circuit comprising: a plurality of input terminals; a plurality of switching elements controlled in their on/off states by light, and connected to said plurality of input terminals, respectively; an output terminal connected in common to the output sides of said plurality of switching elements, and a plurality of voltage applying means for applying predetermined voltages to said plurality of input terminals, respectively, and wherein said plurality of switching elements are sequentially controlled in their on/off states by light, thereby to output logical signals having voltages respectively supplied to said plurality of input terminals in regular sequence to said common output terminal.

4. The high-speed switching circuit as set forth in claim 2, further including a plurality of capacitance elements connected to said plurality of output terminals, respectively.

5. The high-speed switching circuit as set forth in claim 3, wherein voltages different from one another are supplied to said plurality of input terminals, respectively, from said plurality of voltage applying means.

6. The high-speed switching circuit as set forth in claim 3, wherein each of said plurality of voltage applying means is a voltage variable type direct current voltage source.

7. The high-speed switching circuit as set forth in any one 4-.) of claims 1 to 4, further including: a plurality of light-emitting elements placed adjacent to said plurality of switching elements, respectively; and a multi-phase pulse generator for generating multi- phase pulses, and wherein the multi-phase pulses generated from said multiphase pulse generator are supplied to said plurality of lightemitting elements respectively, thereby to radiate lights from these light-emitting elements in regular sequence, and said plurality of switching elements are sequentially turned on by these lights radiated in regular sequence.

8. The high-speed switching circuit as set forth in any one of claims 1 to 4, wherein said plurality of switching elements are photoconductors, respectively.

9. The high-speed switching circuit as set forth in any one of claims 1 to 4, wherein said plurality of switching elements are phototransistors, respectively.