JP2008123358A - Switch matrix circuit and scanning method for it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-dimensional matrix for reducing the number of signal lines. <P>SOLUTION: A matrix part 10 of this switch matrix circuit 1 is provided with a first common line group of a plurality of systems, each of which has a plurality of first common lines COM1A-COM3A and COM1B-COM3B, a plurality of second common lines 28 individually connected to any one of the first common lines COM1A and COM1B in the first common line group of the respective systems, a plurality of switch circuits 18, 20, and 22 individually connected to any of the second common lines, and output lines OUT1-OUT3 individually connected to any one of a plurality of switch circuits respectively connected to the second common lines. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a switch matrix circuit using a diode and a scanning method of the switch matrix circuit.

  2. Description of the Related Art Conventionally, there is known a switch matrix circuit that includes a switch matrix unit composed of a plurality of commons and a plurality of outputs, and scans the states of the plurality of switches in a time division manner. For example, for 16 switches, a 4 × 4 matrix is formed by four common lines and four output lines.

  FIG. 11 is a diagram illustrating an example of a conventional switch matrix circuit. In this example, it is a 2 × 2 matrix composed of two common lines and two output lines, and four switches can be scanned. As shown in FIG. 11, each of the common lines (COM1, COM2) is provided with a buffer (for example, see 100) that receives a common signal from a control circuit such as a CPU. Between the common line and the output lines (OUT1, OUT2), a switch circuit (see reference numerals 101 to 104) including a diode and a switch is disposed. One of the output lines is connected to a power supply by a pull-up resistor, and the other output line is output to the control circuit via a buffer (for example, reference numeral 105).

  FIG. 12 is a timing chart of signals on the common line of the switch matrix circuit shown in FIG. In FIG. 12, when each of the common lines COM1 and COM2 is at a low level, the control circuit takes in the signal of the output line at the last timing (timing indicated by a broken line). For example, at a timing when COM1 is at a low level (see broken line 110), signals indicating the states (ON / OFF) of the switch circuits 101 and 102 can be acquired from COM1 and COM2, respectively. Similarly, at a timing when COM2 is at a low level (see the broken line 111), signals indicating the states of the switches 103 and 104 can be acquired from COM1 and COM2, respectively.

In such a switch matrix circuit, for example, as described in Patent Document 1, the signal line constituting the matrix is either a common line or an output line, thereby shortening the reading of the state of the key switch. Technology has also been proposed.
JP-A-5-165559

  In the conventional switch matrix circuit, since the number of common lines × the number of output lines = the number of switches, the number of common lines and output lines becomes very large as the number of switches increases. There is a problem. For example, in a switch matrix circuit including 100 switches, at least 20 signal lines (number of common lines = 10, number of output lines = 10) are required, and an LSI used as a control circuit. When directly connecting the switch matrix circuit to the switch matrix circuit, it is necessary to prepare LSI terminals as many as the number of signal lines, which is a cause of increasing the number of LSI terminals.

  An object of the present invention is to provide a switch matrix circuit in which the number of signal lines is reduced by making the matrix multidimensional and a scanning method thereof.

An object of the present invention is to provide a plurality of first common line groups each having a plurality of first common lines;
A plurality of second common lines each connected to any one of the first common line groups of each system;
A plurality of switch circuits each connected to any one of the second common lines;
This is achieved by a switch matrix circuit comprising an output line connected to any one of a plurality of switch circuits connected to each second common line.

  In a preferred embodiment, any one of the first common line groups of the respective systems is capable of flowing a current only in a direction toward the second common line. Connected through.

In a preferred embodiment, in the first common line group of the plurality of systems, the first common line of the first system, the second system,..., And the nth system are M ₁ and M ₂ , respectively. , ..., there the _{M n,} the output line is, there the I, the switching _{circuit, M 1 × M 2 × ···} × M n × certain number I.

  In another preferred embodiment, any one first common of the first common line group of each system is sequentially activated so that any one of the plurality of second common lines is sequentially activated. A control circuit is provided that provides a signal to activate the line.

In another preferred embodiment, one end of each of the second common lines is connected to a grounded pull-down resistor,
One end of each of the output lines is connected to a pull-up resistor connected to a constant voltage source, and a voltage is applied to each of the output lines to the other end that is an output end of each of the output lines. The precharge buffer is provided.

  In a more preferred embodiment, any one of the first common line groups of each of the systems is set to be activated by sequentially setting any one of the plurality of second common lines to a low level. A control circuit for setting one first common line to a low level, and the control circuit prior to setting any one of the first common lines of each system to a low level; Thus, the precharge buffer is controlled to apply a voltage from the output precharge buffer to each of the output lines for a predetermined period.

Further, an object of the present invention is to provide a plurality of first common line groups each having a plurality of first common lines;
A plurality of second common lines each connected to any one of the first common line groups of each system;
A plurality of switch circuits each connected to any one of the second common lines;
In a switch matrix circuit comprising: an output line connected to any one of a plurality of switch circuits connected to each second common line;
Providing a signal for activating any one first common line of the first common line group of each of the systems so that any one of the plurality of second common lines is sequentially activated; It is achieved by a switch matrix circuit scanning method characterized by comprising:

In a preferred embodiment, in the switch matrix circuit, one end of each of the second common lines is connected to a grounded pull-down resistor, and one end of each of the output lines is connected to a constant voltage source. A precharge buffer for applying a voltage to each of the output lines is provided at the other end that is connected to the up resistor and is an output end of each of the output lines.
The first common line of any one of the first common lines of each system is activated by sequentially setting any one of the plurality of second common lines to a low level. The step of setting the
A voltage is applied from the output precharge buffer to each of the output lines for a predetermined period prior to setting any one of the first common lines of each system to the low level. And controlling the precharge buffer.

  According to the present invention, it is possible to provide a switch matrix circuit in which the number of signal lines is reduced and a scanning method thereof by making the matrix multidimensional.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an entire example of a switch matrix circuit according to an embodiment of the present invention. As shown in FIG. 1, the switch matrix circuit 1 according to the present embodiment includes a switch matrix unit 10 that forms a switch matrix, and a control circuit 3.

  The control circuit 3 and the switch matrix unit 10 are connected by a plurality of first common line groups each having a plurality of first common lines. In FIG. 1, a first common group of three systems (three first common lines COM1A to COM3A of the first system, three common lines COM1B to COM3B of the second system, and three of the third system Common lines COM1C to COM3C). Further, the control circuit 3 and the switch matrix unit 10 are connected by three output lines OUT1 to OUT3. Further, a signal line for supplying a precharge signal PRE for controlling a precharge buffer described later extends from the control circuit 3 to the switch matrix unit 10.

  As will be described later, the control circuit 3 sets any one first common line in the first common line group of each system to a low level at a predetermined timing, activates them, and then outputs the output lines OUT1 to OUT1. The signal from 3 is captured.

  2 and 3 are diagrams illustrating an example of a switch matrix unit of the switch matrix circuit according to the first embodiment of the present invention. In the example of FIGS. 2 and 3, a 3 × 3 × 3 matrix is formed by 3 × 3 (line) common lines and 3 (line) output lines.

  As shown in FIGS. 2 and 3, the switch matrix unit 10 of the switch matrix circuit according to the present embodiment includes three first common lines COM1A to COM3A of the first system and three of the second system. First common lines COM1B to COM3B and three output lines OUT1 to OUT3. In the conventional switching circuit, only 6 × 3 = 18 switches can be scanned with 6 common lines and 3 output lines, but in this embodiment, 3 × 3 × 3 = 27 switches. Can be scanned.

  The first common line of each system is connected via a diode capable of flowing a current only in the direction toward the second common line. More specifically, as shown in FIG. 2, the first common line of the first system (hereinafter, “COM1A” will be exemplarily described) passes through the buffer 12, passes through the first common line of the second system. Branches by the same number as the number of (COM1B to COM3B). The branched first common line of the first system is connected to a first common line of the second system through a diode (for example, reference numeral 16) in the same manner, via a diode (for example, reference numeral 14). Common lines (second common lines) connected to any first common line (for example, COM1B) of the second system are connected to the switch circuits 18, 20, and 22 by the number of output lines. In the present specification, a common line (for example, reference numeral 28) to which any of the first common lines of each system is connected is referred to as a second common line. One end of the second common line (for example, reference numeral 28) is connected to a grounded pull-down resistor (for example, reference numeral 24).

  The switch circuit includes a switch and a diode. One end of the switch circuit on the diode side is connected to the second common line, and the other end of the switch circuit is connected to the output line. Any one of a plurality of switch circuits connected to each of the second common lines is connected to one output line. In other words, each of the plurality of switch circuits connected to the second common line is connected to a different one of the plurality of output lines. One end of each of the output lines (OUT1 to OUT3) is connected to a pull-up resistor (see reference numeral 26, for example).

  As shown in FIG. 3, a buffer (for example, reference numeral 30) is provided at the other end (output end) of the output line. Further, a precharge buffer (for example, reference numeral 32) for charging a potential from VCC is connected to the output line. The precharge buffer is driven by a precharge signal PRE output from the control circuit 3, and applies a potential from VCC to the output line when the precharge signal is at a high level.

  FIG. 4 is a timing chart of the first common lines COM1A to 3A, COM1B to 3B and the precharge signal PRE in the present embodiment. In FIG. 4, the timing indicated by a broken line corresponds to the signal capture timing of the output lines OUT <b> 1 to OUT <b> 3. Therefore, the interval between the broken lines corresponds to approximately one processing cycle.

  In the present embodiment, the control circuit 3 causes the first common line group of each system to be activated by sequentially setting any one of the plurality of second common lines to a low level. Any one of the first common lines is set to the low level. In addition, the control circuit 3 applies a precharge buffer to each output line for a predetermined period before setting any one of the first common lines of each system to the low level. The precharge signal PRE is output to the precharge buffer so that the voltage is applied.

  As shown in FIG. 4, the precharge signal PRE is set to the high level for a predetermined time at the beginning of the processing cycle, that is, after the completion of the signal capture of the signal lines OUT1 to OUT3. After the precharge signal PRE is returned to the low level, any one of the first common lines of the first system and any one of the first common lines of the second system are set to the low level to be active. To do. Thereby, the second common line connected to the first common line of the first system and the second system that became active becomes active, and the states of the switch circuits connected to the second common line are respectively Output is possible from the output line. The state of the switch circuit connected to the activated second common line appears on the output lines OUT1 to OUT3. The control circuit 3 captures this state at the capture timing.

  In the example of FIG. 4, it is connected to the second common line 28 connected to the first common line COM1A of the first system and the first common line COM1B of the second system in the first process recycling (see reference numeral 401). The states of the switch circuit groups 18, 20, and 22 thus made can be scanned. Therefore, at the timing 411, the states of the switch groups 18, 20, and 22 are output from the output lines OUT1 to OUT3, respectively. In the next processing cycle (see reference numeral 402), the states of the switch circuit groups 34, 36, and 38 to which the first common line COM2A of the first system and the first common line COM1B of the second system are connected can be scanned. At timing 412, the states of these switch circuit groups can be scanned. Thereafter, the second common line connected to the first common line COM3A of the first system and the first common line COM1B of the second system, the first common line COM1A of the first system, and the second common line COM1A of the second system. The state of the switch group connected to each of the second common lines connected to the one common line COM2B can be sequentially scanned.

  For example, in the first processing cycle 401, when the switch of the switch circuit 20 is turned on, the charge of the output line OUT2 that has been precharged passes through the switch and the diode of the switch circuit to the second common line 28 side. Therefore, a low level signal is output from the output line OUT2. In contrast, since the switches of the switch circuits 18 and 22 are not turned on, the output lines OUT1 and OUT3 are precharged. Therefore, a high level signal is output from each of the output lines OUT1 and OUT3.

  Hereinafter, a pull-up resistor (see, for example, reference numeral 26), a pull-down resistor (see, for example, reference numeral 24) and a precharge signal will be described. The voltage (potential difference) in the pull-down resistor is related to the ratio of the resistance values of the pull-up resistor and the pull-down resistor.

  Consider a case where there are a plurality of output signals for one second common line, and switches connected to the same second common line are simultaneously turned on. For example, in the example of FIG. 2, in the second common line 28 to which the first common line COM1A and the first common line COM1B are connected, the switch circuits 18 to 22 connected to the second common line 28 are connected. This is a case where all the switches are turned on.

  As described above, when all the switches connected to the second common line are turned on, the pull-up resistors are connected in parallel and the end portions thereof are connected to the pull-down resistors. If not all of the switches are turned on at the same time, the same number of pull-up resistors as the plurality of switches are connected in parallel.

  Since one end of the pull-down resistor is connected to the power supply, while one end of the pull-up resistor is grounded, the potential at the connection point between the pull-down resistor and the pull-up resistor depends on the resistance value of the pull-up resistor and the pull-down resistor. It becomes the divided value. Therefore, as described above, when all the switches (or a plurality of switches if not all) connected to the same second common line are turned on, the resistance value of the combined resistance of the pull-up resistors becomes small. As a result, the voltage applied to the pull-down resistor becomes high.

  In order to prevent such a situation, it is desirable to make the resistance value of the pull-up resistor as large as possible, while making the resistance value of the pull-down resistor as small as possible. However, as the resistance value of the pull-up resistor is increased, the time for the level of the signal from the output line to transition from “low level” to “high level” increases, that is, the scanning speed of the switch matrix circuit increases. There is a problem that it becomes difficult to do.

  Therefore, in the present embodiment, a buffer for precharging the output line to “high level” for a predetermined time is prepared on the first half of the processing cycle, and the output line is precharged so that the pull-up resistor can be used. The transition time can be made faster than the transition time from “low level” to “high level”. Therefore, by preparing a precharge buffer and precharging the output line, it is possible to increase the number of connected switches and output lines per second common line.

  In the present embodiment, the ratio between the resistance value of the pull-up resistor and the resistance value of the pull-down resistor is about 100: 1. For example, the resistance value of the pull-up resistor can be 100 kΩ, and the resistance value of the pull-down resistor can be 1 kΩ.

  In this embodiment, one processing cycle is approximately 100 μS, and the precharge PRE signal PRE is “high” only for a period of approximately 25 percent (approximately 25 μS), and is output from the precharge buffer during that period. The line is precharged.

  In the first embodiment, when the number of first common lines in the first system, the number of second common lines in the second system, and the number of output lines are M, N, and I, respectively, The number of switches that can be scanned is “M × N × I”. Further, the number of signal lines necessary for scanning is “M + N + I”.

  FIG. 5 shows that when M = N = I, the sum of the first common lines of the first system, the first common lines of the second system and the output lines (the total number of signals), 5 is a table showing the number of switches that can be scanned with the total number of signals, the number of switches that can be scanned, and the same number of signals in a conventional switch matrix circuit. For example, when “M = N = I = 3 (total of signal lines: 9)”, according to the present embodiment, “3 × 3 × 3 = 27” switches can be scanned. On the other hand, in the conventional switch matrix circuit, when the total number of signal lines is 9, “5 × 4 = 20” switches can be scanned. It can be understood that the difference between the number of switches that can be scanned in this embodiment and the number of switches that can be scanned by the conventional switch matrix circuit increases as the total number of signal lines increases.

  According to the present embodiment, a plurality of common lines are provided in the switch matrix circuit, so that the matrix is multi-dimensional, so that more switches can be scanned with fewer signal lines than in the conventional switch matrix circuit. It becomes possible to do.

  In addition, according to the present embodiment, a buffer for precharging the output line to “high level” for a predetermined time is prepared on the first half of the processing cycle, and the output line is precharged, thereby pulling up the output line. The transition time from “low level” to “high level” of the output line can be made faster than the transition time from “low level” to “high level” depending on the resistance.

  Next, a second embodiment of the present invention will be described. In the first embodiment, the matrix is three-dimensionalized by using the first common line group of the two systems of the first system and the second system. In the second embodiment, the matrix is made four-dimensional using the first common line group of three systems. 6 to 9 are diagrams illustrating an example of the switch matrix unit of the switch matrix circuit according to the second embodiment of the present invention. In the switch matrix part of the switch matrix circuit according to the second embodiment, the first common lines COM1A to COM3A of the first system, the first common lines COM1B to COM2B of the second system, the first of the third system. Common lines COM1C to COM3C and output lines OUT1 to OUT3.

  As shown in FIGS. 6 to 8, any of the first common lines of the first system, any of the first common lines of the second system, and any of the first common lines of the third system Are connected via a diode to form a second common line. Each of the second common lines is connected to a switch circuit connected to one of the three output lines. For example, in FIG. 6, the second common line to which the first common lines COM1A, COM1B, and COM1C are connected, the second common line to which the first common lines COM1A, COM1B, and COM2C are connected, and the first The second common lines to which the common lines COM1A, COM1B, and COM3C are connected are respectively connected to three switch circuits as shown in FIG. In the second embodiment, there are nine switch circuit groups having nine switch circuits as shown in FIG. Therefore, in the second embodiment, “3 × 3 × 3 × 3 = 81” switches can be scanned. As shown in FIG. 9A, the end of the signal line connected to the switch circuit is grounded via a pull-down resistor (for example, reference numeral 901).

  Further, as shown in FIG. 9B, also in the second embodiment, the buffer is driven by the precharge signal PRE and applies the potential from VCC to the output line when the precharge signal is at the high level. (See, for example, reference numeral 911). One end of each of the output lines OUT1 to OUT3 is connected to a pull-up resistor (see, for example, reference numeral 912).

  Also in the switch matrix circuit according to the second embodiment, the precharge signal PRE is set to the high level only for a certain time in the first half of the processing cycle. After the precharge signal PRE is returned to the low level, one of the first common lines of the first system, one of the first common lines of the second system, and the first common line of the third system Any one of the above is made active at a low level. As a result, the first common line of the first system, the first common line of the second system, and the second common line connected to the first common line of the third system are activated. The state of each switch circuit can be output from the output line.

  When the first common line group of the three systems is provided, the number of the first common lines of the first system is M, the number of the first common lines of the second system is N, the first of the third system When the number of common lines is P and the number of output lines is I, the number of operable switches is “M × N × P × I”, and the number of signal lines necessary for scanning is “M + N + P + I”.

Alternatively, it is assumed that the number of first common lines in the first system to the third system is the same, and the number of first common lines in each system is M. Here, assuming that the number of systems is n (that is, from the first system to the n-th system) and that the number of output lines is I, the number of operable switches is “M ⁿ × I”. It becomes. The number of signal lines necessary for scanning is “M × n + I”.

  FIG. 10 is a table showing the total number of signals and the number of scannable switches when the number n of common systems is considered to be 1 to 4. Here, it is considered that the number M of the first common lines in each system is equal to the number I of the output lines. The number of common systems = 1 corresponds to a conventional two-dimensional switch matrix circuit. As can be understood from FIG. 10, even when the total number of signals is the same, it is understood that more switches can be scanned when the number of common systems is larger (that is, the dimension of the switch matrix portion is larger).

  The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

In the above embodiment, the number of common lines and the number of output lines in each of the first common line groups of each system are not limited to the above embodiment. In the first common line group of the plurality of systems, there are M ₁ , M ₂ ,..., M _n first system, second system,. Considering that there are I output lines, it is possible to scan M ₁ × M ₂ ×... × M _n × I switch circuits.

It is a block diagram which shows the whole example of the switch matrix circuit concerning embodiment of this invention. FIG. 2 is a diagram illustrating an example of a switch matrix unit according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating an example of the switch matrix unit according to the first embodiment of the present invention. FIG. 4 is a timing chart of the first common lines COM1A to 3A, COM1B to 3B and the precharge signal PRE in the present embodiment. FIG. 5 shows that when M = N = I, the sum of the first common lines of the first system, the first common lines of the second system and the output lines (the total number of signals), 5 is a table showing the number of switches that can be scanned with the total number of signals, the number of switches that can be scanned, and the same number of signals in a conventional switch matrix circuit. FIG. 6 is a diagram illustrating an example of a switch matrix unit according to the second embodiment of the present invention. FIG. 7 is a diagram illustrating an example of a switch matrix unit according to the second embodiment of the present invention. FIG. 8 is a diagram illustrating an example of a switch matrix unit according to the second embodiment of the present invention. FIGS. 9A and 9B are diagrams illustrating an example of a switch matrix unit according to the second embodiment of the present invention. FIG. 10 is a table showing the total number of signals and the number of scannable switches when the common system number n is considered to be 1 to 4 in the second embodiment. FIG. 11 is a diagram illustrating an example of a conventional switch matrix circuit. FIG. 12 is a timing chart of signals on the common line of the switch matrix circuit shown in FIG.

Explanation of symbols

12 Buffer 14, 16 Diode 18, 20, 22, 34, 36, 38 Switch circuit 24 Pull-down resistor 26 Pull-up resistor 28 Second common line 30 Buffer 32 Precharge buffer

Claims (8)

A plurality of first common line groups each having a plurality of first common lines;
A plurality of second common lines each connected to any one of the first common line groups of each system;
A plurality of switch circuits each connected to any one of the second common lines;
A switch matrix circuit comprising: an output line connected to any one of a plurality of switch circuits connected to each second common line.   Any one first common line in the first common line group of each system is connected via a diode capable of flowing a current only in a direction toward the second common line. The switch matrix circuit according to claim 1. In the first common line group of the plurality of systems, there are M ₁ , M ₂ ,..., M _n first system, second system,. 3. The switch matrix circuit according to claim 1, wherein the number of the output lines is I, and the number of the switch circuits is M ₁ × M ₂ ×... × M _n × I.   A signal for activating any one first common line of the first common line group of each system is provided so as to sequentially activate any one of the plurality of second common lines. The switch matrix circuit according to any one of claims 1 to 3, further comprising a control circuit. One end of each of the second common lines is connected to a grounded pull-down resistor,
One end of each of the output lines is connected to a pull-up resistor connected to a constant voltage source, and a voltage is applied to each of the output lines to the other end that is an output end of each of the output lines. 5. The switch matrix circuit according to claim 1, further comprising a precharge buffer.   The first common line of any one of the first common lines of each system is activated by sequentially setting any one of the plurality of second common lines to a low level. And a control circuit that sets the first common line of each system to a low level for a predetermined period of time prior to setting one of the first common lines to the low level. 6. The switch matrix circuit according to claim 5, wherein the precharge buffer is controlled so that a voltage is applied to each of the output lines from the charge buffer. A plurality of first common line groups each having a plurality of first common lines;
A plurality of second common lines each connected to any one of the first common line groups of each system;
A plurality of switch circuits each connected to any one of the second common lines;
In a switch matrix circuit comprising: an output line connected to any one of a plurality of switch circuits connected to each second common line;
Providing a signal for activating any one first common line of the first common line group of each of the systems so that any one of the plurality of second common lines is sequentially activated; A method for scanning a switch matrix circuit, comprising: In the switch matrix circuit, one end of each of the second common lines is connected to a grounded pull-down resistor, and one end of each of the output lines is connected to a pull-up resistor connected to a constant voltage source, And, at the other end which is the output end of each of the output lines, a precharge buffer for applying a voltage to each of the output lines is provided,
The first common line of any one of the first common lines of each system is activated by sequentially setting any one of the plurality of second common lines to a low level. The step of setting the
A voltage is applied from the precharge buffer to each of the output lines for a predetermined period prior to setting any one of the first common lines of each system to the low level. And a step of controlling the precharge buffer. 9. The switch matrix circuit scanning method according to claim 7, further comprising:

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