GB2338618A - Interlace to non-interlace conversion - Google Patents

Abstract

A display converter 110 comprises at least two line stores 114 and 115 which receive a field interlaced digital signal 113 that comprises lines of data and fields of data corresponding to an image. Each line store 114 and 115 is arranged to output its stored line of data at predetermined intervals in time, which constitute a rate substantially greater than the field of data frequency, so that the lines of data form a sequential output signal 119 used in this case to drive a liquid crystal display 117.

Description

2338618 1WROVEMENTS IN OR RELATING TO DISPLAY CONVERTERS This invention

relates to a display converter, in particular to a display converter for conversion of an interlaced video display signal into a sequential output signal suitable for addressing a non-interlaced display without substantially adding to the latency of the image.

As is commonly known, an interlaced technique requires each complete image or frame to be constructed from two sequential fields. A first field consists of lines of data, for example 1,3,5.... etc, and is commonly termed the odd field and a second field consists of lines of data, for example 2, 4, 6.... etc, and is commonly termed the even field. The resultant time delay between the beginning of transmission of an odd field and the beginning of transmission of an even field, that is the delay between lines of data 1 and 2, may be as long as 20 milliseconds in a fifty hertz interlaced video system.

In a non-interlaced display system, each complete image or frame is constructed from a single field which consists of fines of data, for example 1, 2, 3 4, 5, 6.... etc, that are used to address fines of a noninterlaced display. A non-interlaced system may be also known as a sequential or progressive scan system.

It is commonly known that a cathode ray tube system is particularly suited to showing interlaced images. In this system the most recent field of data is always written immediately to a screen of the tube. A remainder image of the field is maintained by the persistence of excited phosphor used to form the screen and the integrating effects of the eye and brain of an observer of the screen while the next field of data is written to the screen. In this manner the observer will not notice that odd and even fields of data are written to the screen at different periods in time.

Whereas a cathode ray tube system is inherently a random write device to which fields of video data can be written and displayed in the convenient order, non- interlaced displays, such as active matrix liquid crystal displays, are configured to display a complete image or frame with each line of data followed consecutively by the next line of data. A non interlaced display is not suited for writing or showing odd and even fields of data at different periods in time.

The most popular interlaced television and video standards are currently a SOHz field rate using 625 lines of data, commonly known as phase alternation line (PAL) which is used in Europe, or a 60Hz field rate using 575 fines of data, commonly known as National Television System Committee (NTSC) which is used in the United States of America. Information conforming to these standards must be converted respectively to a 50Hz frame rate using 625 lines of non-interlaced data or a 60Hz frame rate using 575 lines of noninterlaced data for showing on a non- interlaced display.

A known method of converting an interlaced video signal into a noninterlaced signal suitable for driving a non-interlaced display includes converting the analogue signal to a digital signal, combining each odd field of data with its respective even field of data in a digital memory field stores and writing a reconstructed image line by line to the noninterlaced display. A disadvantage with tls method is that latency is introduced to the shown image. A finiher disadvantage is the cost of memory needed for two field stores each capable of holding an entire field of odd or even lines of data.

The term latency is used to define the temporal delay between the time that a line of data is available for display and the time when it is actually displayed. When the image is reconstructed in digital memory, the latency can well be in excess of 40 milliseconds for a 50H.z video standard.

Furthermore, this known method of conversion introduces vertical distortion in the image shown on a non-interlaced display. Consider a vertical fine moving across a cathode ray tube screen, an interlaced video display signal corresponding to the vertical line will comprise an odd field having lines of data representing the vertical line during a first transmission period of time, while during a second transmission period of time an even field will comprise lines of data representing the vertical line. However, the fine standard is approximately 20 milliseconds, that is there is a delay between the odd and even fields of approximately 20 milliseconds. Once each field is stored in the field stores and written to a non-interlaced display, the line standard delay manifests itself in a zig-zag appearance of the vertical line since the odd field leads the even file in time.

It is an object of this invention to obviate or mitigate the disadvantages associated with the prior art.

According to the invention a display converter comprises at least two line stores operably arranged to receive a field interlaced digital signal comprising lines of data and field of data, each be store being arranged to output its stored line of data at predetermined intervals in -4time, which constitute a rate substantially greater than the field of data frequency, so that the lines of data form a sequential output signal. In this manner the need for two large storage elements to store data corresponding to the odd and even fields is obviated and the latency of the image is reduced.

An analogue to digital converter may be operably arranged to convert an interlaced analogue video display signal into the interlaced digital signal.

Preferably, the output bus may be operably connected to a liquid crystal display and the sequential output signal is used to drive the display. in this manner an input interlaced video display signal in converted into an output signal suitable for showing on a non-interlaced display.

The digital signal may comprise a plurality of lines of data each line of which forms part of either an odd or even field of the interlaced video display signal.

In a first embodiment, first and second line stores may be operably arranged to receive and store alternate lines of data associated with a given field of data from the digital signal.

Preferably, a clock element may be operably arranged to generate a clock signal arranged to repeatedly cause each fine of data stored in one of the fine stores to be placed twice on the output bus at substantially twice the rate of the digital signal, and then to subsequently cause each fine of data stored in the other fine store to be placed twice on the output bus at substantially twice the rate of the digital signal. The clock signal may also be arranged to -5repeatedly cause the digital signal to be received and stored in one of the line stores while substantially concurrently a line of data stored in the other line store is placed twice on the output bus.

In a second embodiment, a field storage element may be operably arranged to receive and store lines of data associated with a previous field of data from the digital signal and three line stores may be operably arranged to receive and store consecutive lines of data associate with a current field of data from the digital signal.

Preferably, a clock element may be operably arranged to generate a clock signal arranged to repeatedly cause the line stores in turn to place each line of data stored therein on the output bus and the clock signal may also be arranged to substantially concurrently cause each next line of data stored in the field store to be placed on the output bus. Once each fine of data from each line store has been placed on the output bus it may be consecutively stored as a line of data in the field store and may be arranged to replace each line of data associated with the previous filed of data already placed on the output bus.

Alternatively, in a third embodiment, a digital to analogue converter may be operably arranged to convert the output signal into a sequential analogue output signal.

The invention will now be described, by way of example only, with reference to the accompanying drawings, in which- Figure 1 is a schematic diagram of a first embodiment of the present invention,- -6Figures 2 and 3 are timing diagrams for the embodiment given in Figure 1 illustrating the odd and even fields respectively;

Figure 4 is a schematic diagram of a second embodiment of the present invention, and Figures 5 and 6 are timing diagrams for the embodiment illustrated in Figure 4 illustrating odd and even fields respectively.

In Figure 1 a display converter 110 comprises an analogue to digital converter 111 operably arranged to convert an analogue video signal 112 into a digital signal 113. The analogue to digital converter 111 is operably connected to a pair of line stores 114 and 115 by a data bus 116 and each be store 114, 115 is operably arranged to store various portions of the digital signal 113. The line stores 114, 115 are operably connected to a non-interlaced display 117 by an output bus 118. The fine store elements 114, 115 are arranged to generate a sequential output signal 119, as is described below, which is used to drive and control the display 117.

The analogue to digital converter 111, each line store 114, 115 and the non-interlaced display 117 are each controlled by a control signal carried by control bus 120 which is operably connected to a clock element, not shown, that is arranged to generate the control signal and oversee data movement through the display converter 110.

The be stores 114, 115 can be a first in, first out type memory devices having an eighteen bit data bus to provide the capacity to store three channels of video simultaneously. That is each channel is assigned six bits which equates to sixty-four grey shades.

Figure 2 shows a timing diagram for an odd field of data and its progression through the display converter 110. The analogue video signal input is digitised by the analogue to digital converter 111 into a digital signal 113 which is then received by line stores 114, 115 and the output signal 119 placed on the output bus 118 in the following manner. It should be recalled that the digital signal 113 is an interlaced signal composed of sequential odd and even fields comprising fines of data, wherein each field constitutes half the frame of the image to be shown. The odd field fines of data are denoted by references 1, 3, 5, 7, 9, 11, 13, 15 and 17 etc.

Considering first the odd field, during a first time period line of data 1 is received and stored in fine store 114 as can be seen in timing sequence 12 1. During a second time period the next line of data 3 is stored in line store 115, as illustrated in timing sequence 122, while simultaneously the Srst line of data 1, as stored in line store 114, is placed twice on the output bus 118 as output signal 119, shown as timing sequence 123, at twice the rate of the digital signal 113. In effect two lines of data 1 and 1 ' are placed on the output bus 118 during the second time period but since they are placed on the output bus 118 at twice the rate of the digital signal 113 they can be arranged to occupy different time periods such that they do not overlap. This can be clearly seen in tirriing sequences 124 and 125. The rates of the digital signal 113 and the output signal 119 are controlled by the clock element through control line 120. The first fine of data 1 placed on the output bus 118 is used to drive a first line of the non-interlaced display 117 and the second line of data 1 ' placed on the output bus 118 is used drive a second line of the non-interlaced display 117.

During a tl-rd time period line of date 5 is stored in line store 114, as illustrated in timing sequence 121, overwriting the previous contents, while simultaneously the line of data 3 is placed twice on the output bus 118 as output signal 119, as shown in timing sequence 123, at twice the rate of the digital signal 113. That is two non overlapping lines of data at 3 and 3' are placed on the output bus 118 during the third time period. This can be clearly seen in timing sequences 126 and 127. In this case the line of data 3 is used to drive a third line of the non-interlaced display 117 and line of data 3' is used to drive a fourth line of the noninterlaced display 117.

In this manner, lines 1, 3, 5, 7 etc. are written to the non-interlaced display 117 and respectively drive lines 1 and 2, 3 and 4, 5 and 6, 7 and 8 etc. of the non-interlaced display 117, as is illustrated by comparison of timing sequence 123 and timing sequence 128 indicating the lines of the display driven by output signal 119.

Now considering an even fielc the beginning of which is received some twenty milliseconds after the beginning of transmission of the odd field, eg. each field is approximately twenty milliseconds in duration. The even field is illustrated in Figure 3 and like references have been used to denote sirnilar features to those used in Figure 2. Again, the even field fine of data are denoted by references 2, 4, 6, 8, 10, 12, 16, 18 etc.

The even field is digitised into a digital signal 113 by the analogue to digital converter 111, the digital signal 113 is then received and stored in he stores 114, 115 and the output signal 119 placed on the output bus 118 in the following manner. During a first time period a first line of data 2 is received and stored in line store 114, as can be seen timing sequence 121.

During a second time period the next line of data 4 is stored in line store 115, as illustrated in timing sequence 122, while simultaneously the first line of data 2, as stored in line store 114, is placed twice on the output bus 118 as output signal 119, shown as timing sequence 123, at twice the rate of the digital signal 113. Again, in effect two lines of data 2 and 2' are placed on the output bus 118 at different time periods during the second time period. This can be seen in timing sequences 124 and 125. The first line of data 2 placed on the output bus 118 at different time periods is used to drive a second fine of the noninterlaced display 117 and the second line of data 2' placed on the output bus 118 is used to drive a third line of the non-interlaced display 117.

During a third time period the next line of data 6 is stored in line store 114, as shown in timing sequence 121, overwriting the previous contents, while simultaneously the fine of data 4, as stored in fine store 115, is placed twice on the output bus 118 as output signal 119 shown as timing sequence 123, at twice the rate of the digital signal 113. That is two nonoverlapping lines of data 4 and 4' are placed on the output bus 118 during the third time period. This can be clearly seen in timing sequences 126 and 127. In this case the line of data 4 is used to drive a fourth line the non-interlaced display 117 and the second line of data 4' placed on the output bus 118 is used to drive a fifth fine of the non-interlaced display 117.

In this manner, fines of data 2, 4, 6, 7 etc. are written to the noninterlaced display 117 and respectively drive lines 2 and 3, 4 and 5, 6 and 7, 8 and 9 etc. of the non-interlaced display 117, as is illustrated by comparison of time sequence 123 and timing sequence 128 indicating the lines of the display driven by output signal 119. It should be noted that the even field lines of data are written to the non-interlaced display 117 off-set by one line. That is line of -10data 1 is written to the first and second lines of the non-interlaced display 117, whereas line of data 2 is written the second and third line of the display.

is In this manner the latency of the image is reduced to one fine of data, which in a fifty hertz type system equates to a sixty-four microsecond latency. This compares to the latency of approximately 40 milliseconds in prior art system using two field stores. Furthermore, when the image is shown on a non-interlaced display 117 the apparent delay between the first and second lines on the display 117 has been reduced to sixty-four microseconds. In this manner, the zig-zag appearance in a vertical line moving across the display 117 is reduced.

Figure 4 illustrates a second embodiment of the invention, wherein a display converter 130 comprises an analogue to digital converter 131 which is operably connected by a data bus 132 to three line store 133, 134 and 135. Each line store 133, 134, 135 is operably connected by a data bus 13 6 to a field store 13 7 and operably connected by an output bus 138 to a non-interlaced display 139.

The analogue to digital converter 13 1, each line store 13 3, 134, 13 5, the field store 13 7 and the non-interlaced display 139 are each controlled by a control signal carried by a control bus 140 operably connected to a clock element, not shown, which is operably arranged to generate the control signal and oversee data movement through the display converter 130.

An analogue video signal 141 is converted by the analogue to digital converter 13 1 into a digital signal 142 which is placed on the data bus 132. The digital signal 142 is supplied to each of the line stores 133, 134, 135 which are arranged to store various portions of the digital signal 142 and, according to a control signal supplied by the control bus 140, place lines of data on the data bus 136 to the field store 137 or place fines of data on the output bus 138 to drive various lines of the display 139. Again the line stores 133, 134, 135 can be first in, first out type memory devices having an eighteen bit data bus and the field store

137 can be a memory device capable of storing a complete field.

Consider an odd field of data and its progression through the display converter 130, as shown in Figure 5. The odd field lines of data are denoted by references 1, 3, 5, 7, 9, 11, 13, 15 and 17 etc. An analogue video signal 141 is digitised by the analogue to digital converter 131 into a digital signal 142 which is placed on the data bus 132 according to a control signal generated on the control bus 140 and thefield store 137 already comprises the entire previously received even field denoted by referenced 2', 4% 6, 8% 10% 12% 14' and 16' etc. During a first time period fine store 133 receives and stores line of data 1, as can be seen in timing sequence 143. During a second time period line store 134 receives and stores fine of data 3, shown in timing sequence 144, while during a first half of the second time period line of data 1, as stored in fine store 133, is placed on the output bus 138, as illustrated in timing sequence 145, to drive a first line of the display 139. During a second half of the second time period fine of data 2' corresponding to the even field previously stored in field store 137 is placed on the output bus 138, as can be seen in timing sequence 146, to drive a second line of the display 139.

During a third time period line store 135 receives and stores line of data 5, as can be seen in timing sequence 147, while during a first half of the third time period line of data 3, as stored in fine store 134, is placed on the output bus 138, as can be seen in timing sequence 145, to drive a third line of the display 139 and line of data 1, as stored in line store 133, is placed on data bus 13 6, as shown in timing sequence 148, and stored in the field store 13 7 as line of data 1' to overwrite the location previously storing line of data 2'. During a second half of the third time period line of data 4', as stored in field store 13 7, is placed on the output bus 138, as illustrated in timing sequence 146, to drive a fourth line of the display 139.

During a fourth time period line store 13 3 receives and stores line of data 7, as can be seen in time sequence 143, which overwrites previously stored fine of data 1, while during a first half of the fourth time period line of data 5, as stored in fine store 135, is placed on the output bus 138, as shown in time sequence 145, to drive a fifth fine 5 of the display 139 and be of data 3, as stored in line store 134, is placed on data bus 136, as illustrated in timing sequence 148, and stored in the field store 137 as lines of data 3' to overwrite the location previously storing fine of data 4'. During a second half of the fourth time period line of data 6% as stored in field store 137, is placed on the output bus 138, as can be seen in timing sequence 146, to drive a sixth fine of the display 139.

Timing sequence 149 indicates the line of the display 139 driven by the lines of data given in timing sequences 145 and 146.

This sequence of events is repeated until all the odd field lines of data eg. 1, 3, 5, 7 etc. have been clocked through the display converter 13 0 and the field store 13 7 contains the entire odd field lines of data 1, 3, 5, 7 etc. which then become the previous odd field V, Y, 5', 7' etc. In practice the first three cycles described above would coincide with the hand over -13 from the previous even field lines of data 2', 4', 6, 8' etc. and the current odd field lines of data 1, 3, 5, 7 etc. The sequence of events is illustrated for the odd field only to aid clarity, but it should be understood that the tail end of the previous even field fines of data 2% 4% 6% 8' etc would already be stored in the fine stores 133, 134 and 135 and that the lines of data corresponding to the previous even 2% 4% 6% 8' etc field would be placed on the output bus 138 while fines of data 1, 3, 5 and 7 etc. are received and stored thereby forming a continuous cycle between received odd and even fields.

From Figure 6 it can be seen that the even field fines of data 2, 4, 6, 8 etc are treated in the same manner as the odd field lines of data 1, 3, 5, 6 etc. described with reference to Figure 5. However, the field store 137 now places previous odd field fines of data 1% 3% 5% 7' etc. on the output bus 138 to drive the fines of the display 139 and the current even field lines of data 2, 4, 6, 8 etc will overwrite the lines of data 1', 3 1, 5% 7' etc. corresponding to the previous odd field already written to the display 139.

Therefore, consider an even field of data and its progression through the display converter 130, as shown in Figure 6. The even field lines of data are denoted by references 2, 4, 6, 8, 10, 12, 14, 16 and 18 etc. The analogue video signal 141 is digitised by the analogue to digital converter 131 into a digital signal 142 which is placed on the data bus 132 according to a control signal generated on the control bus 140 and the field store 137 already comprises the entire previously received odd field denoted by referenced 1% 3% 51, 7% 91, 1 P, 13' and 15' etc. During a first time period fine store 133 receives and stores line of data 2, as can be seen in timing sequence 143. During a second time period line store 134 receives and stores line of data 4, shown in timing sequence 144, while during a first half of -14the second time period line of data 1' corresponding to the odd field previously stored in field store 13 7 is placed on the output bus 13 8, as can be seen in timing sequence 146, to drive a first line of the display 139. During a second half of the second time period line of data 2, as stored in fine store 133, is placed on the output bus 138, as illustrated in timing sequence 145, to drive a second line of the display.

During a third time period fine store 135 receives and stores line of data 6, as can be seen in timing sequence 147, while during a first half of the third time period line of data 3% as stored in field store 137, is placed on the output bus 138, as illustrated in timing sequence 146, to drive a third line of the display 139. During a second half of the third time period line of data 4, as stored in line store 134, is placed on the output bus 138, as can be seen in timing sequence 145, to drive a fourth line of the display 139 and fine of data 2, as stored in line store 133, is placed on data bus 136, as shown in timing sequence 148, and stored in the field store 137 as line of data 2' to overwrite the location previously storing line of data 1 '.

During a fourth time period line store 133 receives and stores line of data 8, as can be seen in time sequence 143, which overwrites previously stored line of data 2, while during a first half of the fourth time period line of data 5', as stored in field store 137, is placed on the output bus 138, as can be seen in timing sequence 146, to drive a fifth line of the display 139. During a second half of the fourth time period line of data 6, as stored in line store 135, is placed on the output bus 138, as shown in timing sequence 145, to drive a sixth line 5 of the display 1-319 and line of data 4, as stored in line store 134, is placed on data bus 136, as illustrated in timing sequence 148, and stored in the field store 137 as line of data 4' to -15overwrite the location previously storing line of data Y.

Timing sequence 149 indicates the line of the display 139 driven by the fines of data given in timing sequences 145 and 146.

This sequence of events is repeated until all the even field lines of data eg. 2, 4, 6, 8 etc. have been clocked through the display converter 13 0 and the field store 13 7 contains the entire even field lines of data 2, 4, 6, 8 etc. which then become the previous even field 2% 4% 6', 8' etc. The cycle then reverts to that described with referenced to Figure 5.

The embodiment of the invention described with referenced to Figures 4 to 6 is a particular implementation of the invention which ensures that neither the field store 137 nor the fine stores 133, 134, 135 are required to store fines of data while concurrently placing lines of data on the data bus 136 or the output bus 138. However, it will be understood that a display converter may function with line and field stores that allow concurrent placing of lines of data on the data bus 136 or the output bus 138 while storing lines of data.

It will also be understood that the odd and even fields shown in Figure 2, 3, 5 and 6 may contain blank fines of data and that the display converter may be arranged to ornit processing of these blank Enes of data.

In a further embodiment, not illustrated, the output bus from the line and field stores could be passed to a digital to analogue converter to produce a non-interlaced or sequential output signal that could be used to drive a non-interlaced analogue display.

Claims (12)

1. A display converter, comprising at least two line stores operably arranged to receive a field interlaced digital signal comprising lines of data and fields of data, and each line store being arranged to output its stored line of data at predetermined intervals in time, which constitute a rate substantially greater than the field of data frequency, so that the lines of data form a sequential output signal.

A display converter, as in Claim 1, wherein an analogue to digital converter is operably arranged to convert an interlaced analogue video display signal into the interlaced digital signal.

A display converter, as in Claims 1 or 2, wherein the output bus is operably connected to a liquid crystal display and the sequential output signal is used to drive the display.

A display converter, as in any preceding claim, wherein the digital signal comprises a plurality of fines of data each line of which forms part of either an odd or even field of the interlaced video display signal.

5. A display converter, as in Claim 4, wherein first and second line stores are operably -17arranged to receive and store alternate lines of data associated with a given field of data from the digital signal.

6. A display converter, as in Claim 5, wherein a clock element is operably arranged to generate a clock signal arranged to repeatedly cause each line of data stored in one of the line stores to be placed twice on the output bus at substantially twice the rate of the digital signal, and then to subsequently cause each fine of data stored in the other line store to be placed twice on the output bus at substantially twice the rate of the digital signal.

7. A display converter, as in Claim 6, wherein the clock signal is also arranged to repeatedly cause the digital signal to be received and stored in one of the line stores while substantially concurrently a fine of data stored in the other fine store is placed twice on the output bus.

8. A display converter, as in Claim 4, wherein a field storage element is operably arranged to receive and store lines of data associated with a previous field of data from the digital signal and three line stores are operably arranged to receive and store consecutive fines of data associate with a current field of data from the digital signal.

9 A display converter, as in Claim 8, wherein a clock element is operably arranged to generate a clock signal arranged to repeatedly cause the line stores in turn to place each line of data stored therein on the output bus and the clock signal is also -18arranged to substantially concurrently cause each next line of data stored in the field store to be placed on the output bus.

10. A display converter, as in Claim 9, wherein once each line of data from each line store has been placed on the output bus it is consecutively stored as a fine of data in the field store and is arranged to replace each line of data associated with the previous filed of data already placed on the output bus.

11. A display converter, as in Claims 1 or 2, wherein a digital to analogue converter is operably arranged to convert the output signal into a sequential analogue signal.

12. A display converter substantially as illustrated in and /or as described with reference to the accompanying drawings.