GB2338590A - Insulated gate power semiconductor devices - Google Patents

Insulated gate power semiconductor devices Download PDF

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Publication number
GB2338590A
GB2338590A GB9812825A GB9812825A GB2338590A GB 2338590 A GB2338590 A GB 2338590A GB 9812825 A GB9812825 A GB 9812825A GB 9812825 A GB9812825 A GB 9812825A GB 2338590 A GB2338590 A GB 2338590A
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GB
United Kingdom
Prior art keywords
region
trenches
conductivity type
mask
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9812825A
Other versions
GB9812825D0 (en
Inventor
Peter Rawson Waind
Simon Sui Man Chan
James Thomson
Florin Udrea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor Ltd
Original Assignee
Mitel Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Semiconductor Ltd filed Critical Mitel Semiconductor Ltd
Priority to GB9812825A priority Critical patent/GB2338590A/en
Publication of GB9812825D0 publication Critical patent/GB9812825D0/en
Publication of GB2338590A publication Critical patent/GB2338590A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42308—Gate electrodes for thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

The semiconductor device has a plurality of gate trenches extending from a major surface thereof and which trenches extend through a shallow first region 9 of first conductivity type semiconductor, and through a second region 4 of second conductivity type semiconductor to terminate in a third region 1 of a first conductivity type semiconductor. An apertured mask is used to diffuse dopants into the third region to form the second region 4 and the same mask is used to define the gate trenches. The trenches so formed are used as a mask for introducing dopant to form the first region 9. The device may be an IGBT, a MOSFET or a thyristor.

Description

2338590 1 Power Semiconductor Device This invention relates to a power
semiconductor device and more particularly to a method of manufacturing such a device which permits a high voltage switchable device to be manufactured economically and reliably.
According to a first aspect of this invention, a method of making a power semiconductor device having a plurality of gate trenches extending from a major surface thereof and which trenches extend through a shallow first region of first conductivity type semiconductor, and through a second region of second conductivity type semiconductor to terminate in a third region of a first conductivity type semiconductor, said method including the steps of:
forming an apertured mask on said major surface, diffusing conductivity modifier dopants through the apertures in said mask to form said second region within the third region, utilising the same apertured mask to form trenches by etching semiconductor material under each aperture, forming a thin insulating layer on the wall of each trench and providing a conductive gate region on the face of said thin insulating layer remote from the semiconductor material.
The conductivity modifier dopants introduced via adjacent apertures in the mask may form localised second regions which are spaced apart from each other, or localised second regions which are contiguous with each other.
2 According to a second aspect of this invention a method of making a power semiconductor device having a plurality of gate trenches extending from a major surface thereof and which trenches extend through a shallow first region of first conductivity type semiconductor, and through a second region of second conductivity type semiconductor to terminate in a third region of a first conductivity type semiconductor, said method including the steps of:
forming an apertured mask on the surface of a semiconductor body of said second type; utilising the apertured mask to form said trenches by etching semiconductor material under each aperture; forming a thin insulating layer on the wall of each trench, and providing a conductive gate region on the face of said thin insulating layer remote from the semiconductor material; and utilising the trench so formed as a mask for introducing dopant into the surface of the semiconductor device to form said first region which extends between adjacent trenches.
Preferably further conductive regions, in the form of shallower trenches, are formed to penetrate said first region of first conductivity type between adjacent trenches, the further conductive regions being spaced apart from adjacent trenches by regions of said first conductivity type, the pn junction between said first and second regions being electrically shorted by said further conductive regions.
The shallower trench walls may be coated with a conductive material to constitute said further conductive regions, but preferably said shallower trenches are filled with conductive material.
3 The invention is further described by way of example with reference to the accompanying drawings, in which:
Figure 1 if a diagrammatic section view of a semiconductor device made in accordance with the invention, and Figures 2 to 9 show successive processing steps in the manufacture of the device. Figure 10 shows a modified device. Figures 11, 12 and 13 show processing steps in manufacturing a further modified device.
Referring to Figure 1, an IGBT semiconductor device consists of a substrate 1 of n type material. The device has a lower electrode 14, with a layer 13 of p type material, or n type material in the case of a MOSFET, between it and the substrate 1. An electrode 12 is provided at the upper surface of the device, and extending from the upper surface are a plurality of trenches, each trench consisting of a conductive material comprising a gate electrode 7, and a thin insulating layer 6 between the gate electrode and the semiconductor material which surrounds the trench. The trench extends from the upper surface through a thin first layer 9 of n type material and a thicker second region 4 of p type material, and terminates in the substrate 1 which comprises the third region.
Between adjacent trenches there is provided a shallower trench 10 comprising conductive material which makes electrical contact to the regions 4 and 9 and to electrode 12. A layer 8 of insulating material insulates the gate electrode 7 from electrode 12. To improve the electrical contact to the region 4, a layer 11 is provided at the base of trenches 10, the layer 11 consisting of the same electrical type of semiconductor as region 1 4 4 but having a higher dopant concentration.
The shallower trench 10 serves to electrically short the pn junction formed by p region 4 and the n type region 9.
The device shown in Figure 1 is made by the process steps illustrated in Figures 2 to 9, which show just the relevant portions of the device.
Referring to Figure 2, there is shown therein a silicon substrate 1 of n type material of uniform resistivity. Alternatively, this region may be of epitaxial construction formed on a further substrate, not shown. The resistivity of layer 1 is chosen to achieve a designed minimum breakdown for the device in the off-state, ie non-conductive state.
The first stage of the process is the formation of a masking layer 2 on the uppermost is surface of the semiconductor. The material of this masking layer will usually be an oxide or nitride of silicon or a combination of such layers. One option is to grow a relatively thick thermal oxide to act alone as the masking layer. Preferably a thin thermal oxide is grown and overlaid with a deposited silicon nitride layer followed by a second deposited silicon oxide layer. In either case the masking layer must be of sufficient thickness and composition to withstand the subsequent etching processes.
The pattern of the trench for the gate electrode is defined and etched into the upper surface of the semiconductor using conventional semiconductor photolithographic and etching techniques. The oxide and nitride layers 2 are first etched through with a photoresist pattern in place to create apertures or openings 3 in the masking layer as shown in Figure 3. Dopant ions are then implanted, and or, diffused through these openings 3 in the masking layer 2 to form a region 4 of opposite conductivity type to the starting material 1. Thus region 4 is of p type in this example. The diffusion time and temperature will normally be sufficient to form a continuous layer 4 by allowing diffusions from adjacent openings to merge as shown in Figure 3 to form contiguous localised regions as shown. Typically the maximum depth of these p type regions 4 is between 21= and 5,"m. During the diffusion process a thermal oxide will be grown on the exposed silicon in the openings 3. This must be removed by etching before the next stage. The nitride masking layer will remain in place during this oxide etch and be able to act as a mask during the next stage.
After the diffusion of layer 4 the trenches 5 are then etched into the exposed silicon using the same openings 3 as a mask pattern. These must be of sufficient depth to penetrate through the semiconductor layer 4 and into the layer 1. A dry (or plasma) etching is used to create the trenches and should have anisotropic etching properties so as to form trenches with near vertical side walls and avoid significantly undercutting the masking layer or layers 2. The bottom of the trenches should preferably be rounded to allow a good quality gate oxide to be grown and avoid excessive electric field concentrations during operation.
Following the etching of the trenches an insulating gate oxide layer 6 is grown on the side walls and bottoms of the trenches. A sacrificial oxide layer may be grown and removed prior to the gate oxide growth to improve the final oxide quality. The structure after the 6 gate oxide growth is depicted in Figure 4.
The trenches are then filled with polysilicon gate material. This will usually be done by chemical vapour deposition. The polysilicon is doped to increase its conductivity by diffusion with suitable ions such as phosphorus. The deposition will usually be done in two stages; the first stage will partly fill the trenches and be followed by the doping stage, then a second deposition stage will completely fill the trenches and leave polysilicon covering the upper surface of the semiconductor. Following this deposition, the polysilicon is removed from the upper surface during a planarisation stage; the polysilicon is etched back to the masking layer 2 leaving polysilicon gate material 7 located only in the trenches as shown in Figure 5.
The upper portions of the polysilicon gates are next oxidised to form regions 8 as shown in Figure 6. These provide electrical isolation of the gate from the emitter metallisation to be deposited later. During this oxidation the nitride layer 2 protects the surface of the silicon layer 4 from further oxidation.
The nitride layer 2 is removed by selective etching leaving oxide layer 8 intact. This exposes the surface of layer 4. Dopant ions of opposite conductivity to layer 4 are now implanted, and or, diffused into this exposed silicon surface to form another semiconductor layer 9 in this example n type, as shown in Figure 7.
1Proper operation of the semiconductor device requires that an electrical contact is made to both layers 4 and 9 to short out the pn junction. This contact to region 4 is made via 7 a second shallower trench 10. A photolithographic masking stage is used to define the regions for this second trench. The silicon may be etched using either a wet or dry etching process but must extend through the layer 9 and into layer 4, but not normally through into region 1. Electrical contact to region 4 may be poor due to the low concentration of dopant at the bottom of the contact trench. Contact can be improved by implanting and diffusing additional ions to produce a shallow layer 11 of the same electrical type as layer 4 but of higher dopant concentration as shown in Figure 8.
Electrical contact to regions 9 and 4 is made by evaporation or sputtering of a suitable metal 12 layer such as aluminium onto the upper surface followed by an anneal. Contact to the source 9 and body regions of the device are made at the upper surface of the semiconductor and the bottom of the contact trench respectively, while the oxide region 8 provides gate isolation as shown in Figure 9. The same metal layer 12 can make separate remote contact to the gate region using standard photolithographic techniques, is this is not illustrated. In the case of a power MOSFET device layer 12 is known as the source electrode, in the case of an IGBT it is known as the emitter and in the case of a thyristor the cathode. Drain or collector metal connections 14 are made to the lower surface of the semiconductor as shown in Figure 1.
An alternative embodiment of the invention is shown in Figure 10. In the previous embodiment, the diffusion 4 is of sufficient depth such that adjacent diffusions from windows 3 merge to form a continuous layer, and the second trench 10 does not penetrate through this layer. Alternatively the diffusions 4 may be shallower such that the trench 10 penetrates through it into region 1. Whether or not the diffusions are merged prior 1 8 to the formation of this second trench is immaterial. However, for the device to be functional the contact layer 12 must not make contact to layer 1. In Figure 10 the enhancement layer 11 will separate the metal from layer 1. Layer 11 must be of sufficient concentration and thickness to avoid premature punch through breakdown in the device off-state. In Figure 10, the configuration is such that the device can have a reduced channel length, and this can be advantageous as compared with Figure 1.
A nitride and oxide sandwich is used as the masking layer 2 in the previous embodiment and this allows selective etching to expose the upper silicon surface to permit diffusion of layer 9 while leaving the gate isolation layer 8 in place as shown in Figure 7.
Alternatively layer 2 may be a thermal oxide grown at the beginning of the process. This is then etched off after planarisation of the polysilicon gate material. Layer 9 is then implanted or diffused into the upper silicon surface. The polysilicon gate material 7 will also be exposed during this diffusion but this will merely add additional dopant of the same type to the polysilicon. After or during the formation of layer 9 a fresh silicon oxide layer 14 is thermally grown, and or, deposited on the upper surface to provide gate isolation as shown in Figure 11. The contact trench 10 is then etched directly and sequentially through layers 14 and 9 as shown in Figure 12. As before this trench is defined using photoresist. Finally the metal layer 12 makes contact to regions 9 and 11 along the sidewalls and bottom of the trench respectively as shown in Figure 13.
9

Claims (8)

Claims
1. A method of making a power semiconductor device having a plurality of gate trenches extending from a major surface thereof and which trenches extend through a shallow first region of first conductivity type semiconductor, and through a second region of second conductivity type semiconductor to terminate in a third region of a first conductivity type semiconductor, said method including the steps of:
forming an apertured mask on said major surface, diffusing conductivity modifier dopants through the apertures in said mask to form said second region within the third region, utilising the same apertured mask to form trenches by etching semiconductor material under each aperture, forming a thin insulating layer on the wall of each trench and providing a conductive gate region on the face of said thin insulating layer remote from the semiconductor material.
is
2. A method as claimed in Claim 1 and wherein the conductivity modifier dopants introduced via adjacent apertures in the mask form localised second regions which are spaced apart from each other.
3. A method as claimed in Claim 1 and wherein the conductivity modifier dopants introduced via adjacent apertures in the mask form localised second regions which are contiguous with each other.
4. A method of making a power semiconductor device having a plurality of gate trenches extending from a major surface thereof and which trenches extend through a shallow first region of first conductivity type semiconductor, and through a second region of second conductivity type semiconductor to terminate in a third region of a first conductivity type semiconductor, said method including the steps of:
forming an apertured mask on the surface of a semiconductor body of said second type; utilising the apertured mask to form said trenches by etching semiconductor material under each aperture; forming a thin insulating layer on the wall of each trench, and providing a conductive gate region on the face of said thin insulating layer remote from the semiconductor material; and utilising the trench so formed as a mask for introducing dopant into the surface of the semiconductor device to form said first region which extends between adjacent trenches.
5. A method as claimed in Claim 4 and wherein further conductive regions, in the is form of shallower trenches, are formed to penetrate said first region of first conductivity type between adjacent trenches, the further conductive regions being spaced apart from adjacent trenches by regions of said first conductivity type, the pri junction between said first and second regions being electrically shorted by said further conductive regions.
6. A power semiconductor device made in accordance with any of the preceding claims.
7. A method of making a power semiconductor device substantially as illustrated in and described with reference to Figures 1 to 9 of the accompanying drawings.
8. A method of making a power semiconductor device substantially as illustrated in and described with reference to Figures 10 to 13 of the accompanying drawings.
GB9812825A 1998-06-16 1998-06-16 Insulated gate power semiconductor devices Withdrawn GB2338590A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9812825A GB2338590A (en) 1998-06-16 1998-06-16 Insulated gate power semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9812825A GB2338590A (en) 1998-06-16 1998-06-16 Insulated gate power semiconductor devices

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GB9812825D0 GB9812825D0 (en) 1998-08-12
GB2338590A true GB2338590A (en) 1999-12-22

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5082795A (en) * 1986-12-05 1992-01-21 General Electric Company Method of fabricating a field effect semiconductor device having a self-aligned structure
EP0583028A1 (en) * 1992-08-05 1994-02-16 Philips Electronics Uk Limited A semiconductor device comprising a vertical insulated gate field effect device and a method of manufacturing such a device
US5554862A (en) * 1992-03-31 1996-09-10 Kabushiki Kaisha Toshiba Power semiconductor device
US5627393A (en) * 1994-12-07 1997-05-06 United Microelectronics Corporation Vertical channel device having buried source

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5082795A (en) * 1986-12-05 1992-01-21 General Electric Company Method of fabricating a field effect semiconductor device having a self-aligned structure
US5554862A (en) * 1992-03-31 1996-09-10 Kabushiki Kaisha Toshiba Power semiconductor device
EP0583028A1 (en) * 1992-08-05 1994-02-16 Philips Electronics Uk Limited A semiconductor device comprising a vertical insulated gate field effect device and a method of manufacturing such a device
US5627393A (en) * 1994-12-07 1997-05-06 United Microelectronics Corporation Vertical channel device having buried source

Also Published As

Publication number Publication date
GB9812825D0 (en) 1998-08-12

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