GB2337138A

GB2337138A - Arbitrating between a plurality of requests to access resources

Info

Publication number: GB2337138A
Application number: GB9802099A
Authority: GB
Inventors: James Graham Matthew; Anthony Xavier Jarvis
Original assignee: STMicroelectronics Ltd Great Britain; SGS Thomson Microelectronics Ltd
Current assignee: STMicroelectronics Ltd Great Britain
Priority date: 1998-01-30
Filing date: 1998-01-30
Publication date: 1999-11-10
Anticipated expiration: 2018-01-30
Also published as: GB2337138B; GB9802099D0

Abstract

An electrical system for sharing a resource or resources 3, e.g. a memory, has a hierarchical structure. In the first level, first and second functional elements 7 and 9, e.g. a CPU and a dedicated controller, are directly connected to resource 3 via bus 5 (or a routing system (701, Fig. 7)). Functional element 9 comprises further functional elements 19, 21, 23 at a second level, and an arbitrating switch 11. Further hierarchical levels, with corresponding switches, may be included (Fig. 1b). Each switch arbitrates the access of elements in a lower level to a higher level, receiving a plurality of request signals identifying the resource(s) to which access is requested, and status signals identifying whether a resource can be accessed, and arbitrating between requests for resources which can be accessed. The switches can shuffle different requests to a given resource, but will not shuffle during a burst access. The switch circuitry is described in some detail (Figs. 5 and 6). A described embodiment (Figs. 8-10) relates to arbitration between requests from different functional units to access resources in a television set-top box.

Description

1 ARBITRATION 2337138 This invention relates to circuitry for arbitrating

between a plurality of request signals to access resources and a method of arbitrating between a plurality of requests to access resources.

According to a first aspect of the present invbntion there is provided circuitry for arbitrating between a plurality of request signals to access resources, comprising:

input means for receiving said plurality of request signals, wherein each request signal identifies the resource to which it is requesting access; and arbitration means arranged to receive said plurality of request signals, and status signals wherein each status signal identifies whether a resource is capable of being accessed, and wherein said arbitration means is arranged to arbitrate between request signals which are requesting access to resources having status signals indicating that they are capable of being accessed, to select one request signal.

Embodiments of the present invention have particular application "onchip" as part of an integrated electronic circuit. According to a preferred embodiment of the present invention the timing of the arbitration means is controlled by a clock signal having a constant clock cycle and the arbitrating, between the request signals which are requesting access to resources having status signals indicating that they are capable of being accessed, to select one request signal occurs within a single clock cycle.

According to a second aspect of the present invention there is provided a method of arbitrating between a plurality of requests to access resources comprising the steps of:

receiving a plurality of request signals, wherein each request signal identifies the resource to which it is requesting 2 access; receiving status signals wherein each status signal identifies whether a resource is capable of being accessed; and arbitrating between request signals which are requesting access to resources having status signals indicating that they are capable of being accessed, to select one request signal to access resources comprising, being being accessed to inhibit the processing of said second request signal.

For a better understanding of the present invention and to understand how the same may be brought into effect, reference will now be made by way of example only to the following Figures in which:

Figure la illustrates a system utilising a modular architecture, having a hierarchical structure; Figure 1b illustrates in further detail a module of the hierarchical structure of the system of Figure la; Figure 2 illustrates in further detail one of the modules of the system illustrated in Figure la; Figures 3a to 3e illustrate the protocol which is used to communicate between the different levels of hierarchy within the system illustrated in Figure la; Figure 4 illustrates the input and output signals of the module illustrated in figure 2; Figure 5 illustrates a circuit implementation of the switches illustrated in Figures la, 1b and 2; Figure 6a illustrates one implementation of the memory circuitry 112 illustrated in Figure 5; Figure 6b illustrates one implementation of the arbitration circuit 110 illustrated in Figure 5; Figure 7 illustrates a system utilising a routing system; Figure 8a illustrates a cable, terrestrial or satellite communication system including a set-top box; Figure 8b illustrates a transport stream; Figure 9 illustrates a programmable transport interface (PM suitable for use in the set-top box of the system of Figure 3 8a; Figure 10a illustrates a source decoder having an architecture similar to that illustrated in Figure la; and Figure 10b illustrates a source decoder having an architecture similar to that illustrated in Figure 7.

Figure la illustrates an electrical system for sharing a resource 3. Although a single resource is shown it should be borne in mind in the following that the resource 3 may be representative of a plurality of separate resources. The system is modular, having as interconnected modules a first functional element 7, a second functional element 9 and the resource 3 and has a hierarchical architecture. The resource 3 may be for example static RAM, dynamic RAM, or an interface to external memory. The f irst functional element 7 may be a CPU and the second functional element 9 may be a dedicated controller. A bus 5 interconnects the modules and allows either one of the first or second functional elements to access the resource 3. The second functional element 9, is multifunctional and comprises as separate modules a switch 11, a third functional element 19, a fourth functional element 21 and a fifth functional element 23. The third and fifth functional elements may be processors. The switch 11 is connected to the bus 5 and to the third functional element 19 via a first interconnect 13, to the fourth functional element 21 via a second interconnect 15 and to the fifth functional element 23 via a third interconnect 17. The switch 11 receives requests to access the resource 3 from the third, fourth and fifth functional elements. The switch 11 arbitrates between the requests and selects one. The switch then presents the selected request to the bus 5 as if it were the appropriate one of the third, fourth, or fifth functional elements. The second functional element 9 can thus assume at any one time the function of any one of the third, fourth, or fifth functional elements.

The first functional element 7 and the second functional element 9 are directly connected to the resource 3 via the bus 5, and 4 both occupy a first level of hierarchy. The second functional element 9 has within it two levels of hierarchy. The highest level, the first level, is occupied by the switch 11 and the lower level, the second level, is occupied by the third, fourth and fifth functional elements 19, 21 and 23. The switch 11 arbitrates the access by any one of the third, fourth or fifth functional elements 19, 21 or 23 to the first level of hierarchy.

Figure 1b illustrates in more detail the fourth functional element 21. This element includes a switch 25 which is connected to switch 11 via the second interconnect 15. A plurality of functional elements 29:,, 2921... 29n make connection to the switch 25 via their respective interconnects 271, 2721... 27n Each of the functional elements 29:,, 2921... 29n may be singular in function, representing a single level of hierarchy, or may be multifunctional having multiple levels of hierarchy within them. The fourth functional element 21 has in this example two levels of hierarchy within it. The upper level of hierarchy, the second level, is occupied by the switch 25. The lower-level of hierarchy, the third level, is occupied by the functional elements 29,, 2921... 29,. The switch 25 occupies the same level of hierarchy within the system 1 as the third functional element 19 and the fifth functional element 23. The switch 25 operates in the same manner and is structurally similar to switch 11 and arbitrates the access of any one of the functional elements 291, 292... 29, in the third level of hierarchy to the second level of hierarchy.

Each of the modules in the first level of hierarchy of the system 1 make direct access to the bus 5. These elements can access the resource 3 via the bus 5 in the shortest possible time, that is with the least latency. The access of these elements to the resource 3 can be controlled by an arbiter (not shown). The arbiter receives requests for access to the bus from the switch 11 and the functional element 7. The arbiter determines which of these two competing elements should have priority of access to the bus on the basis of a predetermined criterion or predetermined criteria, such as the type of resource each is trying to access via the bus, the operational status of the resources each element is trying to access, and whether the accesses from the switch 11 or first functional element 7 are given priority. The third functional element 19, the fifth functional element 23 and the switch 25 have access to the resource 3 by first gaining access to the output of the switch 11 and have a delay in accessing the resource 3 when compared to those elements in the first level of hierarchy. The functional elements 291, 2921... 29, in the third level of hierarchy compete for access to the switch 25 (in the second level of hierarchy). When one of the functional elements 291, 292... has access to the switch 25, the switch 25 requests access to the switch 11 (in the first level of hierarchy). The switch 11 and functional element 7 then compete for access to the resource 3. Each of the functional elements 291, 2921... in the third level of hierarchy has a greater delay or latency, in accessing the resource 3 than the elements in the first level of hierarchy or in the second level of hierarchy.

The system 1 illustrated in Figure la provides for the simple design of a system architecture. Those functional elements which require access to a resource 3 with the smallest possible latency are connected directly to the bus 5 and occupy the first level of hierarchy. Those functional elements which do not require the shortest possible delay in accessing the resource 3 may occupy the second or third level of hierarchy. In designing a system, a functional element can be placed in a particular level of hierarchy depending upon the maximum latency the system can stand in that functional element accessing the resource 3. Those functional elements which require a priority of access to the resource 3 via the bus 5 may occupy the first, second, third or any other hierarchical level of the system 1. However, the arbitration of their access to the resource 3 via the intervening hierarchical levels of the system 1 (if any) will be strongly arbitrated in their favour. For example if the functional element 291 in the third level of hierarchy was required to have 6 priority of access to the resource 3, the switch 25 would preferentially allow that functional element to access the switch 25 in the second level of hierarchy. The switch 11 would arbitrate preferentially in favour of the switch 25 thereby allowing the request from the switch 25 to have access to the first level of hierarchy. The functional element 29, thereby has preferential access to the first level of hierarchy. The switch 11 will then be given priority of access to th e resource 3 via bus 5. Consequently the function element 291 would have priority of access to the resource 3 over and above any of the other functional elements. It is therefore possible by controlling at each of the levels of hierarchy the arbitration of the requests for access to the resource 3, to control the priority of access which a functional element has to the resource 3.

The communication between the different levels of hierarchy is controlled by the same protocol.

Figure 2 illustrates a switch for arbitrating the access of elements in a lower-level of hierarchy to a higher level of hierarchy. The switch has a requester 31, a receiver 41 and an interconnect 51 connecting the requester 31 and the receiver 41. The requester 31 has a first requesterinterface 33, which interfaces to a higher level of hierarchy, and a second requester- interface 35, a third requester- interface 37 and a fourth requester-interface 39 which interface to a lower-level of hierarchy. In the example of Figure la in relation to switch 11, the first requester- interface 33 makes connection to the bus 5, and the second, third and fourth requester-interfaces 35, 37 and 39 respectively make connection to the third, fourth and fifth functional elements 19, 21 and 23 via the first, second and third interconnects 13, 15 and 17. The receiver 41 has a first receiver-interface 49, which interfaces to a higher level, and second receiver- interface 43, a third receiverinterface 45 and fourth receiver- interface 47 which interface to a lower-level. In the example illustrated in figure la in relation to switch 11, the first receiverinterface 49 makes connection to the bus 5, 7 the second, third and fourth receiver- interfaces 43, 45 and 47 respectively make connection to the third, fourth and fifth functional elements 19, 21 and 23 via the first, second and third interconnects 13, 15 and 17. The requester 31 and the receiver 41 communicate with each other via the interconnect Si.

The number of utilised receiver-interfaces which interface to a lowerlevel and utilised requester- interfaces which interface to a lower-level, may differ in number from the three illustrated in Figure 2.

Referring to Figure 2 the requester 31 requests access to a higher level of hierarchy within the system 1 via the first requester- interface 33. This request is made in accordance with a defined protocol for communicating between the different levels of hierarchy within the system. If the requester 31 has multiple requester-interfaces which interface to a lower-level, then the requester 31 will arbitrate to determine which of these interfaces will be given access to the first requester interface 33. The receiver 41 also allows a higher level of hierarchy of the system to access a lower-level of hierarchy. The receiver 41 communicates with the requester 31 to determine whether the access from the higher level of hierarchy is in response to a request made by one of the requesterinterfaces to a lower-level. If this is the case the receiver 41 will determine to which of the second, third or fourth receiver- interfaces 43, 45,47 the access from the higher level is directed.

Figure 4 schematically illustrates the signals produced at and received at a switch, such as the switch 25, as it receives communications from the level of hierarchy above and below it and as it communicates to the level of hierarchy above it and below it. A second level of hierarchy is occupied by an upper-level requester 31:, interconnected to an upperlevel receiver 411 by an interconnect 51,. The upper-level requester 311 has a first requester- interface 33,, interfacing to a first level and a second requester- interface 351. interfacing to the third level.

c 8 Only one interface from the second level to the third level is shown in this figure, for the purposes of clearly illustrating the signals. The upper-level requester 31, would in practice have a plurality of such interfaces as shown in figure 2a. The upperlevel receiver 411 has a first receiver-interface 49,, interfacing to the first level and a second receiver-interface 431 interfacing to the third level. Also illustrated is the third level of hierarchy which is occupied by a lower-level requester 31, and a lower-level receiver 412 connected by an interconnect 512. The lower-level requester 312 has a first requester-interface 33. which is connected to the second requester- interface 351 of the upper- level requester 311, The lower-level receiver 412 has a first receiverinterface 492 which is connected to the second receiver- interface 431 of the upper-level receiver 41..

The upper-level requester 311 receives, at its second requesterinterface, a first requester-input signal 80 produced at the first requesterinterface 332 of the lower-level requester 312.

The upper-level requester 31,. produces, from its first requesterinterface 331, a first requester-output signal 70. The upperlevel requester 311 receives as an input at its first requesterinterface 33, a second requesterinput signal 71. The upperlevel requester 311 produces as an output from its second requester- interface 351 a second requester- output signal 81 which is received as an input at the first requester- interface 332 Of the lower-level requester 312. The upper-level receiver 411 receives as an input to its first receiver- interface 49, a first receiver-input signal 90. The upperlevel receiver 411 produces as an output from its second receiver- interface 431 a first receiver-output signal 100, which is received as an input at the first receiver- interface 492 of the lower-level receiver 412.

The first requester-input signal 80 may include a number of separate signals, including an input request signal 82, an input read-not-write signal 83, a requester-input address signal 85, a requester-input data signal 86, and a requesterinput ID signal 9 87. The first requester-output signal 70 may include a number of individual signals, including: an output request signal 72, an output read-not-write signal 73, a requester-output address signal 75, a requester-output data signal 76, and a requesteroutput ID signal 77. The first receiver-input signal 90 may include a number of individual signals, including: an input grant signal 91, an input valid signal 92, a receiver-input data signal 94, and a receiver-input ID signal 95. The first receiver-output signal 100 may include a number of individual signals, including: an output grant signal 101, and output valid, signal 102, a receiver-output data signal 104, and a receiveroutput ID signal 105.

The request signals (output request signal 72 and input request signal 82), the readnot-write signals (output read-not-write signal 73 and input read-not-write signal 83), the grant signals (input grant signal 91 and output grant signal 101), the valid signals (input valid signal 92 and output valid signal 102) and the requester-output address signal 75 are used in the protocol for communicating between the different levels of hierarchy within the system. The operation of this protocol will be explained later in more detail in relation to Figures 3a to 3e. The address signals (requester-output address signal 75, requester-input address signal 85, receiver-output address signal 103, and receiver-input address signal 93) and data signals (requester- output data signal 76, requester-input data signal 86, receiver-output data signal 104 and receiver-input data signal 94) are used to direct and transmit data between levels of hierarchy to resources. The second requester-input signal 71, the second requester-output signal 81, and the ID signals (requester -output ID signal 77, requesterinput ID signal 87, receiverinput ID signal 95 and receiver-output ID signal 105) may be utilised to route a signal, returning from a resource, through the hierarchical system to a functional element.

Figures 3a to 3e illustrate the communication protocol which is implemented in the communication between one level of hierarchy I 1 of the system and another level of hierarchy of the system. The outputs from each functional element and switch 11, 25 are in accordance with this protocol. The timing diagrams include a clock signal 300, a request signal 302, an address signal 304, a grant signal 306, an output data signal 312, a valid signal 310 and an input data signal 322. The request signal 302, the address signal 304, and the output data signal 312 are produced as output signals from the first requester- interface 33 of a requester 31. For the lower-level requester 312 of figure 4, these signals are respectively the input request signal 82, the requester-input address signal 85 and the requester-input data signal 86. For the upper- level requester 31, of figure 4, these signals are respectively the output request signal 72, the requester- output address signal 75 and the requester- output data signal 76. The grant signal 306, the valid signal 310 and the input data signal 322 are received as input signals at the first receiver- interface 49 of the receiver 41. For the lower-level requester 312 of figure 4, these signals are respectively the output grant signal 101, the output valid signal 102 and the receiveroutput data signal 104. For the upper-level requester 311 of figure 4, these signals are respectively the input grant signal 91, the input valid signal 92 and the receiver-input data signal 94.

Figure 3a illustrates the protocol used for a requester 31 to request access to a resource 3 at a higher level of hierarchy within the system so that it may write to that resource. The requester 31 requests access to a higher level of hierarchy to perform a write operation by asserting simultaneously the request signal 302, the output data signal 312 and the address signal 304 which indicates the address at which the write operation is to be performed. If the next highest level of hierarchy grants access to the requester 31 to its level, it asserts the grant signal 306 which is returned to the receiver. In the example illustrated in Figure 3a the grant signal 306 is returned by the higher level of hierarchy of the system immediately. The request signal 302, address signal 304 and data signal 312 are no longer 11 asserted after the receipt of the asserted grant signal 306. The valid signal 310 is returned to the receiver 41 when the write operation has been completed at the resource. In the time between the return of an asserted grant signal 306 and the return of asserted valid signal 310 the requester may make further and different requests to the higher level of hierarchy.

Figure 3b illustrates the protocol used for a requester 31 to request access to a resource 3 at a higher level of hierarchy within the system so that it may read at that, resource. The requester 31 requests access to a higher level of hierarchy to perform a read operation. It asserts simultaneously the request signal 302 and the address signal 304 which indicates the address at which the read operation is to be performed. If the next highest level of hierarchy grants access to the requester 31 to its level, it asserts the grant signal 306 which is returned to the receiver. In the example illustrated in Figure 3a the grant signal 306 is returned by the higher level of hierarchy of the system immediately. The request signal 302 and the address signal 30 are no longer asserted a predetermined time (one clock cycle) after the receipt of the asserted grant signal 306. The request then moves upwards through the levels of hierarchy within the system until it accesses the resource 3 and reads the requisite address at that resource. The read data is returned through the levels of hierarchy to the requester 31. The read data is represented in Figure 3b as the input data signal 322. The input data signal 322 is returned to the receiver 41 with the valid signal 310 after the write operation has been completed at the resource. The return of the valid signal 310 indicates that the input data signal 322 is valid. In the time between the return of an asserted grant signal 306 and the return of asserted valid signal 310, the requester may make further and different requests to the higher level of hierarchy.

Reference is now made to Figure 3c which illustrates the signals produced by a requester 31 in order to perform a pipelined write operation to a resource 3. In a pipelined operation a continuous 1 12 series of transactions are effected. In the example of Figure 3c a series of two transactions is made. The reference numerals of Figure 3c where they correspond with those of Figure 3a represent the same signals. As previously the request signal 302, the address signal 304 and the write data signal 312 are asserted at the same time and are supplied to the higher level hierarchy. The signals of Figure 3c are different from those of Figure 3a in that the request signal 302 is asserted for multiple (two) clock cycles and in that the address signal 304 and the write data signal 312 are each composed of multiple portions. The address signal 304 has a first address portion 404a containing a first address and a second address portion 404b containing a second address. The write data signal 312 is composed of a first data portion 412a and a second data portion 412b. The first data portion 412a is to be written to the first address and the second data portion 412b is to be written to the second address. The grant signal 306 is also asserted for two clock cycles. The first data portion 412a and the first address portion 404a are asserted until one clock cycle after the start of the asserted grant signal 306. The second data portion 404b and the second address portion 404b are asserted for one clock cycle after the first data portion 412a and the first address portion 404a are no longer asserted. The valid signal 310 is asserted by the higher level of system hierarchy when the first and each write operation is completed at the resource. Consequently, a continuous series of requests can be made while previously made requests remain outstanding. Each request in the series is independent of the completion of accesses requested previously.

Figure 3d illustrates a pipelined read operation. In a pipelined operation a continuous series of first transactions are effected. All the reference numerals in Figure 3d which correspond to those in Figure 3b represent the same signals. The signals of Figure 3d differ from those of Figure 3b in that the request signal 302 is asserted for two clock cycles and in that the address signal 304 has two portions, a first address portion 404a and a second address portion 404b. As previously the request signal 302 and 13 the address signal 304 are asserted at the same time and are supplied to the higher level of hierarchy. The higher level of hierarchy then returns a grant signal 306 when it grants access to its level to the requester of the lower-level. The grant signal 306 in this instance is two clock cycles. The f irst address portion 404a is asserted until one clock cycle after the start of the asserted grant signal 306. The second address portion 4 04b is asserted for one clock cycle after the first address portion 404a is no longer asserted. When the read data is to be transferred from the higher level of system architecture to the receiver 41 in the lower-level the valid signal 310 is asserted as before. However on this occasion the valid signal is two clock cycles long. As previously, while the valid signal 310 is asserted the input data signal 322 transfers the read data from the higher level of system architecture to the receiver in the lower-level of system architecture. The input data signal 322 has a first input data portion 422a and a second input data portion 422b. The first input data portion 422a of the read data signal is the data read from the address associated with the first address portion 404a of the address signal 304. The second input data portion 422b of the read data signal is the data read from the address associated with the second address portion 404b of the address signal 304. Consequently a continuous series of requests can be made while previously made requests remain outstanding. Each request in the series is independent of the completion of accesses requested previously.

The pipelined request signal 302 and pipelined address signal 304 in Figure 3c and 3d are produced by a requester 31 which receives the address signal 304 from a single functional element in the level of hierarchy below the requester 31.

Reference will now be made to Figure 3e to illustrate how a requester 31 and receiver 41 may mix, shuffle or interleave requests received from the different functional elements in the level of hierarchy below them. The reference numerals of Figure 3e where they correspond to those of Figures 3a to 3d represent 14 the same type of signal. Where no subscript is used it indicates that the signal is output from the requester 31 to a higher level of hierarchy. Where a subscript is used in respect of a reference numeral it indicates that the signal is received from or supplied to a functional element in the level of hierarchy below that of the requester 31 and receiver 41. A subscript 1 indicates that the signal is derived from or supplied to a first one of the functional elements in a level of hierarchy below that of the requester 31. A subscript 2 indicates that the signal is derived from or supplied to a different functional element in the level of hierarchy below that of the requester 31.

The receiver 31 receives at the second requester-interface 35 a burst request signal 3021 and an associated address signal 304, which has first, second, third and fourth address portions 4041,, 4041b, 404,, and 4041d. A flag is provided in the request signal to indicate that it is a burst request signal requesting a burst access. A burst access is a succession of accesses to the same resource. The requester 31 also receives at its third requesterinterface 37 a burst request signal 3022 and an associatedaddress signal 3042 having first, second, third and fourth portions 4042,, 4042b, 4042, and 4042d. A flag is provided in the request signal to indicate that it is a burst request signal requesting a burst access. A burst access is a succession of different accesses to the same resource. The second requesterinterface 35 and third requester-interface 37 receive the burst request signals 3021 and 3022 at the same time. The requester 31 must therefore arbitrate between these two requests to determine which of the requests made will be presented at the first requester- interface 33. The receiver 31 may arbitrate in favour of the second requester- interface or the third requesterinterface. If arbitration is in favour of the second requesterinterface 35 the grant signal 306, is asserted high at the second requester- interface 35. If arbitration is in favour of the third requester- interface 37 the grant signal 3062 is asserted high at the third requester- interface 37. The address signal and request signals supplied to the second requester-interface 35 are held until the grant signal 306, is asserted high. The address signal and request signal supplied to the third requesterinterface 37 are held until the grant signal 3062 is asserted high. When the receiver arbitrates in favour of a burst request signal that is requesting a burst access to a first resource", it prevents for the duration of the burst request signal, the receiver arbitrating in favour of any other request signal received which is requesting access to that first resource, but remains responsive to other request signals received by the receiver which are not requesting access to that first resource. These other request signals may be normal request signals or burst request signals. Consequently, the switch may enable a burst of accesses to the first resource, while interleaving those accesses with accesses to a resource other than a first resource.

In summary, the circuitry in the level below, compete to perform transactions with the switch. Each of the circuitry in the level below the switch requests to transact with the switch until the switch arbitrates in its favour and transacts with it. The switch can therefore shuffle the requests presented at the second and third requester interfaces to provide requests at its first requester interface to the higher level of hierarchy. While a burst access is being carried out at a first resource, the switch will not shuffle in other requests to access that resource.

Figure 5 illustrates circuitry suitable for implementing the switch 11 illustrated in Figures la, 2a and 4 and like numerals designate like features. The requester 31 has in addition to the first, second, third and fourth requester-interfaces 33, 35, 37 and 39, arbitration circuitry 110, memory circuitry 112, a first control switch 114 which is a multiplexer, and a register 116. The receiver 41 has in addition to the first, second, third and fourth receiver-interfaces 49, 43, 45 and 47, a second control switch 118 which is a demultiplexer. The second, third and fourth requester-interfaces 35, 37 and 39 receive respectively as the first requester-input signal 80 a requester-input signal 801 from the third functional element 19, a requester-input 1 16 signal 802 from the fourth functional element 21 and a requesterinput signal 803 from the fifth functional element 23. The requester-input signal 801 is supplied to a first input of the first control switch 114 and to a first input of the arbitration circuitry 110. The requester- input signal 802 is supplied to a second input of the first control switch 114 and to a second input to the arbitration circuitry 110. The requester-input signal 803 is supplied to a third input of the first control switch 114 and to a third input to the arbitration circuitry 110. The arbitration circuitry 110 provides a signal to the first control switch 114 which controls which of the first, second or third inputs to the first control switch 114 will be presented as an output of the first control switch 114. This control signal is also used as the requester- output ID signal 77 and is supplied to the first control switch 114, to memory circuitry 112 and it is introduced into the output signal from the first control switch 114 to replace the requester-input ID signal 87 and thereby to produce the first requesteroutput signal 70. In the first requester- output signal 70, the requester -output ID signal 77 is produced by the arbitration circuitry 110 whereas the output request signal 72, the output read-not-write signal 73, the requester-output address signal 75, and the requesteroutput data signal 76 are, respectively, the same as the input request signal 82, the input read-not- write signal 83, the requester-input address signal 85, and the requester- input data signal 86. The first requester-output signal 70 is presented as an input to the register 116. The register 116 latches the first requester- output signal 70 providing it to a higher level of hierarchy within the system under control of the input grant signal 91.

The second requester-input signal 71 is supplied by the first requesterinterface 33 to the arbitration circuitry 110 and to the second, third and fourth requester-interfaces 35, 37 and 39. The second, third and fourth requester-interfaces 35, 37 and 39 respectively provide the received second requester-input signal 71 to the third, fourth and fifth functional elements as the 17 second requester-output signals 81,, 812, and 81_, The first receiver- interface 49 receives from a higher level the first receiver-input signal 90 and - supplies the input grant signal 91 to the register 116, the receiver-input data signal 94 to the second control switch 118, the input valid signal 92 to the memory circuitry 112 and the receiver-input ID signal 95 to the memory circuitry 112 and to the second control switch 118. The memory circuitry 112 produces the output valid signal 105 and the receiver-output ID signal 102, which are presented with the receiver-input data signal 94 at the input to the second control switch 118. The second control switch 118 has a single input and three outputs. Under the control of the receiverinput ID signal 95, the second control switch 118 diverts the signals received at its single input to a selected one of its outputs. The first, second and third outputs of the second control switch 118 are supplied respectively to the second, third and fourth receiverinterfaces 43, 45 and 47. The second, third and fourth receiverinterfaces are respectively connected to the third, fourth and fifth functional elements 19,21,23. The arbitration circuitry 110 supplies as the output grant signal 101 either the signal 1013. to the second receiver- interface 43, or the signal 101. to the third receiverinterface 45 or the signal 101. to the fourth receiver- interface 47. The signal output from the second control switch 118 and the output grant signal 101 produce the receiveroutput signal 100. The receiver-output signal 100 is presented to one of the third, fourth or fifth functional elements 19, 21 and 23 respectively as one of the signals 100,, 10021 or 1003. In the first receiver-output signal 100, the output grant signal is produced by the arbitration circuitry 110, the output valid signal 102 and the receiver-output ID signal 105 are produced by the memory circuitry 112, and the receiver-output data signal 104 is the same as the receiver-input data signal 94.

The operation of switch 11 will now be explained with reference to Figure 5. When the third functional element 19, the fourth functional element 21 or the fifth functional element 23 require 18 access to a higher level of hierarchy within the system they assert the first requester-input signals 80,, 802, and 803 respectively. The arbitration circuitry 110 receives the signals and in addition receives the second requester-input signal 71. on the basis of the received signals the arbitration circuitry 110 determines which of the third functional element 19, the fourth functional element 21 and the fifth functional element 23 should gain access to the level of hierarchy occupied by the switch 11. If the third functional element 19 gains access, the output grant signal 1011 would be asserted., If the fourth functional element 21 gains access, the output grant signal 1012 would be asserted. If the fifth functional element 23 gains access, the output grant signal 1013 would be asserted. At any one time only one of the output grant signals 1011, 1012, or 1013 is asserted and supplied to one of the third, fourth or fifth functional elements 19, 21, or 23. The arbitration circuitry thus provides for local arbitration. The arbitration circuitry 110 produces the requester- output ID signal 77. This signal controls the first control switch 114 and identifies which one of the third, fourth or fifth functional elements has gained access to the higher level and consequently which of the first requester-input signals 80,., 802. or 803 will be provided as an output from the first control switch 114. The requester-input ID signal 87 in the output signal from the first control switch 114 is replaced by the requester- output ID signal 77. The requester-input ID signal 87 is stored in the memory circuitry 112 in association with the requester-output ID signal 77 which has replaced it in the output signal from the first control switch 114. The first requester-output signal 70 is stored in the register 116.

The second requester-input signal 71 is asserted at the start of each clock cycle. That is it is asserted with a frequency equal to that of the clock signal 300 illustrated in Figures 3a to 3e. The requester-input signal 71 indicates the status of the resource(s) 3. That is it indicates whether the resource(s) 3 is capable of receiving and responding to an access. Each 19 resource may have an input register which asserts a flag when it is available. These flags will be provided at the start of each clock cycle as the second requester-input signal 71 to the requester 31 at the highest level of the hierarchy of the system.

The passage of the second requester-input signal 71 is not arbitrated and it proceeds directly to the second, third and fourth requester- interfaces 35, 37 and 39 and is in addition supplied to the arbitration circuitry 110. The signals indicating the status of the resource(s) 3 cascade through each of the levels of hierarchy of the system. 1 when a first receiver-input signal 90 is received at the first receiver- interface 49, it is in response to an access to a resource previously requested by one of the third, fourth or fifth functional elements 19, 21 or 23. Consequently, it is necessary to direct the first receiver-input signal 90 to the functional element which made the request to which that signal is a response. As previously described when the switch 11 makes a request, the requester-input ID signal 87 is replaced by the requester- output ID signal 77 and the signals are stored in association in the memory circuitry 112. When the higher level of hierarchy responds to the request, the receiver-input ID signal 95 returned by the higher level will be the same as the requester-output ID signal 77 provided to the higher level when the switch made the request. The memory circuit 112 accesses its stored information to retrieve the requester-input ID signal 87 associated with the requester-output ID signal 77 which is the same as the receiver-input ID signal 95. The memory circuitry outputs the receiver-output ID signal 105 with a value of the retrieved requesterinput ID signal 87 stored in the memory. The output valid signal 102 and the receiver-output ID signal 105 are presented with the input data signal 94 as an output signal from the second control switch 118. The receiver-input ID signal 95 identifies which one of the first, second or third receiverinterfaces to a lower-level 43, 45 or 47 should receive this signal and controls the switch accordingly. Consequently, the switch can have many outstanding requests in progress at one time. The order of accesses responsive to requests may be different to the order in which the requests were initiated.

The operation of the memory circuitry 112 will now be explained in further detail in relation to Figure 6a which illustrates the components of the memory circuitry 112. The memory circuit 112 includes decode and enable circuitry 130 a first-in/first-out (FIFO) memory 140, a second first-in/first-cut (FIFO) memory 142 and a third first-in/first-out (FIFO) memory 144. The memory circuitry 112 receives the requester- output ID signal 77 and the requester-input ID signal 87 at a first input 146. The memory circuitry 112 receives the input valid signal 92 and the receiver-input ID signal 95 at a second input 147. The memory circuitry 112 produces at an output 148 the output valid signal 102 and the receiver-output ID signal 105. The requester- output ID signal 77 and the receiverinput ID signal 95 are supplied as inputs to the decode enable circuitry 130. The requester-input ID signal 87 is supplied as a first input to each of the first, second and third FIF0s 140, 142 and 144. The input valid signal 92 is supplied as a second input to each of the FIF0s 140, 142 and 144 and is in addition supplied as the output valid signal 102. The decode and enable circuitry 130 produces a first enable signal 150 or a second enable signal 152 or a third enable signal 154. The first, second and third enable signals 150, 152 and 154 are received as a third input to the first, second and third FIF0s 140, 142 and 144 respectively. Each of the FIF0s has an output and the signal produced at the output of the FIF0s is supplied as the receiveroutput ID signal 105. The first FIFO 140 is associated with the third functional element 19. The second FIFO 142 is associated with the fourth functional element 21. The third FIFO 144 is associated with the fifth functional element 23. The requesteroutput ID signal 77 indicates which one of the third, fourth or fifth functional elements 19, 21 or 23 has been given access to the level of hierarchy of the system occupied by the switch 11. The decode and enable circuitry 130 asserts one of the first, second or third enable signals 150, 152 or 154 to enable the FIFO which is associated with that 21 functional element. The requester-input ID signal 87 is simultaneously asserted at the first input of each of the FIF0s 140, 142 or 144. The requester-input ID signal 87 causes a FIFO if enabled to be written to, with the value of the requesterinput ID signal 87 being stored therein. It will therefore be appreciated that the first FIFO 140 logs the values of the requester-input ID signal 87 supplied by the first requesterinput signal 80, in the order in which the first requester-input signals 80, have been given access to a higher level of hierarchy. The second FIFO 142 logs the values of the requesterinput ID signal 87 supplied by the first requester-input signal 802 in the order in which those signals have been given access to the higher level of hierarchy. The third FIFO 144 logs the values of the requester-input ID signal 87 provided by the first requesterinput signal 803 in the order in which those signals have been granted access to the higher level of hierarchy.

The receiverinput ID signal 95 when received by the memory circuitry 112 is decoded in the same manner as the requesteroutput ID signal 77 by the decode enable circuitry 130. If the first receiver-input signal 90 is to be supplied to the third functional element 19 then the first enable signal will be asserted. If the first receiver-input signal 90 is to be supplied to the fourth functional element 21 the second enable signal 152 will be asserted. If the receiver-input signal 90 is to be supplied to the fifth functional element 23 the third enable signal 154 will be asserted. The first, second and third enable signals 150, 152 and 154 respectively enable the first, second and third FIF0s 140, 142 and 144. The input valid signal 92 is supplied to the second input of the first, second and third FIF0s 140, 142 and 144. The input valid signal 92 causes a FIFO, if enabled, to be read from. The value read f rom the FIFO is provided as the receiver-output ID signal 105.

Figure 6b illustrates arbitration circuitry 110. The arbitration circuitry receives the first requesterinput signals 80,, 80. and 803 and the second requester-input signal 71 and produces the c 22 requester output ID signal 77 and an output grant signal 101., 1012 or 1013. The arbitration circuitry includes decision circuitry 200, first, second and third decision weighting circuitry 210, 220, 230, inhibition circuitry 240, first, second and third gates 241, 242 and 243.

The f irst requester-input signals 801, 802 and 803 are respectively supplied to the f irst, second and third decision weighting circuitries 210, 220 and 230 via first and fourth gates 241 and 281, second and fifth gates 242 and 282 and third and sixth gates 243 and 283.

The inhibition circuitry 240 receives the requester-input address signal 85 of the first requester-input signals 801, 802 and 803 and second requester-input signal 71 and produces first, second and third suspension signals 204, 205, 206 which are respectively supplied to the first, second and third gates 241, 242 and 243. The first, second and third suspension signals control the first, second and third gates 241, 242 and 243 and consequently the reception of the first, second and third first requester-input signals by the first, second and third decision weighting circuitries 210, 220 and 230.

The inhibition circuitry 240 comprises first, second and third filter circuits 244, 245 and 246. The first filter circuitry 244 comprises decode circuitry and logic circuitry. The decode circuitry receives the requester-input address signal 85 of the first requester-input signal 801. It decodes the most significant bits (or any particular predetermined bits) of the address signal and provides a signal to the logic circuitry which identifies the resource addressed by the requester-input address signal 85. The logic circuitry in addition receives the second requesterinput signal 71. The requester-input signal 71 comprises a plurality of status signals, wherein each of the signals indicates the operational status of a resource. If any particular resource is unable to be accessed then this will be indicated by its associated status signal in the requester-input 23 signal 71. The logic circuitry on receiving the second requester-input signal 71 and the output from the decode circuitry determines whether the resource addressed by the requester-input address signal of the first requester-input signal 80, is addressing a resource which is not available for access. If the addressed resource is not available for access the logic circuitry asserts the first suspension signal 204 which disables the first gate 241 and prevents the first requesterinput signal 801 reaching the first decision weighting circuitry 210. The second filtration circuitry 245 comprises logic circuitry and decode circuitry and receives the second requesterinput signal 71 and the requester-input address signal 85 of the first requester-input signal 80.. The most significant bits of the requester-input signal are decoded and if the resource addressed is unavailable for access the logic circuitry asserts the second suspension signal 205 to disable the second gate 242 and prevent the first requester-input signal 802 reaching the second decision waiting circuitry 220. The third filtration circuitry 246 contains logic circuitry and decode circuitry and it receives the second requester-input signal 71 and the requester-input address signal 85 of the first requester-input signal 803. If the resource addressed by the requester- input address signal 85 is unable to be accessed then the third suspension signal 206 is asserted and the third gate 243 is disabled preventing the first requester-input signal 803 reaching the third decision weighting circuitry 230. As previously mentioned, the second requester-input signal 71 is asserted at the start of each clock cycle. Consequently, the filtration circuits 244, 245 and 246 are activated at the beginning of each clock cycle on the receipt of the second requesterinput signal 71 and if any one of the first, second or third suspension signals 204, 205, 206 are asserted in response to the receipt of the second requester-input signal 71 they remain asserted until the next clock cycle. The simple decoding and logic circuitry required for the operation of the filtration circuits allows the very rapid processing of the requester-input address signals 85 and, if necessary, the production of suspension signals 204, 205 24 and 206. Consequently, the inhibition circuitry 240 prevents any one of the first request-input signals 80,., 802 and 80, which are requesting access to a resource which is unavailable for access from reaching the decision weighting circuitry 210, 220 and 230, thereby reducing the processing load on the weighting circuitries 210, 220 and 250.

The first, second and third burst access circuitry 250, 260 and 270 operate to allow the request of a burst access to a first resource to be shuffled with the request to a second different resource, as described in relation to Figure 3e. The first burst access circuitry 250 is connected to receive the input request signal 82 and requester-input address signal 85 of the first requester-input signal 801 and the output grant signal 1011 if asserted. The first burst access circuitry 250 produces a fourth suspension signal 251 which is used to deactivate the fourth gate 281 and prevent the first requester-input signal 80 reaching the first weighting circuitry 210 and a first interconnection signal 252 which is provided to a bus 280 and thence to the second and third burst access circuitry 260 and 270. The second burst access circuitry 260 is connected in a analogous manner receiving signals from the first requester-input signal 802 and the output grant signal 1012 and produces a fifth suspension signal 261 for controlling the fifth gate 282 and a second interconnection signal 262 onto the bus 280. The third burst access circuitry 270 is connected in an analogous manner receiving signals from the first requester-input signal 80. and the output grant signal 1013 and produces a sixth suspension signal 271 for controlling the sixth gate 283 and a third interconnection signal 272 for provision on the bus 280.

The opera-Lion of the first, second and third burst access circuitry 250, 260 and 270 will now be explained on the assumption that the first requester-input signal 801 has requested a burst access and has been granted said access by the arbitration circuitry 110. The input request signal 82 of the first requester-input signal 801 contains a flag indicating that the request is for a burst access at a resource represented by the requester-input address signal 85 of the first requesterinput signal 80, The output grant signal 101, will be asserted high indicating that the arbitration circuitry has granted the request for burst access. The other output grant signals 101. and 1013 will not be asserted. The first burst access circuitry 250 responds to its input signals to produce a fourth suspension signal 251 which controls the fourth gate 281 to allow the first requester-input signal 80, to be received at the first weighting circuitry 210 for the duration of the burst access. The first burst access circuitry 250 also produces a first interconnection signal 252 which indicates to the second and third burst access circuitry 260 and 270 that a burst access has been granted and which indicates the resource at which the burst access has been granted. Subsequently, for the duration of the burst access, the second and third burst access circuitry 260 and 270 are responsive to the first interconnection signal received respectively as the second interconnection signal 262 and third interconnection signal 272 from the bus 280 to prevent the first requester-input signal 802 and 80. reaching the second or third weighting circuitries 220 and 230 if they are addressing the resource at which a burst access has been granted. For example, the second burst access circuitry 260 compares the identification of the resource at which a burst access has been granted supplied as second interconnection signal 262 with the identity of the resource addressed by the requester-input address signal 85 of the first requester-input signal 802. If the second burst access circuitry finds identity between these resources it asserts the fifth suspension signal 261 causing the fifth gate 282 to prevent the passage of the first requester-input signal 80. to the second weighting circuitry 220. When the burst access has finished, the first interconnection signal 252 is disabled and the first, second and third burst access circuitry 250, 260 and 270 return to their normal state in which the fourth, fifth and sixth suspension signals 251, 261 and 271 are such that the fourth fifth and sixth gates 281, 282 and 283 are conductive allowing the first requesterinput signals to reach the weighting 26 circuitries.

Each of the first, second and third decision weighting circuitries 210, 220 and 230 comprise first and second determinators 214 and 216 and a combiner 218 for combining the outputs from the first and second determinators. The operation of the first, second and third decision weighting circuitry are similar and only the operation of the first decision weighting circuitry will be described.

The first determinator 214 receives as inputs the address signal 85, the requester-input ID signal 87 and the input read-not-write signal 83 and provides an output signal 215. The first determinator 214 stores a value indicating to which of the first, second or third inputs to the arbitration circuitry it is connected. The first determinator uses this value by itself, or in combination with the requester-input ID signal 87 to identify the functional element from which a request has been received. It uses the input read-not-write signal 83 to determine the type of operation which has been requested, and the requester-input address signal 85 to determine at which resource the access has been requested. The first determinator 214 uses this information to assign a particular priority to the access which has been requested. It produces an output signal 215 which reflects this priority. The higher the priority the greater the value of the output signal.

The second determinator 216 receives the input request signal 82 and the output grant signal 101 and produces an output signal 217. It determines how long an access has been requested without being granted. A counter counts the number of clock cycles for which the input request signal 82 has been asserted and the counter is reset by the receipt of the input grant signal 1011 or a change in the request signal 82. The second determinator 216 produces an output signal 217 which increases in value as the count in the counter (timed from the last granted access) increases. This allows the requests received at the different 27 requester interfaces of the switch to be shuffled and intermittently presented to the next level of hierarchy. The operation of the second determinator 216 may optionally be disabled.

The combiner 218 combines the signals from the first and second determinators and the fourth decision weighting circuitry to produce the first weighting signal 201. The combiner multiplies the signals it receives to produce the first weighting signal 201. 1 The decision circuitry 200 receives first, second and third weighting signals 201, 202 and 203 from the first, second and third decision weighting circuitry 210, 220, and 230. The decision circuitry 200 produces a requester output ID signal 77 and asserts one of the output grant signals 1011, 1012, and 1013 as an output from the arbitration circuitry.

The decision circuitry 200 determines which of the first, second and third weighting signals 201, 202 and 203 is the largest. If the first weighting signal 201 is the largest the output grant signal 101, is asserted and the grant signals 1012 and 1013 are disasserted and the two bit requester output ID signal 77 is set to 0 1. If the second weighting signal 202 isthe largest the grant signal 1012 is asserted and the other grant signals are disasserted and the two bit requester output ID signal 77 is set to 1 0. If the third weighting signal 203 is the largest the output grant signal 101. is asserted and the other grant signals are disasserted and the two bit requester output ID signal 77 is set to 1 1.

The arbitration circuitry 110 after receiving the first requester-input signals 801, 802 and 803, decodes and arbitrates those signals within a single clock cycle to produce a requesteroutput 10, signal 77 and output grant signal 101.

Figure 7 illustrates an electrical system for sharing a resource 28 3. Where references in Figure 7 are the same as those in Figure la they relate to the same structural or functional features. The system is modular having as interconnected modules a first functional element 7, a second functional element 9, a routing system 701, and a resource 3. The routing system 701 replaces the bus 5 in figure la. The resource 3 includes first, second, third and fourth resources 706, 708, 710 and 712. The f irst functional element 7 is connected to the routing system 701 via interconnect 703. The second functional element 9 is connected to the routing system 701 via interconnect 705. Each of the first, second, third and fourth resources 706, 708, 710 and 712 are connected to the routing system 701 via the respective interconnects 727, 729, 731 and 733. The routing system 701 controls the access of the first functional element 7 and the second functional element 9 to each of the first, second, third and fourth resources 706, 708, 710 and 712.

The components of the routing system 701 are also illustrated in Figure 7. The routing system includes a first decoder 714, a second decoder 716, a third decoder 718, and first, second, third and fourth switches 720, 722, 724 and 726. The first decoder 714 has a first input/output interface 740 connected to the interconnect 703, a second input/output interface 741 connected to an interconnect 707 and a third input/output interface 742 connected to an interconnect 709. The second decoder 716 has a first input/output interface 743 connected to the interconnect 705, a second input/output interface 744 connected to an interconnect 711, and a third input/output interface 745 connected to an interconnect 713. The first switch 720 has a first input/output interface 746 connected to the interconnect 707, a second input/output interface 747 connected to the interconnect 711 and a third input/output interface 762 connected to the interconnect 727. The third decoder 718 has a f irst input/output interface 748 connected to the interconnect 709 and a second input/output interface 749 connected to the interconnect 713, third, fourth, fifth, sixth, seventh and eighth input/output interfaces 750, 751, 752, 753, 754, 755 respectively make 29 connection to interconnects 715, 717, 719, 721, 723, and 725. The second switch 722 has a first input/output interface 756 connected to the - interconnect 715, a second input/output interface 757 connected to the interconnect 717 and a third input/output interface 763 connected to the interconnect 729. The third switch 724 has a first input/output interface 758 connected to the interconnect 719, a second input/output interface 759 connected to the interconnect 721 and a third input/output interface 764 connected to the interconnect 731. The fourth switch 726 has a first input/output interface 760 connected to the interconnect 723, a second input/output interface 761 connected to the interconnect 725 and a third input/output interface 765 connected to the interconnect 733. The interconnects illustrated in Figure 7 carry signals in both directions in the same manner as the interconnects of Figure la. The first and second decoders 714 and 716 decode the signal provided at the first input/output interfaces 740 and 743. if the signal received at the first input/output interface is addressed to the first resource 706 it is provided at the second input/output interface 741, 744, otherwise the signal is presented at the third input/output interface 742, 745. The third decoder 718 decodes the signal received at its first input/output interface 748 and provides it at its third, fifth or seventh input/output interface 750, 752, 754 respectively depending on whether that signal is addressed to the second, third or fourth resource 708, 710, or 712. The signal received at the second input/output interface 749 of the third decoder 718 is provided at the fourth, sixth or eighth input/output interface 751, 753, 755 of the third decoder 718 respectively depending on whether that signal is addressed to the second, third or fourth resource 708, 710 or 712. Each of the first, second, third and fourth switches 720, 722, 724 and 726 arbitrate between the signals received at their first input/output interface and their second input/output interface and provide one of those signals at the third input/output interface.

The switch 11 illustrated in Figure 2a and Figure 5 is suitable for use as any one of the first, second, third or fourth switches 720, 722, 724 or 726. In this context, the first input/output interfaces of the switches each have a second requester-interf ace 35 in combination with a second receiver- interface 43, the second input/output interfaces of the switches each have a third requester- interface 37 in combination with a third receiverinterface 45, the third input/output interfaces of the switches each have a first requester-interface 33 in combination with a first receiver-interface 49 Each of the first, second, third and fourth resources 706, 708, 710 and 712 may have a structure similar to that of the third functional element 19 illustrated in Figure 2b. Each of the resources will therefore have functional circuitry 57, a requester 31 and a receiver 41. The requester and receiver of each resource via their first requester-interface 33 and their first receiver- interface 49 make respective connection to the first requester-interface 33 and first receiver-interface 49 of the first, second, third and fourth switches.

The first functional element 7 and the second functional element 9 may also have circuitry similar to that illustrated in Figure 2b. The first decoder 714 and third decoder 718 then connect respectively the first requester-interface 33 and first requester-interface 49 of the first functional element 7 to the second requester-interface 35 and second receiver-interface 43 of the first input/output interface 746, 756, 758, 760 of any one of the first, second, third, or fourth switches. The second decoder 716 and the third decoder 718 connect respectively the first requester interface 33 and first receiver interface 49 of the second functional element 9 to the third requester- interface 37 and third receiver- interface 45 of the second input/output interface 747, 757, 759 and 761 of any one of the first, second, third or fourth switches.

A first requester-output signal 70 produced at the first requester interface 33 of the first functional element 7 is 31 routed by the f irst decoder 714 and if necessary the third decoder 718 to the second requester-interface 35 of one of the first, second, third or fourth switches 720, 722, 724, or 726, in dependence on whether the requester-output address signal 75 of the first requester- output signal 70 addresses the first, second, third or fourth resource. Similarly the first requesteroutput signal 70 from the first requester- interface 33 of the second functional element 9 is directed by the second decoder 716 and if necessary the third decoder 718 to the third requesterinterface 37 of one of the first, second, third or fourth switches, in dependence on whether the requester-output address signal 75 indicates the first, second, third or fourth resource. Each of the first, second, third and fourth switches 720, 722, 724 and 726 arbitrate between the signals received at their second and third requester interfaces 35,37 to produce a signal at their first requester- interface 33, in the same manner as described in relation to Figure 5. The switches 720, 722, 724 and 726 directly access the first, second, third and fourth resources. When the access has been completed a first receiverinput signal 90 is returned to the first receiver-interface 49 of the switches. The signal is directed back through the appropriate decoders to be received at the first receiverinterface 49 of the first functional element 7 or the second functional element 9.

Although in the context of Figures la, 1b and 7 the systems have been described as modular they may be formed as integrated circuits. In particular the second functional element 9 and routing system 701 may be formed as integrated circuits.

Figure 8a illustrates how digital television signals 809, 811, and 813 can be transmitted via a cable, satellite or terrestrial television channel 852 and be viewed on a television 890. The first, second and third television signals 809, 811 and 813 each represent the audio and video signals necessary to recreate a television programme on input to a television. The digital television signals 809, 811, and 813 are source encoded and 32 channel encoded by a transmitter 850 to produce a modulated analogue signal 835 for transmission into the channel 852. An integrated receiver decoder (also known as a set-top-box) 880 receives the modulated analogue signal 835 from the channel 852 and produces a video signal 839 which operates the television 890.

The operation of the transmitter 850 will now be explained. The transmitter includes a source encoder 810 and a channel encoder 84 0. The source encoder includes - first, second, and third MPEG2 encoders 812, 814 and 816; first second and third packetisers 818, 820, and 822; first, second and third scramblers 824, 826 and 828 and a multiplexer 830. The first, second and third MPEG2 encoders respectively receive the first, second and third television signals and encode the signals to produce first, second and third elementary bit streams 815, 817 and 819. The first, second and third packetisers respectively receive the first, second and third elementary bit streams and packetise them to produce first, second and third packetised elementary bit streams (PES) 821, 823 and 825. The packetising of an elementary bit stream includes creating a series of packets which contain a packet header and a data portion. The first, second and third scramblers receive respectively the first, second, and third packetised elementary bit streams (PES) and produce first, second, and third scrambled PES 827, 829 and 831. The multiplexer 830 receives as inputs packetised sections of tables 841, and the first, second and third scrambled PES 827, 829 and 831 and produces a transport stream 801. The packetised sections of tables 841 contains information which allows the set-top-box 880 to effect source decoding and produce the video signal 839. The information is stored in a tabular format where each table contains a number of sections and each section is transmitted individually. The multiplexer 830 produces a transport stream 801 such as that illustrated in Figure 8b. The transport stream includes a number of transport packets 802 where each transport packet contains a transport packet header 804 and a transport packet payload 806. The transport packets have a fixed length 33 which is dependent upon the estimated error in the channel 852 and will be shorter if the channel is noisy. In the digital video broadcast WVB) standard the transport packet is 188 bytes in length. The transport packets are shorter in length than the packets in the packetised elementary stream. Consequently, in the transport stream 801, a packet from the first scrambled PES 827 will be spread over a number of transport packets and these transport packets will be multiplexed with transport packets derived from the packetised sections of tables 841 and the second and third scrambled PES 829, 831. The transport stream is then supplied to the channel encoder 840 to produce the modulated analogue signal 835.

The channel encoder 840 includes circuitry 832 for forward error correcting (FEC) the transport stream 801 and converting the signal from digital to analogue (DAC) to produce an analogue signal 833. The analogue signal 833 is modulated and upconverted to a transmission frequency by the circuitry 834 to produce the modulated analogue signal 835, which is then transmitted into the channel 852.

The operation of the set-top-box 880 will now be explained. The set-topbox 880 includes a channel decoder 860 and a source decoder 870. The channel decoder 860 receives the modulated analogue signal 852 and supplies the transport stream 801 to the source decoder 870. The channel decoder 860 includes circuitry 862 for tuning to the modulated analogue signal 852, and for downconverting and demodulating the modulated analogue signal 835 to produce an analogue signal 837. The analogue signal 837 is converted from analogue to digital (ADC) and forward error corrected (FEC) by the circuitry 864 to reproduce the transport stream 801. The source decoder 870 receives the transport stream 801 and produces the video signal 839. The source decoder 870 includes a programmable transport interface (PTI) 960 and MPEG-2 decoder 872. The PTI 960 demultiplexes the transport stream 801, selects the transport packets 802 carrying information relating to a particular television programme, and descrambles these 34 selected transport packets to produce a data output stream 956, which is in fact the packetised elementary bit stream of the selected television programme. The MPEG-2 decoder 872 receives the data output stream 956 and produces the video signal 839 which is supplied to the television 890. The television 890 displays the selected television programme.

Figure 8b illustrates a portion of the transport stream 801 having a series of N transport packets 802. Each transport packet 802 comprises a transport packet header 804 and a transport packet payload 806. The transport stream is a bit stream which carries in the transport packet payloads 806 information for recreating a number of different television programmes. Each particular television programme requires three types of information (audio information, video information and tables of programme information) for its recreation. Each transport packet 802 is preferably associated with a particular television programme, a particular source encoding time and a particular one of the information types. The individual transport packets are time division multiplexed to form the transport stream and allow the real-time recreation of a selected one of the different television programmes. To recreate a television programme the transport stream is sequentially demultiplexed to recover only the transport payloads 806 of audio information, video information and table of programme information which are associated with the selected television programme. The recovered payloads are then decoded and used to recreate the selected television programme.

According to the digital video broadcast standard (DVE) each of the transport packets 802 is 188 bytes long and the transport packet header 804 is 4 bytes long. The payload 806 contains either packetised audio or video information or sections of a table of programme information. The audio and video information in the payloads 6 have been packetised and encoded in accordance with the MPEG-2 compression standard in the DVB standard.

i j The transport packet header 804 contains a synchronisation byte which identifies the beginning of each transport packet 802, a packet identification (PID) which identifies the information type and the television programme associated with the transport packet payload 806 and information identifying the time at which of the transport packet was source encoded. The transport packet header 804 including the synchronisation byte and the PID is not scrambled. The transport packet payload 6 may_be scrambled.

The programmable transport interface 960 is illustrated in Figure 9. It receives the transport stream 801 and produces a data output stream 956 and an alternative output stream 906. The alternative output stream 906 may be an output derived from the transport stream 801 for example by private encryption or changing the communication standard under which the transport stream has been prepared. The programmable transport interface (PTI) 960 performs the following functions amongst others. The PTI 960 uses the synchronisation byte to identify the start of a transport packet 802, it uses the packet identification (PID) to identify the type of information contained in the packet and the television programme it represents, and it descrambles the transport packet payloads 806 and demultiplexes the transport stream 801 to produce the data output stream 956. The data output stream comprises a stream of audio information associated with the selected television programme, a stream of video information associated with the selected television programme and tables of programme information associated with the selected television programme. The PTI 960 then outputs these streams to the necessary decoders to reproduce the selected television programme.

The programmable transport interface 960 comprises six functional blocks: the input module 900; the transport controller 920; the instruction SRAM (Static Random Access Memory) 930; the data SRAM 940; and the multichannel DMA (Direct Memory Access) 950.

The input module 900 has a transport stream input interface 902 36 for receiving the transport stream 801 and an alternative stream output interface 904 for outputting the alternative output stream 906. The input module 900 identifies the synchronisation byte of each transport packet which is used to synchronise the system clock and the transport stream. The input module 900 is controlled by the transport controller 920 via an input module control signal 912 which includes a descrambling control signal 914, an alternative stream control signal 91 - 6 and an output stream control signal 918. The input module 900 provides bits to the transport controller 920 via an interconnect 908 and it receives bits back from the transport controller 920 via the interconnect 110. The input module 900 under the control of the transport controller 920 descrambles the payload 806 of selected transport packets 802 and supplies the selected, demultiplexed and descrambled payloads to the transport controller 920 via the interconnect 908. The descrambling of the payloads is controlled by the descrambling control signal 914 and the number and rate of bits supplied on the interconnect 908 is controlled by the output stream control signal 918. The input module 900 receives along the interconnect 910, bits from the transport controller 920 which may be output as the alternative output stream 906 under the control of the alternative stream control signal 916. The operation of the input module is described in more detail in copending Patent Application (Agents reference The transport controller 920 operates on the bits received on interconnect 908 from the input module 900. The transport controller 920 receives from the input module 900 via interconnect 908 the transport packet header 804 of the transport packet 802 arriving at the transport stream input interface 902. The transport controller 920 uses the packet identification (PID) in the transport packet header 804 to determine whether the transport packet 802 now entering the input module 900 via transport stream input interface 902 is associated with a selected television programme. If it is not the received transport packet 802 is discarded. If it is, it controls the input module 900 to descramble and supply the transport packet 37 payload 806 via the interconnect 908 to the transport controller 920. The transport controller 920 may pass a payload 806 associated with audio or video information for the selected programme straight to the multi- channel DMA via interconnect 952. If the payload 806 relates to a section of a table of programme information the transport controller 920 may process the information before providing it at its output 952. Alternatively the transport controller 920 may process the received payloads 806 and repacketise them in accordance with a different transmission standard. The reformatted transport stream is then provided to the input module 900 via the interconnect 910 and it is output as the alternative output stream 906 under the control of the alternative stream control signal 916.

The transport controller 920 comprises a transport controller processor (not shown in Figure 9) which reads instructions from the instruction SRAM 930. The transport controller 920 is connected to the SRAM 930 by interconnect 934 and it reads its instructions via the interconnect 934. A CPU (not shown in Figure 9) may read and write to the instruction SRAM 930 via the interface 302 allowing the transport controller instruction to be varied. However, the transport controller 920 has preferential access to the instruction SRAM 930.

The data SRAM 940 can be read from and written to by the transport controller processor via the interconnect 944. A search engine (not shown in Figure 9) within the transport controller 920 reads from the data SRAM 940 via interconnect 946. The search engine associates a pointer with each of the programme identifications (PIDs) in the transport packet headers 804. The data SRAM 940 stores at a location indicated by the pointer the information associated with a transport packet 802 having a particular PID. This information is read over interconnect 946 and it enables the transport controller to control the production of the input module control signals 912 and the processing of the bits received on interconnect 908. The data SRAM 940 can be written to and read from by the system processor via the 38 interface 902. Access to the data SPLAM 940 is arbitrated with the following order of decreasing priority: search engine, transport controller processor, CPU. The transport controller 920 may be reset by the system processor by reset signal 922.

The transport controller 920 produces a transport controller output which is supplied to a multi-channel DMA 950 via interconnect 952. The multichannel DMA 950 has an external memory interface 954 which supplies the data output stream 956 to decoders (not shown in Figure 9).

Figure 10a illustrates a source decoder 870 in a set-top-box 880. The source decoder 870 uses a bus 5 and a hierarchical structure similar to that illustrated in Figure la. The system includes the following elements: a CPU 1000, a bus 5, a switch 11, an MPEG-2 decoder 872, a decoder memory 1002, an arbiter 1004 and the components of a programmable transport interface 960 including the data SRAM 940, the instruction SRAM 930, the transport controller 920 and the input module 900. The transport controller 920 includes a search engine 1060 and a transport controller processor 1070. The input module 900 of the PTI receives a transport stream 801 and the MPEG2 decoder 872 produces the video signal 839 for supply to a television. The data SRAM 940, instruction SRAM 930 and decoder memory 1002 are resources connected to the bus 5. The CPU 1000, the search engine 1060 within the transport controller 920, the transport controller processor 1070 and the switch 11 are functional elements in the first level of hierarchy of the system and are each connected to the bus 5. The arbiter 1004 arbitrates to determine which of the functional elements should gain access to the bus 5 and to the resources. The transport controller 920 and the MPEG-2 decoder 872 are functional elements in the second level of hierarchy of the system and are each connected as inputs to the switch 11. The switch 11 arbitrates between the transport controller 920 and the MPEG-2 decoder 872 to determine which should have access to the first level of hierarchy and therefore be able to compete with the CPU 1000 and the search engine 1060 39 for access to the bus 5 and the resources. The transport controller 920 supplies the data output stream 956 via the switch 11 to the decoder memory 1002. The MPEG-2 decoder 872 reads from the decoder memory 1002 via the switch 11, and uses the information read from the decoder memory 1002 to produce the video signal 839 for supply to a television. The switch 11 arbitrates between the writing to the decoder memory 1002 by the transport controller 920 and the reading from the memory 1002 by the MPEG-2 decoder 872.

Figure lob illustrates a source decoder 870 in a set-top-box 880. The source decoder 870 includes a PTI 960 (including data SRAM 940, instruction SRAM 930, and a transport controller 920 which includes a search engine 1060 and a transport controller processor 1070); MPEG2 decoder 872; CPU 1000; decoder memory 1002; and routing system 701. This figure differs from Figure loa in that a hierarchical system similar to that illustrated in Figure 7 is used which does not necessitate the use of a bus. The routing system 701 includes a first decoder 1040, a second decoder 1050, and first, second, and third switches 1010, 1020, and 1030 which respectively request access to the data SRAM 940, the instruction SRAM 930 and the decoder memory 1002. The CPU 1000 requires access to the data SRAM 940 and the instruction SR.AM 930 and its output is decoded by the first decoder 1040 and input to either the first switch 1010 or the second switch 1020. The search engine 1060 requires access to the data SRAM 940 and is connected as an input to the first switch 1010. The transport controller processor 1070 requires access to the data SRAM 940 and the instruction SRAM 930, and its output is decoded by the second decoder 1050 and input to either the first switch 1010 or the second switch 1020. The transport controller 920 requires access to the decoder memory 1002 and its output is supplied as an input to the third switch 1030. The MPEG-2 decoder 872 requires access to the decoder memory 1002 and it is connected as an input to the third switch 1030. The first, second and third switches are similar to the switches described in relation to Figures la, lb, 2a, 5 and 7.The first switch 1010 arbitrates between a request for access to the data SRAM 940 from the CPU 1000, the search engine 1060 and the transport controller processor 1070. The second switch 1020 arbitrates between requests for access to the instruction SRAM 930 from the CPU looo and the transport controller processor 1070. The third switch 1030 arbitrates between requests for access to the decoder memory 1002 from the transport controller 920 and the MPEG-2 decoders 872.

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Claims

CLAIMS:

1. Circuitry for arbitrating between a plurality of request signals to access resources, comprising:

input means for receiving said plurality of request signals, wherein each request signal identifies the resource to which it is requesting access; and arbitration means arranged to receive said plurality of request signals, and status signals wherein each status signal identifies whether a resource is capable of beihg accessed, and wherein said arbitration means is arranged to arbitrate between request signals which are requesting access to resources having status signals indicating that they are capable of being accessed, to select one request signal.

2. Circuitry as claimed in claim 1, wherein said plurality of request signals include a first request signal comprising a first address signal identifying a first resource and a second request signal comprising a second address signal identifying a second resource.

3. Circuitry as claimed in claim 2, wherein said f irst request signal comprises, simultaneously, a request signal and the f irst address signal and said second request signal comprises, simultaneously, a request signal and the second address signal.

4. Circuitry as claimed in any one of claim 1, 2 or 3, wherein said arbitration means is arranged to control an access to one of said resources by processing said request signals.

5. Circuitry as claimed in claim 4 when dependent upon claim 2, wherein the arbitration means is responsive to a first status signal identifying the first resource as being incapable of being accessed to inhibit the processing of said first request signal and to a second status signal identifying the second resource as being incapable of being accessed to inhibit the processing of said second request signal.

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6. Circuitry as claimed in claim 5, wherein the arbitration means comprises arbitration circuitry for processing said first and second request signals and logic circuitry for supplying said first and second request signals to said arbitration circuitry, wherein said logic circuitry receives said first and second status signals and is responsive to the first status signal when identifying the first resource as being incapable of being accessed to inhibit the supply of the first request signal to said arbitration circuitry and is responsive to the second status signal when identifying the second resource as'being incapable of being accessed to inhibit the supply of the second signal to said arbitration circuitry.

7. Circuitry as claimed in any preceding claim, wherein said arbitration is dependent upon the identity of the resources to which said first and second signals are requesting access.

8. Circuitry as claimed in any preceding claim, wherein the timing of said arbitration means is controlled by a clock signal having a constant clock cycle, and wherein the arbitrating between the request signals which are requesting access to resources having status signals indicating they are capable of being accessed, to select one request signal occurs within a single clock cycle.

9. Circuitry as claimed in claim 2, wherein said first and second resources are the same resource or different resources.

10. Circuitry as claimed in any preceding claim, wherein said arbitration means is responsive to said selection of one request signal, to produce an output request signal requesting access to a resource.

11. Circuitry as claimed in claim 10, wherein said arbitration means is further arranged to produce and return a grant signal to the circuitry which provided said selected one request signal.

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12. Circuitry as claimed in claim 10 or 11, wherein said request signals and said output request signal utilise the same protocol.

13. Circuitry as claimed in claim 10, 11 or 12, wherein said arbitration circuitry selects one of said request signals and provides the selected request signal as the output request signal.

14. A system for accessing resources, comprising: circuitry as claimed in any preceding claim; plurality of resources; bus interconnecting said circuitry and said plurality of resources; and second arbitration means for determining whether said circuitry, producing said output request signal, should have access to one of said plurality of resources.

15. An integrated circuit comprising circuitry as claimed in any one of claim 1 to 13 or a system as claimed in claim 14.

16. A method of arbitrating between a plurality of requests to access resources comprising the steps of: receiving a plurality of request signals, wherein each request signal identifies the resource to which it is requesting access; receiving status signals wherein each status signal identifies whether a resource is capable of being accessed; and arbitrating between request signals which are requesting access to resources having status signals indicating that they are capable of being accessed, to select one request signal.

17. A method of arbitrating as claimed in claim 16, wherein said step of arbitrating between request signals comprises the processing of said request signals.

18. A method as claimed in claim 16, wherein said step of arbitrating between request signals further comprises:

44 identifying the resource each of said plurality of request signals is requesting access to; identifying, from the status signals, whether the resources to which access is requested are capable of being accessed; and arbitrating between request signals which are requesting access to resources having status signals indicating that they are capable of being accessed to select one request signal.

19. A method as claimed in claim 17 or 18, wherein said step of arbitrating further comprises: the inhibition of processing request signals having status signals indicating that they are not capable of being accessed.

20. A method as claimed in any preceding claim when dependent upon claim 17, wherein said processing of the request signals is controlled by a clock signal having a constant clock cycle and wherein the step of arbitrating between the request signals which are requesting access to resources having status signal indicating they are capable of being accessed to select one request signal, occurs within a single clock cycle.