GB2329289A

GB2329289A - Antifuse-controlled analogue circuit trimming with security locking antifuse

Info

Publication number: GB2329289A
Application number: GB9718146A
Authority: GB
Inventors: Raymond Filippi; Richard Goldman
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 1997-08-27
Filing date: 1997-08-27
Publication date: 1999-03-17
Also published as: GB9718146D0; TW364197B; WO1999010931A1; AU9263398A

Abstract

A trimming circuit for an analogue IC includes a number of antifuses 24.1 to 24.N controlling switching MOS transistors P1.1 and N1.1 operating to alter resistances in the IC. Trial trimming data is read into the circuit serially 12 to control the switches, and when a suitable trimming data set is established the antifuses 24.1 to 24.N are blown. The security antifuse 15 is then blown to prevent any accidental further trimming.

Description

ANALOG TRIMMING TECHNICAL FIELD OF THE INVENTION This invention relates to a trimming control circuit, for use when trimming analog circuits.

DESCRIPTION OF RELATED ART In the manufacture of analog integrated circuits, it is desirable or necessary to keep certain circuit parameters close to the values intended by the circuit designer. However, it may be very difficult to achieve these values, to within acceptable tolerances, and indeed mechanical stress may alter parameters of the components once the circuit has been packaged. As a result, the idea of trimming is widely used. For example, when it is the resistance value of a resistor, which is intended to be kept at a particular value, the circuit may also include one or more extra resistors, which can be switched in or out of the circuit, in order to adjust the total value of resistance. The trimming may be carried out by means of an antifuse, which may be blown by the application of a high voltage thereto, and which, when blown, may ensure that the extra resistor is permanently switched into or out of the circuit, as desired.

US Patent No. 5,361,001 discloses a circuit which allows a trim to be previewed. Each fuse forms part of a control circuit, which can be used to switch a respective resistor in or out of a circuit. The voltage across each fuse is supplied as one input to an OR gate, which receives a respective bit of a data signal as its other input. Thus, a data signal supplied to all of the control circuits which switch all of the respective resistors in or out of the circuit, mimics a particular trim. The effect of various trims can be tested, until the desired result is obtained, and the antifuses can then be blown as required to obtain that trim.

SUMMARY OF THE INVENTION A problem which can arise with conventional trimming circuits is that, once the chip has been adjusted as required, further trimming may take place accidentally.

The present invention seeks to overcome this potential problem with conventional circuits, by providing an additional fusible element which, when blown, prevents the application of a signal which might blow the other fusible elements in the trimming circuit.

A further disadvantage of conventional trimming circuits is that the process of carrying out the blowing of the antifuses can be relatively time consuming.

The present invention seeks to overcome this disadvantage, by allowing all of the fusible elements, which are intended to be blown, to be blown in a single action.

Trimming circuits in accordance with preferred embodiments of the present invention therefore have the advantage that they allow trimming to be carried out quickly and accurately, without the possibility that further inadvertent trimming may later take place.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block circuit diagram of a trimming circuit in accordance with the invention.

Figure 2 is a circuit diagram of a trimming block used in the circuit of Figure 1.

Figure 3 is a flow chart showing the progress of a trimming operation using the circuit of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Figure 1 shows a trimming circuit, in which trimming can be achieved in two slightly different ways.

A first controlled block 2 includes a PMOS transistor P1.1, the source of which is connected to a positive supply SUPA. When a low level signal, of less than the supply voltage minus the threshold voltage, is supplied to the gate of the transistor Pal.1, the transistor conducts, and the resistor R1.1 is switched into the circuit, in parallel with the resistor R1.2.

When a high level signal of about the level of the supply voltage is applied to the gate of the transistor P1.1, the resistor R1.1 is out of the circuit.

A second controlled block 4 includes resistors R1.3 and R1.4 connected in series to an earth voltage GNDA, with an NMOS transistor Nl connected in parallel with the second resistor R1.4. When a low level signal is applied to the gate of the transistor N1.1, the resistor Rl.4 appears in the circuit, but, when a high level signal is applied to the gate of the transistor N1.1, the resistor R1.4 is short circuited out.

Thus, the two types of controlled device 2, 4 shown in Figure 1 each allow the total resistance of the device to be adjusted, by means of the application of a high level or low level signal to the gate of a transistor. As is conventional, these controlled devices 2, 4 can be connected to other integrated circuit components, in order to trim the parameters of the integrated circuit.

In order to be able to supply either high or low level voltages to controlled devices, as required, the circuit of Figure 1 includes an inverting data block 6 and a non-inverting data block 8. The circuit further includes a security block 10, and a serial interface 12, which supplies signals to the trimming circuit.

Each data block 6, 8, and the security block 10 includes a respective ZAP interface circuit, which includes a capacitor acting as an antifuse. When the digital input to one of these ZAP interface circuits Z is low, it blows the antifuse. The circuit Z senses if the antifuse has been blown, and produces a digital output which is low while the antifuse remains open circuit, and is high once the antifuse has been blown.

Figure 2 is a circuit diagram of one of the ZAP interface circuits Z. The circuit diagram of Figure 2 is largely self-explanatory, and the circuit itself is described in more detail in British Patent Application No. 9621058.8, the contents of which are incorporated herein by reference.

The antifuse is the low voltage capacitor labelled CAPZAP, which blows short circuit when > 50V is applied across it. Therefore, to blow it, the ZAP node is pulled down towards VNEG (preferably about -120V) by a current source of -58A. This current is generated when the input terminal IN is pulled down to GND, which causes a voltage drop of 4.3V across R1 which is then mirrored by Ni and N2. This current only flows when trying to blow the capacitor. Once blown the capacitor is equivalent to an 80Q resistor and thus pulls the ZAP node to GND. The zapping current is then switched off by pulling IN up to SUP.

The state of the capacitor is determined by sensing when the PNP transistor P2 goes into saturation by monitoring its base current.

A reference current of 5yA is set up by applying -3V across R5, this is mirrored by N6 and N5 to set up a current of 5yA through P3, which in turn is mirrored by P2. This current mirror has a Beta helper, P4.

Therefore the combined base current of P2 and P3 flows through P4. This current normally flows into N4 which is a 0.5A current sink and therefore N3B is pulled close to GND and therefore N3 is switched off and OUT is pulled high by P7. This is the case for when the capacitor is blown and ZAP is pulled to GND thus keeping P2 out of saturation. However if the capacitor is not blown, then P2 will charge it and pull it close to SUP which saturates P2 which will therefore pull a much larger base current of up to 5yea. This current is much larger than the 0.5A N4 current sink and therefore the excess current flows into the base of N3, turning it on and thus pulling the output low.

The resistor R2 ensures that N2 is turned off even when leakage at high temperature is taken into account and thus prevents ZAP from being pulled down below GND, when IN is high. The transistor P5 is used as a clamp diode and prevents the node P2B from being pulled much above SUP. This can happen when the ZAP node is pulled down to VNEG and the capacitor suddenly blows and pulls the ZAP node up to GND. This is coupled through the collector-base capacitance of P2 and also through the base-collector capacitance of P3, which could put the drain of N5 at risk if the P5 protection diode is not used.

Thus, returning to Figure 1, each ZAP interface circuit block Z produces a digital output which is low, for as long as the digital input remains high. When the digital input is pulled low, the antifuse is blown, and the digital output remains high thereafter.

The security block 10 includes a zap interface circuit 15, and a pair of inverters 14, 16, connected before the zap interface circuit and after it. The inverter 14, connected before the zap interface circuit Z, receives a DISABLE signal from the serial interface circuit 12.

On manufacture, the zap interface circuit produces a low output signal which, by means of the inverter 16, results in the ENABLE signal, output from the security block 10, to remain high. The ENABLE signal is supplied as an input signal to one terminal of an AND gate 18.1, ..., 18.N in each of the data blocks 6, 8.

The other input of each AND gate 18.1, ..., 18.N comes from a respective output ZAP1, ..., ZAPN of the serial interface 12. In each data block 6, 8, the output of the AND gate 18.1, ..., 18.N is supplied to one input terminal of a NAND gate 20.1, ..., 20.N, and also to one input terminal of a logic gate 22.1, ..., 22.N which, in the case of an inverting data block 6 is a NOR gate and which, in the case of a non-inverting data block 8, is an OR gate.

The other input of each NAND gate 20.1, ..., 20.N is connected to an output on the serial interface 12 to receive a BLOW signal, and the output from each NAND gate is supplied to the respective zap interface circuit 24.1, ..., 24.N. The output from each zap interface circuit 24.1, ..., 24.N is supplied as the other input to the respective logic gate 22.1, 22.N, and the outputs from those logic gates 22.1, 22.N are taken as the outputs from the respective data blocks, for supply to the controlled circuits 2, 4 respectively.

Figure 3 is a flow chart showing a process in which the trimming circuit of Figure 1 is used.

In step S1 of the process, the signals DISABLE and BLOW from the serial interface 12 are kept low. The low DISABLE signal means that the input supplied via the inverter 14 to the zap interface 15 in the security block 10 remains high, which means that the antifuse is not blown, the output from the zap interface 15 remains low, and the ENABLE signal remains high. The low BLOW signal means that one of the inputs to the NAND gate 20.1, ..., 20.N in each of the data blocks 6, 8 remains low. As a result, the output of each NAND gate 20.1, ..., 20.N remains high, and so the antifuses in the interface circuits 24.1, ..., 24.N in the data blocks are not blown.

Then, in step S2 of the process shown in Figure 3, data relating to a proposed trim are supplied to the DATA input of the serial interface 12, and supplied to the data blocks 6, 8 on the lines ZAP1, ..., ZAPN.

Specifically, these signals are supplied to inputs of the respective AND gates 18.1, ..., 18.N. The signal on each of these lines can be either high or low, depending on the proposed trim. When the signal on a line ZAPn is low, the output from the respective AND gate 18.n is low, which means that both inputs to the logic gate 22.n are low, since the antifuse in the zap interface circuit 24.n has not blown. The output from the data block is therefore high in the case of a NOR gate 22.1 in an inverting data block 6, or low in the case of an OR gate 22.N in a non-inverting data block 8. In each case, these outputs leave the respective MOS transistors switched off in the controlled circuits 2, 4.

Where the signal on a line ZAPn is high, the output from the respective AND gate 18.n is high, and so each logic gate 22.n has an input which is high. In the case of a NOR gate 22.1 in an inverting data block 6, this means that the output is low, and in the case of an OR gate 22.N in a non-inverting data block 8, this means that the output is high. In each case, this means that the respective MOS transistor in the controlled circuit 2, 4 is switched on. As discussed above, the effect of this proposed trim can then be tested in step S3 of the process shown in Figure 3. If the performance of the circuit is still not acceptable, the proposed trim can be adjusted in step S4, and steps S2 and S3 can be repeated. When an acceptable trim configuration has been achieved, then, in step S5, a high level output signal BLOW is applied from the serial interface 12 to each of the NAND gates 20.1, 20.N. In those data blocks which are also receiving high signals on the respective one of the lines ZAP1 ..., ZAPN, the second input to the respective NAND gate 20.1, ..., 20.N, received from the output of the AND gate 18.1, ..., 18.N, is also high, which means that the NAND gate supplies a low output signal to the respective zap interface circuit 24.1, ..., 24.N, which blows the antifuse. When the antifuse has been blown, the output from the zap interface circuit 24.1, ..., 24.N produces a high output signal thereafter, which means that, in data blocks 6, 8 where the antifuse has blown, the logic gate 22.1, ..., 22.N always has at least one input terminal which receives a high input signal, and which means that, in the case of a NOR gate 22.1 in an inverting data block 6, the output signal is low thereafter, and, in the case of an OR gate 22.N in a non-inverting data block 8, the output signal is high thereafter.

The performance of the circuit can then be checked in step S6.

Assuming that the performance remains acceptable, then1 in step S7, a signal can be applied on the DISABLE line from the serial interface 12. This has the effect of preventing any further blowing of any unblown antifuses.

When a high signal is supplied on the DISABLE line, the input supplied to the zap interface circuit 15 in the security block 10 from the inverter 14 becomes low, and the antifuse in the zap interface circuit 15 is blown. Thereafter, the output from the zap interface circuit 15 in the security block 10 remains high, and the ENABLE signal supplied from the security block 10 via the inverter 16 remains low.

Thus, from then on, each data block 6, 8 receives a low ENABLE signal to the respective AND gate 18.1, 18.N. That means that, even if signals are erroneously sent on the BLOW line or the respective ZAPn line, the output from the AND gate 18.n will remain low, and the output from the NAND gate 20.n will remain high. Thus, blowing the antifuse in the zap interface circuit 15 in the security block 10 means that the antifuses in the data blocks 6, 8 cannot be blown, even if signals are inadvertently transmitted on the lines normally used to blow those antifuses. This is particularly advantageous if the serial interface 12 is used to control other functions on the integrated circuit.

Moreover, the ability to blow all of the desired antifuses in the respective zap interface circuits in the data blocks essentially simultaneously, by applying a signal on the BLOW line means that the trimming can be carried out more quickly.

Claims

1. A trimming circuit, comprising: a plurality of first fusible elements, which may each be blown by applying a control signal thereto; means for supplying control signals to some or all of the first fusible elements; a second fusible element, which may be blown by applying a control signal thereto; and means for preventing the application of a control signal to the first fusible elements when the second fusible element is blown.

2. A trimming circuit as claimed in claim 1, wherein the means for preventing the application of a control signal to the first fusible elements comprises logic circuitry.

3. A trimming circuit as claimed in claim 2, wherein the logic circuitry comprises a first logic gate, associated with each first fusible element, each first logic gate receiving a signal from the second fusible element, which allows a control signal to be sent to the respective first fusible element only when the second fusible element is not blown.

4. A trimming circuit as claimed in claim 1, 2 or 3, wherein: each first and second fusible element is an antifuse, which is blown by the application of a low level signal thereto; each first fusible element receives an input signal from the output of a respective NAND gate; each respective NAND gate receives an input signal from the output of a respective AND gate; and each respective AND gate receives an input signal from the output of the second fusible element, and wherein: the means for preventing the application of a control signal to the first fusible elements comprises means for applying a low level signal to the input of each respective AND gate when the second fusible element is blown, such that each respective AND gate produces a low level output signal, with the result that each respective NAND gate receives at least one low level input signal and so produces a high level output signal for supply to the respective first fusible element.

5. A trimming circuit, for supplying a trimming output signal in response to trimming data, the trimming circuit comprising a security block and a data block, the security block including a fusible element and having an input terminal and an output, and the data block including a fusible element, and having first, second and third input terminals and a trimming output, and further including a plurality of logic gates, the output of the security block being connected to the first input terminal of the data block and the logic gates in the data block being arranged such that: when the data block receives a first signal on its first input terminal, the fusible element cannot be blown, when the data block receives a first signal on the second input terminal and a second signal on the first input terminal, the fusible element may be blown, in dependence on a signal on the third input, and when the security block receives a first signal on its input terminal, the fusible element thereof is blown, and the security block thereafter produces an output signal which is supplied as the first signal on the first input terminal of the data block.

6. A trimming circuit as claimed in claim 5, including a plurality of data blocks, and further comprising a serial interface, for sending the same signal to the respective second inputs of the data blocks substantially simultaneously.

7. A trimming circuit as claimed in claim 5, wherein, when the fusible element in the data block is not blown: when the data block receives a second signal on the first input terminal, and a first signal on the third input terminal, the signal on the trimming output is the same as if the fusible element is blown, and when the data block receives a second signal on the first input terminal, and a second signal on the third input terminal, the signal on the trimming output is the same as if the fusible element is not blown.

8. A trimming circuit as claimed in claim 7, including a plurality of data blocks, and further comprising a serial interface, for sending respective signals to the respective third inputs of the data blocks substantially simultaneously.

9. A trimming circuit as claimed in claim 5 or 7, wherein the data block produces a high level signal when the fusible element is blown.

10. A trimming circuit as claimed in claim 5 or 7, wherein the data block produces a low level signal when the fusible element is blown.

11. A trimming circuit as claimed in one of claims 5 to 8, including a plurality of data blocks, wherein at least one data block produces a high level signal when the fusible element is blown and at least one data block produces a low level signal when the fusible element is blown.

12. A trimming circuit, comprising a plurality of data blocks, each including a fusible element and logic circuitry such that, when the respective data block receives appropriate input signals, either the data block can produce an output signal which is the same as if the fusible element thereof were blown, or the fusible element can be blown, wherein the trimming circuit further comprises a serial interface, for receiving a data signal, and supplying appropriate input signals to each data block substantially simultaneously.