GB2327579A - Data transportation in two modes using two clock signals - Google Patents

Abstract

For data transportation between a master apparatus 2 and at least one module 4 there is provided a clock signal and a strobe signal on clock lines 32 and 34 respectively. In Normal mode data from micro-controller 6 is written into output buffer block 16 and into output shift register block 18 by the strobe signal. The data is then shifted out serially bit by bit by the clock signal to input shift register block 30 of module 4 via output port 36. Data received into input shift register block 22 from module 4 via input port 38 is transferred to input buffer block 20 by the strobe signal. In SPI mode data is transferred between SPI devices 12 and 14 using the strobe signal, while the clock signal is deactivated or stopped. Thus data in the shift register blocks is halted until the normal mode is resumed. Typical applications include supervisory control and data acquisition (SCADA) systems.

Description

APPARATUS FOR CONTROLLING OF DATA TRANSPORTATION AND A METHOD Field of the Invention This invention relates to apparatus for controlling data transportation and a method.

Background of the Invention This invention relates in particular to communications apparatus, such as remote data/control apparatus. The invention relates to improvements in communication protocols and communication systems having several remote terminal units and one or more master control centres communicating by radio, serial ports, dedicated lines and/or telephone lines.

Typical applications include, but are not limited to supervisory control and data acquisition (SCADA) for water and waste water systems, electric utility distribution systems, oil and gas pipelines, early warning siren systems, communication control systems, irrigation control systems and roadside emergency callbox systems.

Summarv of the Invention According to the invention there is provided apparatus as set forth in claim 1.

Brief Description of the Drawings FIG. 1 is a block diagram of a simple SCADA system; FIG. 2 is a block diagram of an apparatus and a communication module according to a preferred embodiment of the invention; FIG. 3 is a timing diagram of the communication port in a Normal mode of operation a according to a preferred embodiment of the invention; FIG. 4 is a timing diagram the communication port in SPI mode of operation of according to a preferred embodiment of the invention; and FIG. 5 is a detailed block diagram of a shift register block of the apparatus according to the preferred embodiment of the invention.

Detailed Description of the Drawings A general overview of a SCADA system will now be given with reference to FIG. 1. The SCADA system includes a central computer 1 operably coupled to a central processor unit (CPU) 2. The CPU 2 is operably coupled to a plurality of modules 4,5 through a signal communication port 3. The modules can be a remote control unit, Input/Output unit or other units that are part of the SCADA system.

A detailed description of an apparatus which controls the communication port operation will now be given with reference to FIG.

2.

The components of the apparatus 10 are divided into two units, the CPU 2 and to each module 4. The communication port 3 links the CPU 2 to at least one module. The CPU 2 includes a SeriaVParallel Interface (SPI) device 14, a switch 12, an output buffer block 16 which includes five buffers of 8 bits, an output shift register block 18 which includes five shift registers of 8 bits, an input buffer block 20 which includes five buffers of 8 bits and an input shift register 22 which includes 5 shift registers of 8 bits. Each module includes a SPI device 24, a switch 26, an output shift register block 28 which includes five shift registers of 8 bits, an input shift register block 30 which includes five shift registers 31 of 8 bit and an input buffer block which includes five buffers of 8 bits. The communication port 3 includes a clock 32, a strobe 34, an output port 36 and an input port 38.

The apparatus 10 may be in one of the three states from communication point of view. The three states are Idle mode, Normal mode and SPI mode.

The apparatus 10 enters Idle mode upon start up or after reset.

After loading all modules Output buffers block's 28 buffers the CPU 2 may issue Start 110 command in order to enter into Normal mode of data transfer with the modules, for example module 4.

When in Normal mode , the apparatus 10 may return into Idle mode by issuing commands, for example Reset 0 or Reset 1, or enter SPI mode with one of the modules by issuing the appropriate command.

When in SPI mode , the system may return into Idle mode by issuing Reset 0 or Reset 1 commands.

With reference to FIG. 3, in Normal mode, data 40 is written by a micro-controller 6 into the output buffer block 16. The data 40 from the output buffer block 16 is loaded by Strobe signal 44 into the output shift register block 18. Then, the data 40 is shifted out serially bit-by-bit by the Clock signal 42. Simultaneously, the Clock signal 42 shifts in serially the data 40 into the module 4 input shift register block 30. The strobe signal 44 loads the data 40 into the input buffer block.

Data 40 from the module 4 is transferred to the CPU 2 in the same manner. This data transfer repeats automatically as long as the system is in Normal mode.

The data transportation between the CPU 2 and the module 4 is orchestrated by the strobe signal 44 and the clock signal 42. The strobe signal 44 simultaneously loads data from the output buffers block 16 and data from the input port 38 to the shift register block 22 of the CPU 2, loads data to the output shift registers blocks 28 and data from the output port 36 to the input shift registers block 30 of the module 4. The clock signal 42 which become active immediately after the strobe signal 44 push the data 40 from the shift registers blocks to the output port 38 and to CPU 2 and the module 4 respectively.

The operation of the SPI mode will be now described with references to FIG. 4.

In SPI mode , switch 14 connects the out port 36 to the SPI device 12 and switch 26 connects the input port to the SPI device 24. Data transfer starts after the micro-controller 6 writes a byte into SPI device 14 as it shown as signal 51 of FIG. 4. The SPI signal 53 become "Busy" and the strobe signal 44 shifted the data 50 out. Data 50 is shifted into the SPI device 24 of the module 4, at the same time data addressed in the module's SPI device 24 is transferred into SPI Input port 38 to be read by the SPI device 12 in the CPU 2. SPI Data transfer recycles for each write into SPI Output Data Register until terminated by a CPU command.

Alternating from "Normal" mode to SPI mode is done in the following way. In Normal mode, a command is issued by the controller 6. The command is received by the module 4. The module 4 translate the command and switches switch 26 to rout the input port 38 to the SPI device 24. The controller 6 switches the switch 14 to rout the output port 36 to the SPI device 12 and changes the functionality of the Clock port 32 and the Strobe port 34. The Strobe signal 44 is became the clock signal of the SPI and the clock signal 42 is not activated during the time period that the communication port 3 is in SPI mode.

The advantage of not activating the clock signal during SPI is that data in the shift register blocks 18, 20, 28 and 30 is halted till returning to Normal mode and activated the Clock signal..

In order to terminate SPI mode , Reset 0 or Reset 1 commands are issued. Reset 0 is issued by providing to the clock port 32 , the strobe port 34 and the output port 36 the value of logic "1". Reset 1 is issued by providing to the clock port 32 and the strobe port 34 the value of logic "1" and logic "0" to the output port 36.

Referring to FIG. 5 a detailed block diagram of the shift register block is shown. The shift register block 12 includes five shift register 60,62,64,66,68 of 8 bit each and a shift register 70 for delaying the 40 bits of the five shift registers. Shift register 60 is carry bits 40 to 33, shift register 62 carry bits 32 to 25, shift register 64 carry bits 24 to 17, shift register 66 carry bits 16 to 9 and shift register 68 carry bits 8 to 1. For each strobe signal 44 bits are loaded to the five shift register and shifted out according to the clock signal 42 through the shift register 70. The shift register 70 can be program to 1 to 8 bit delay. For exampl, if the shift register was program to delay of 4, the controller 6 will clock out 4 extra bit which will be ignored by the receiving unit. Bits 37 to 40 will be ignored and bits 36 to 33 will be shifted to shift register 62. In that way an valid data that are in the range of two shift registers can be moved to one shift register.

The following table describe the last 8 bits in the output train (time slots 33..40), versus the delay set in the delay control register.

Time Slot Delay 33 34 35 36 37 38 39 40 0 33 34 35 36 37 38 39 40 1 32 33 34 35 36 37 38 39 2 31 32 33 34 35 36 37 33 3 30 31 32 33 34 35 36 37 4 29 30 31 32 33 34 35 36 5 28 29 30 31 32 33 34 35 6 27 28 29 30 31 32 33 34 7 26 27 28 29 30 31 32 33 8 25 26 27 28 29 30 31 32

Claims (3)

1. Claims 1. An apparatus for controlling of data transportation between the apparatus to at least one module via a communication port having at least two mode of operation, wherein the apparatus comprising: a device for controlling communication in a first mode; a device for controlling communication in a second mode; and the communication port is characterised by that: providing a function which is activated with a first control line to a second control line; and halting activities of a second control line for alternating between the communication port modes of operation.
2. 2. Apparatus substantially as hereinbefore described with reference to an as illustrated by the drawings.
3. 3. A method for controlling data transportation substantially as hereinbefore described with reference to and as illustrated by the drawings.