GB2326801A

GB2326801A - Allocation of a test channel for a trunk line

Info

Publication number: GB2326801A
Application number: GB9806859A
Authority: GB
Inventors: Youn-Ho Won
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1997-05-29
Filing date: 1998-03-31
Publication date: 1998-12-30
Anticipated expiration: 2018-03-31
Also published as: KR19980085451A; FR2764150A1; CN1206318A; FR2764150B1; JP3154972B2; CN1114331C; DE19818451A1; JPH1141195A; GB9806859D0; GB2326801B; KR100258150B1; RU2146417C1

Description

1 2326801 CHANNEL ALLOCATION METHOD AND CIRCUIT FOR TRUNK LINE IN A

COMMUNICATION SYSTEM

BACKGROUND TO THE INVENTION

The present invention relates to a communication system, and in particular, to a channel allocation method and circuit for testing a trunk line in a radio communication system.

In general, a trunk line is connected between a base station controller (BSC) and a basestation transceiver system (BTS), to transmit packet data. The trunk line is tested occasionally to check whether it transmits the packet data normally.

A line interface E1 assembly (LIEA) is used as an interface board with the trunk line. The line interface E1 board assembly can accommodate up to 8 links LINKO-LINK7, as shown in figure 2, so that it can thereby be connected to up to 8 E1 trunks.

Moreover, a connection between the base station controller and the basestation transceiver system is made by an E1 or T1 trunk, and the data transmitted through the E1 or T1 trunk is in packet form.

There are two known methods for checking whether or not a trunk transmits data normally. One such method is to provide a loop back by using a back-loop cable; transmit pseudo random data; and receive the transmitted, loopedback, pseudo random data, so as to decide whether or not the data is transmitted normally. The other such method is to loop back by using the back-loop cable, and perform a back-loop test by using a WEA F1W (i.e., a LIEA (EI/TI interface Board) processing program).

However, these conventional methods are available only in the off-line state, so it is not possible to transmit 2 packet data during the trunk test. Further, since the back loop test must be repeated five times, they are time consuming and the conventional method is restricted by space, in that the test must be operated at the base 5 station controller.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a trunk test method and circuit in which an operator may request a test command to be performed, without restriction of time and space.

It is another object of the present invention to provide a circuit for testing a trunk by transmitting reliable data.

is It is still another object of the present invention to provide a circuit for performing a BER (bit error rate) test, at the same time as communications service is provided by a trunk line.

Accordingly, the present invention provides a method of allocating a test channel in a multi-channel trunk line of communication system, comprising the steps of allocating number of data channels; allocating, in a test enable state, a first channel as a frame synchronisation channel, a second channel as a further data channel and a third channel as a test channel, thereby enabling the testing of the data channels of the trunk through the test channel; and allocating, in a test disable state, a first channel as a frame synchronisation channel, a second channel as a multi-frame synchronous channel and a third channel as a test channel.

the present invention also provides a circuit for allocating a test channel in a multi-channel trunk line of a communication system, comprising:

means for allocating a number of data channels; means for allocating, in a test enable state, a first channel as a frame synchronisation channel, a second 3 channel as a further data channel and a third channel as a test channel, thus enabling testing of the data channels of the trunk through the test channel; and means for allocating, in a test disable state, a first channel as a frame synchronisation channel, a second channel as a multi-frame synchronous channel and a third channel as a test channel.

The present invention further provides a circuit for 10 allocating a test channel in a multi-channel trunk line of a communication system, comprising a call controller for controlling a call; an IPC (Inter Processor Communication) node part connected to said call controller, for controlling an IPC node; a maintenance controller of a base station controller, connected to said IPC node part; an IPC part connected to the IPC node part; a cable connecting said maintenance controller to said IPC part; and a base station transceiver system connected to said IPC part by way of a PCM (Pulse Code Modulation) cable.

Preferably, the communications system is a radio communications system. The test may be a bit error rate (BER) test. Preferably, the test is successively performed on the data channels of the trunk.

The trunk may comprise thirty-two channels, the first channel is the first such channel, the second channel is the seventeenth such channel and the third channel is the thirty-second such channel.

The method may further comprise, in the test enable state, substituting the second channel for a data channel under test; transmitting or receiving test data over the test channel; and correspondingly receiving or transmitting test 35 data over the data channel under test.

The maintenance controller may comprise an alarm control processor and a line bit error rate tester.

4 BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described by way of example with reference to the accompanying drawings in which: 5 figure 1 is a block diagram for explaining a bit error rate (BER) path according to an embodiment of the present invention; figure 2 is a diagram illustrating the structure of a line interface Ei board assembly (LIEA) according to an embodiment of the present invention; figure 3 is a detailed block diagram of a call controller, a line BER tester, and an IPC processor board of figure 1; figures 4A through 4E are timing diagrams of signals occurring within the circuit shown in figure 3; and figures 5 and 6 are time diagrams of signals occurring within the circuit shown in figure 3, in a BER test disable state and a BER test enable state, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 is a block diagram illustrating a bit error rate (BER) path according to an embodiment of the present invention. As illustrated, a call controller 101 is connected to an IPC (Inter Processor Communication) node part 103 for controlling an IPC node. The IPC node part 103 is connected to a maintenance controller 105 of the base station controller, and an IPC part 107. The maintenance controller 105 is connected to the IPC part 107 by way of a cable SHW, which may be a sub-highway cable. The IPC part

107 is connected to a basestation transceiver system (BTS) 109 by way of a PCM (Pulse Code Modulation) cable ill, which is the trunk line to be tested. The maintenance controller 105 includes an alarm control processor 112 and a line bit error rate tester 113. The IPC part 107 includes an IPC processor board 115 and a line interface E1 board assembly 116. The base station transceiver system 109 includes an IPC processor 117 and a line interface Ti board assembly 118.

Figure 2 illustrates a channel allocation of line interface E1 board assemblies 116 according to an aspect of the present invention. As illustrated, respective line interface E1 board assemblies LIEA-A0 through LIEA-A7 (corresponding to eight base stations) each include eight links LINKO-LINK7. Each of the links LINKO-LINK7 includes 32 channels CHO-CH31. The first channel CHO is allocated for a frame synchronisation channel and the last channel CH31 is allocated for the BER test channel. The remaining channels CH1-CH30 are for packet data channels.

Figure 3 illustrates a detailed block diagram of a circuit for allocating channels CHO-CH31 of a trunk, according to an aspect of the present invention. The IPC processor board 115 is composed of a receiver 301 and a transmitter 302.

The receiver 301 converts input data DIFF_DATA_1-8 into PCM data BTPCM for processing, and the transmitter 302 converts PCM data BRPW_1-8 into transmission data DIFF_DATA_1-8.

The line interface E1 board assembly 116 allocates the channel CH31 for the BER test, and the channels CHO-CH30 for transmitting the transmission data through the transmitter 302 according to a frame pulse and a clock signal, so as to form a transmission frame. A time switch 308 is connected to the IPC board 115 and the line interface E1 board assembly 116, to set the communication channels CHO-CH30 for transmitting the transmission data and to set the channel CH31 for the BER test. The line BER tester 113 includes a BER test data receiver 304 and a BER test data transmitter 305. The BER test data receiver 304 receives the BER test data DIFF - BERTAX through the channel CH31 set by the time switch 308. The BER test data transmitter 305 transmits the BER test data DIFF-BERTAX through the channel CH31 set by the time switch 308.

A CPU (Central Processing Unit) 309 generates control signals to control an overall operation of the system. A command data generator 311 generates command clock signals to the line interface E1 board assembly 116 under the 6 control of the CPU 309.

Figures 4A to 4E are timing diagrams of the clock signals generated from the command data generator 311 of figure 3.

Specifically, figure 4A shows a frame pulse FP; figure 4B shows a data transmission/reception packet clock 2M; and figures 4C to 4E show clock signals /FOI, 4M, /4M generated from the line interface Ei board assembly (WEA) 116 based on the clock signals FP, 2M of figures 4A and 4B.

Figures 5 and 6 show time diagrams of the circuit shown in figure 3, in a BER test disable state and a BER test enable state, respectively. Signals TX (RX) PKT= and TX (RX) PKTDTA represent processing packet clock and data, respectively.

Now, referring to f igures 1 to 6, an embodiment of the present invention will be described in detail.

The line BER tester 113 tests a transmission line ill according to mode data and command data received from the alarm control processor 112 via a TD-BUS. Upon completion of the test, the line BER tester 113 transmits the test results to the alarm control processor 112 in such a way that the line BER tester 113 sets a flag indicating transmission of data to the alarm control processor 112. The alarm control processor 112 reads the result data, if the flag is set.

In communications between the alarm control processor 112 and the line BER tester 113, an address is divided into a data transmission/reception region and an interrupt request region. The transmission/reception data is in the form of an ASCII code or an hexadecimal code. Further, since the number of data bytes required differs according to circumstances, the last byte of each data transmission should be 110Dh11 which is a carriage return, in order to indicate the last byte of the data.

7 After writing the data in the data reception region of the line BER tester 113, the alarm control processor 112 writes interrupt sign data llEEhIl in the reception interrupt region (7FFh) of the line BER tester 113 in order to notify completion of the data write operation to the line BER tester 113, and thereby to generate an interrupt. The line BER tester 113 reads out the received data, and reads the interrupt region to clear the interrupt sign.

The transmission line test is performed to check a BER characteristic of the PCM cable 111 of figure 1, so the line BER tester 113 must be connected to the line interface E1 board assembly 116. To do so, the SHW (sub-highway) cable employs a differential signalling method, and the time slot is determined by software.

The line interface E1 board assembly 116 allocates the channel CH31 for the BER test channel, as shown in figure 2, by means of the time switch 308. The BER test data is transmitted/ received through the BER test data receiver 304 and the BER test data transmitter 305. In addition, the packet data is transmitted and received through the channels CHO-CH30 by means of receiver 301, transmitter 302, LIEA 116 and PCM cable 111.

With reference to figures 4A to 4E. the clock pulse 2M of 2MHz frequency (figure 4B), the clock pulses 4M, /4M of 4MHz frequency (figures 41) and 4E) and a signal /FOI, which represents an 8Khz clock which is a synchronised clock of the time switch, are derived from the frame synchronous pulse FP (figure 4A).

By designating a specified port of the line interface E1 board assembly 116, it is determined whether the BER test between the base station controller (IPC part) 107 and the base station transceiver system 109 is enabled or disabled. Referring to figure 3, in the BER test disable state (figure 5), the line interface E1 board assembly 116 allocates the channel CHO for the frame synchronisation 1 8 channel and the channel CH16 for a multi-frame synchronous channel by means of the time switch 308. However, in the BER test enable state (figure 6), the line interface E1 board assembly 116 allocates the channel CH16 for a packet data channel and the channel CH31 for the BER test channel by means of the time switch 308. The BER test may thereby be performed without loss of the packet data, since any packet data channel.undergoing a BER test may be replaced by the channel CH16.

If the CPU 309 requests the BER test and the channel allocation of the line interface E1 board assembly 116, the command data generator 311 generates the frame pulse FP of figure 4A and the 2MHz clock of figure 4B to the line interface E1 board assembly 116. In the BER test enable mode (figure 6), the time switch 308 allocates the channel CH31 for the BER test channel, and the CPU 309 enables the BER test data transmitter 305 to transmit the BER test data through the BER test channel CH31.

However, in the BER test disable mode (figure 5), the packet data is communicated by using the channels CHO-CH30 through the IPC processor board 115, and the CPU 309 enables the receiver 301 of the IPC processor board 115 to receive the packet data through the channels CHO-CH30.

As described above, the operator can input the BER test command at a base station manager (BSM) to test the trunk 111 even during the on-line service state of the trunk, i.e. while the system is in a normal operation, without using the trunk test equipment, thereby reducing the trunk test time. Further, the trunk test can be performed at a any specified base station manager anytime, without restriction of time and space.

Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments. In 9 particular, each trunk may comprise a number of channels other than 31, and any of such channels may be chosen for any of the functions described above.

The method and circuit of the invention may be applied to types of test other than bit error rate tests. The trunk line tested may be a cable, a radio link or any other type of multi-channel trunk line.

Claims

1. A method for allocating a test channel in a multichannel trunk line of a communication system, comprising: allocating a number of data channels; allocating, in a test enable state, a first channel as a frame synchronisation channel, a second channel as a further data channel and a third channel as a test channel, thus enabling testing of the data channels of the trunk through the test channel; and allocating, in a test disable state, a first channel as a frame synchronisation channel, a second channel as a multi-frame synchronous channel and a third channel as a test channel.

is

2. A method according to claim 1 in which the communications system is a radio communications system.

3. A method according to claim 1 or claim 2 in which the test is a bit error rate (BER) test, successively performed on the data channels of the trunk.

4. A method according to any preceding claim in which the trunk comprises thirty-two channels, the first channel is the first such channel (CHO), the second channel is the seventeenth such channel (CH16), and the third channel is the thirty-second such channel (CH31).

5. A method according to any preceding claim, further comprising, in the test enable state: substituting the second channel for a data channel under test; transmitting or receiving test data over the test channel; and correspondingly receiving or transmitting test data over the data channel under test.

6. A circuit for allocating a test channel in a multichannel trunk line of a communication system comprising:

11 a call controller for controlling a call; an IPC (Inter Processor Communication) node part connected to said call controller, for controlling an IPC node; a maintenance controller of a base station controller, connected to said IPC node part; an IPC part connected to the IPC node part; a cable connecting said maintenance controller to said IPC part; and - a base station transceiver system connected to said IPC part by way of a PCM (Pulse Code Modulation) cable.

7. A circuit for allocating a test channel in a multi channel trunk line of a communication system, comprising means for allocating a number of data channels; means for allocating, in a test enable state, a first channel as a frame synchronisation channel, a second channel as a further data channel and a third channel as a test channel, thus enabling testing of the data channels of the trunk through the test channel; and means for allocating, in a test disable state, a first channel as a frame synchronisation channel, a second channel as a multi-frame synchronous channel and a third channel as a test channel.

8. A circuit according to claim 6 or 7 in which the test is a bit error rate (BER) test.

A circuit according to claim 6,7 or 8, in which the test is successively performed on the data transmission channels of the trunk.

10. A circuit according to any one of claims 6-9, in which the trunk comprises thirty-two channels, the first channel is the first such channel (CHO), the second channel is the seventeenth such channel (CH16), and the third channel is the thirty-second such channel (CH31).

11. A circuit according to any one of claims 6-10, in 12 which the communications system is a radio communications system.

12. A circuit according to claim 6, in which the maintenance controller comprises an alarm control processor and a line bit error rate tester.

13. A method of allocating a test channel in a multichannel trunk line of a communication system, the method being substantially as described herein with reference to and/or as illustrated in the accompanying drawings.

14. A circuit for allocating a test channel in a multichannel trunk line of a communication system, the circuit being substantially as described herein with reference to and/or as illustrated in the accompanying drawings.