CN1114331C - Channel allocation method and circuit for testing trunk line in radio communication system - Google Patents

Channel allocation method and circuit for testing trunk line in radio communication system Download PDF

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Publication number
CN1114331C
CN1114331C CN98107916A CN98107916A CN1114331C CN 1114331 C CN1114331 C CN 1114331C CN 98107916 A CN98107916 A CN 98107916A CN 98107916 A CN98107916 A CN 98107916A CN 1114331 C CN1114331 C CN 1114331C
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China
Prior art keywords
channel
error rate
rate test
distribute
circuit
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Expired - Fee Related
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CN98107916A
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CN1206318A (en
Inventor
元允好
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/04—TPC
    • H04W52/18—TPC being performed according to specific parameters
    • H04W52/22—TPC being performed according to specific parameters taking into account previous information or commands
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W24/00—Supervisory, monitoring or testing arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/204—Multiple access
    • H04B7/216—Code division or spread-spectrum multiple access [CDMA, SSMA]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

A circuit for allocation of bit error rate checking channel. The circuit provides a method for a BER(bit error rate) test enable state and disable state by a operation according to a channel allocating method. In bit error rate checking enable state, device provides allocation of first channel CHO as frame synchronization channel, seventeenth channel CH16 as packet data transmission channel, and thirty second channel as bit error rate checking channel. In bit error rate checking enable state, trunk line is tested by means of bit error rate checking. In mode with blocked bit error rate checking, device reallocates seventeenth channel CH16 for its use as inter-frame synchronization channel.

Description

Method for channel allocation in the wireless communication system and trunk test circuit
Technical field
The present invention relates to wireless communication system, be specifically related to method for channel allocation and trunk test circuit in the wireless communication system.
Background technology
Generally, trunk is connected between base station controller (BSC) and the base station transceiver system (BTS) alternately, is used to send grouped data.Whether the running check trunk is in the normal grouped data that sends.In addition, also use a line interface E1 assembly (LIEA) for the trunk interface board.But 8 link LINKO-LINK7 of line interface E1 component palette outfit as many as shown in Figure 2, allow the interface of maximum 8 E1 trunk lines.
Connection between base station controller and the base station transceiver system is realized by E1 or t1 trunk line that generally data send by E1 or t1 trunk line with the form of grouping.There are two kinds of known methods can check that whether trunk line is in the normal data that send.First method adopts loopback, by using the loopback cable, send pseudo-random data with the ad-hoc relay line testing device, and the pseudo-random data of accepting to send comes specified data whether normally to be sent.Another kind of known method is by with the loopback cable and carry out loopback test with LIEAF/W and come loopback.However, traditional method is just available at the off-line state, so the underway line that continues can not send grouped data when testing.Because loopback test will repeat 5 times, it will take the very long testing time, and traditional method of testing is subjected to spatial limitation in addition.
Summary of the invention
Therefore an object of the present invention is to provide a kind of trunk line method of testing and circuit, wherein the operator goes up test command of input at base station manager (BSM), and is not subjected to the restriction in time and space.
Another object of the present invention provides a kind of by sending the method for authentic data test trunk.
What a further object of the invention was is for the circuit that is used to carry out the BER test, keeps the online service state of E1 or t1 trunk line simultaneously.
Above purpose is by provide one to be used to distribute the circuit of BER (error rate) test channel to realize at wireless communication system.According to a kind of form of the present invention, form a circuit that is used to distribute the BER test channel.Circuit comprises a call controller that is used for controlling call.Circuit also comprises an internal processor communication node part, and it is operably connected to a controller and controls IPC (intercommunication processor) node.Circuit also comprise one be connected with the IPC node section safeguard controller.Also comprise an ipc section and be connected with the IPC node section.A HW highway cable is placed on to be safeguarded between controller and the ipc section.At last, base station transceiver system is by PCM cble and ipc section interface.
According to a method of the present invention, communication system places bit error rate test enable state.At BER test enable state, the first channel CH0 is assigned with as frame synchronizing channel, and the 17th channel (CH16) is as packet data transport channel, and the 32nd channel (CH31) is as the BER test channel.Integrality by BER test channel test trunk.This method also requires a BER test illegal state.At BER test illegal state, the first channel CH0 is assigned with as frame synchronizing channel, and the 17th channel CH16 is reallocated as multiframe synchronizing channel and the 32nd channel CH31 and still is assigned with the test channel as BER.
Description of drawings
By description of the preferred embodiment of the present invention also with reference to the accompanying drawings, above-mentioned purpose of the present invention and other benefit will be more than you know.
Fig. 1 is the block diagram that bit error rate (BER) path is described according to one embodiment of present invention.
Fig. 2 is the figure according to embodiment of the invention explanation line interface E1 board component (LIEA) structure.
Fig. 3 is the call controller (101) of Fig. 1, the detailed diagram of circuit BER tester (113) and IPC processor plate (115).
Fig. 4 A is the sequential chart of circuit shown in Figure 3 to Fig. 4 E;
Fig. 5 is the sequential chart of circuit shown in Figure 3 to Fig. 6, is in BER test illegal state and BER test enable state respectively.
Embodiment
Describe the preferred embodiments of the present invention below with reference to the accompanying drawings in detail, for the purpose of understanding, identical reference symbol is represented identical parts in the accompanying drawing.Although for theme of the present invention is described, specific definition and explanation concrete example embodiment of the present invention, one of ordinary skill in the art also can be implemented the present invention by description of the invention without these details.In addition, the unnecessary known function and the detailed description of structure are not disclosed.
Fig. 1 is the block diagram that bit error rate (BER) path is described according to one embodiment of present invention.As described, call controller 101 is connected to IPC (intercommunication processor) node section 103, is used to control the IPC node.IPC node section 103 is connected to safeguarding on controller 105 and the ipc section 107 of base station controller.Safeguard that by public cable SHW accessible by road controller 105 is connected to ipc section 107.Ipc section 107 is connected to base station transceiver system (BTS) 109 by PCM (pulse-code modulation) cable 111.Safeguard that controller 105 comprises an alarm processor controls 112 and circuit bit error rate tester 113.Ipc section 107 comprises IPC processor plate 115, line interface E1 board component (LIEA) 116.Base station transceiver system 109 comprises IPC processor 117 and line interface and board component 118.
Fig. 2 is the figure according to embodiment of the invention explanation line interface E1 board component (LIEA) structure.As described, each line interface E1 board component, LIEA-A0 to LIEA-A7 corresponding to 8 base stations and comprise 8 link LINK0-LINK7.Corresponding link, LINK0-LINK7 comprises 32 channel CH0-CH31, and wherein the first channel DHO is assigned with as frame synchronizing channel, and the last item channel CH31 is assigned with the test channel as BER, and remaining channel CH1-CH30 is assigned with as Packet Data Channel.
Fig. 3 represents according to the present invention by utilizing the continue detailed circuit diagram of line of channel CH0-CH31 distributor.With reference to figure 3, IPC processor plate 115 comprises a receiver 301 and a transmitter 302.Receiver 301 receives input data (DIFF DATA1-8) to send.Line interface E1 board component 116 allocated channel CH0-CH30, sending signals according to frame pulse and clock signal by transmitter 302, and allocated channel CH31 is used for the BER test, thereby forms transmission frame.
Time switch 308 is connected to IPC plate 115 and line interface E1 board component 116.Time switch 308 provides signal to test to help to distribute the communication channel CH0-CH30 that sends transmission signals and to be used for BER to line interface E1 board component 116, thereby forms transmission frame.
Time switch 308 is connected to IPC plate 115 and line interface E1 board component 116.Time switch 308 provides signal to help to distribute the communication channel CH0-CH30 that sends transmission signals and to be used for the channel CH31 that BER tests to line interface E1 board component 116.
Circuit BER tester 113 comprises BER test data receiver 304 and BER test data transmitter 305.The channel CH31 of BER test data receiver 304 by putting by time switch 308 height.BER test data receiver 304 receives BER test data DIFF BERTAX by the channel CH31 that is provided with by time switch 308.BER test data transmitter 30 sends BER test data DIFF_BERTAX by the channel CH31 that is provided with by time switch 308.The integrated operation that CPU (CPU) 309 produces the control signal control system.Common data generator 311 produces common clock signal under the control of CPU309 line interface E1 board component 116.
Fig. 4 A-4E is the sequential chart of the clock signal that produces of the common data generator 311 of Fig. 3.Especially, Fig. 4 A represents a frame pulse, and Fig. 4 B represents that a data transmission/reception grouping clock and Fig. 4 C represent the clock signal of line interface E1 board component 116 according to the clock generating of Fig. 4 A and 4B to 4E.
The sequential chart of Fig. 5 and 6 expressions circuit shown in Figure 3 is in BER test illegal state and BER test enable state respectively.
Describe the preferred embodiments of the present invention referring now to Fig. 1 in detail to Fig. 6.Circuit BER tester 113 is according to the mode data and the order data test transmission line that receive through TD BUS from alarm processor controls 112.After the test result, circuit BER tester 113 is to alarm processor controls 112 flourishing test results and indication sends sign from data to alarm processor controls 112 is set.If sign is set up, alarm processor controls 112 just reads test result data.
In order to help to alarm the interface between processor controls 112 and the circuit BER tester 113, an address is provided, this address is divided into data transmission/acceptance domain and interrupt requests territory.Address in data transmission/acceptance domain is the form or 16 ary codes of ASCII character preferably, and one of them byte comprises 8 bits.In addition, because the data word joint number changes with situation, last byte of data should be " OD ".This description symbolic representation carriage return is also represented last bytes of data.In addition, after the Data Receiving territory of line tester 113 writes data, alarm processor controls 112 is interrupted territory (address 7FFH) with the reception that data " EEH " write circuit BER tester 113, to the end of circuit BER tester 113 expression data write operations, interrupts thereby produce.
Have no progeny during BER tester 113 receives and read the data of reception, and read the interruption territory to remove interrupt signal.Carry out the BER characteristic of transmission line test, and circuit BER tester 113 should be connected to line interface E1 board component 116 with the PCM cable of controlling chart 1.In order to do like this, the SHW cable adopts the differential signal method, determines time slot by software.About channel allocation, line interface E1 board component 116 allocated channel CH31 are as the BER test channel, as shown in Figure 2.
With reference to figure 3, line interface E1 board component 116 distributes the last item channel, and promptly CH31 as the 308BER test channel, therefore selects route through BER test data receiver 304 and BER test data transmitter 305 the BER test data by time switch.In addition, grouped data is by remaining channel, and CH0-CH30 is sent out and receives.
To 4E, the clock pulse of 2MHZ (Fig. 4 B) obtains (Fig. 4 A) with the clock pulse (Fig. 4 D and 4E) of 4MHZ and signal FOI from frame-synchronizing impulse with reference to figure 4A.
The appointment of the particular port of line interface E1 board component 116 determines that the BER test between base station controller 107 and the base station transceiver system 109 is enabled or is under an embargo.With reference to figure 3, at BER test illegal state (Fig. 5), line interface E1 board component 116 is the multiframe synchronizing channel by time switch 308 allocated channel CH0 as frame synchronizing channel and channel CH16.But, at BER test enable state (Fig. 6), line interface E1 board component 116 by time switch 308 allocated channel CH16 as Packet Data Channel and CH31 as the BER test channel.
If the channel allocation of CPU request BER test and line interface E1 board component 116, then order data generator 311 produces the frame pulse FP of Fig. 4 A and the 2MHZ clock signal of Fig. 4 B, and these signals are provided for line interface E1 board component 116.In BER test enable pattern (Fig. 6), time switch allocated channel CH31 is the BER test channel, and CPU enables BER test data transmitter 305, makes it pass through BER test channel CH31 and sends the BER test data.But, at BER test prohibited mode (Fig. 5), utilize channel CH0-CH30 to transmit data by IPC processor plate 15, CPU309 makes IPC processor plate 115 receive data by channel CH0-CH30.
As mentioned above, even the operator also can go up input BER test command with test trunk at base station manager (BSM) at the online service state of trunk line, when promptly being in normal operating state, and need not to use the trunk line testing equipment, thereby reduced the trunk line testing time in system.In addition, the trunk line test can be carried out at the certain base station manager at any time, and is not subjected to the restriction in time and space.
Although exemplary embodiment of the present invention has been described with reference to the drawings, be to be understood that the present invention is not subjected to the restriction of these specific embodiments, one of ordinary skill in the art can be carried out other modification under the premise of without departing from the spirit of the present invention.

Claims (9)

1. distribute the method for error rate test channel in the communication system of many channels that are useful on test trunk, this method may further comprise the steps:
By distributing frame synchronizing channel, packet transmission channel and error rate test channel provide the error rate test enabled state;
Be used for the multiframe synchronizing channel error rate test illegal state is provided by redistributing above-mentioned packet transmission channel.
2. be used to distribute the method for error rate test channel as claim 1, wherein a plurality of channels comprise first channel, last channel, with at least one intermediate channels, and wherein said frame synchronizing channel is described first channel, described error rate test channel is described last channel, and described packet transmission channel is one of at least one intermediate channels.
3. be used to distribute the method for error rate test channel as claim 2, wherein said a plurality of channels comprise 32 channels, and wherein said packet transmission channel is the 17th channel.
4. be used to distribute the method for error rate test channel as claim 1, wherein in the error rate test enabled state, distribute first channel (CHO) as frame synchronizing channel, article 17, channel (CH16) is as packet data transport channel, article 32, channel (CH31) is as the error rate test channel, by error rate test channel test trunk line; At the error rate test illegal state, described first channel is as described frame synchronizing channel, and described the 17th channel (CH16) is as the multiframe synchronizing channel, and described the 32nd channel is as described error rate test channel.
5. distribute the circuit of error rate test channel in the communication system of many channels that are useful on test trunk, it comprises:
Be used to control the call controller that respectively cries;
The intercommunication processor node part that links to each other with described call controller is used to control the intercommunication processor node;
Base station controller safeguard controller, partly be connected with described intercommunication processor node, with the intercommunication processor part that partly is connected with described intercommunication processor node;
With the described sub-HW highway cable of safeguarding that controller and described intercommunication processor partly are connected;
The base station transceiver system that partly is connected by PCM cble and described intercommunication processor.
6. define the circuit that is used to distribute the error rate test channel as claim 5, the wherein said controller of safeguarding comprises an alarm processor controls and circuit bit error rate tester.
7. define the circuit that is used to distribute the error rate test channel as claim 5, wherein said intercommunication processor part comprises that also line interface assembly, described line interface assembly distribute a plurality of channels to realize an error rate test enabled state and error rate test illegal state.
8. define the circuit that is used to distribute the error rate test channel as claim 7, wherein said a plurality of channel comprises first, last and at least one intermediate channels, and wherein the line interface assembly distributes described first channel as synchronizing channel in described error rate test enabled state, described last channel is as the error rate test channel, and further distributes one of described intermediate channels to redistribute described intermediate channels as the multiframe synchronizing channel as packet data transport channel and at described error rate test illegal state.
9. define the circuit that is used to distribute the error rate test channel as claim 8, wherein said call controller also comprises a time switch, and described line interface assembly distributes from described time switch received signal and according to it.
CN98107916A 1997-05-29 1998-04-30 Channel allocation method and circuit for testing trunk line in radio communication system Expired - Fee Related CN1114331C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR21546/97 1997-05-29
KR1019970021546A KR100258150B1 (en) 1997-05-29 1997-05-29 Method and circuit for channel assign trunk line test in rf communication system
KR21546/1997 1997-05-29

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CN1206318A CN1206318A (en) 1999-01-27
CN1114331C true CN1114331C (en) 2003-07-09

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JP (1) JP3154972B2 (en)
KR (1) KR100258150B1 (en)
CN (1) CN1114331C (en)
DE (1) DE19818451A1 (en)
FR (1) FR2764150B1 (en)
GB (1) GB2326801B (en)
RU (1) RU2146417C1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003276959A1 (en) 2002-09-30 2004-04-23 Interdigital Technology Corporation Reference transport channel on/off status detection and reselection

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US3259695A (en) * 1961-11-27 1966-07-05 Nippon Electric Co Malfunction monitoring of time-division multiplex pcm equipment
US4022979A (en) * 1975-12-29 1977-05-10 Bell Telephone Laboratories, Incorporated Automatic in-service digital trunk checking circuit and method
US4149038A (en) * 1978-05-15 1979-04-10 Wescom Switching, Inc. Method and apparatus for fault detection in PCM muliplexed system
GB2111348B (en) * 1981-11-12 1985-06-12 Plessey Co Plc V.f. receivers for use in digital switching systems
US4736377A (en) * 1986-02-11 1988-04-05 Bradley Telcom Corp. Method for determining reliability of high speed digital transmission by use of a synchronized low speed side channel
EP0333942A1 (en) * 1988-03-22 1989-09-27 Hewlett-Packard Limited Monitoring of digital transmission systems
US5453989A (en) * 1992-03-19 1995-09-26 Fujitsu Limited Subscriber digital transmission system
JPH06169299A (en) * 1992-11-30 1994-06-14 Fujitsu Ltd Transmission line monitor system
JPH0715405A (en) * 1993-06-25 1995-01-17 Nec Corp Digital transmission line test method and digital transmission line test system
GB9509554D0 (en) * 1995-05-11 1995-07-05 Newbridge Networks Corp On fault loop-back detection on digital trunks

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Publication number Publication date
JP3154972B2 (en) 2001-04-09
FR2764150B1 (en) 2002-01-18
CN1206318A (en) 1999-01-27
KR100258150B1 (en) 2000-06-01
JPH1141195A (en) 1999-02-12
FR2764150A1 (en) 1998-12-04
RU2146417C1 (en) 2000-03-10
DE19818451A1 (en) 1998-12-10
GB2326801B (en) 1999-10-20
KR19980085451A (en) 1998-12-05
GB2326801A (en) 1998-12-30
GB9806859D0 (en) 1998-05-27

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