GB2315598A

GB2315598A - Process for forming a large grain polysilicon part for a semiconductor device.

Info

Publication number: GB2315598A
Application number: GB9715430A
Authority: GB
Inventors: Satoru Sugiyama
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1996-07-23
Filing date: 1997-07-22
Publication date: 1998-02-04
Also published as: KR980012099A; GB9715430D0; JPH1041245A

Abstract

A process for manufacturing a polysilicon current carrying part 10 in a semiconductor device having at least a circuit pattern 6 on a semiconductor substrate 1. The initial part of the polysilicon is formed whilst adjusting the pressure to reduce the generation of growth seeds, and then the remainder of the polysilicon is formed under a higher pressure than the initial pressure. Reducing the concentration of growth seeds increases the size of the polysilicon grains that form, and the consequential reduction in the number of grain boundaries increases the polysilicon conductivity. The invention may be applied whilst forming a capacitative electrode of a DRAM.

Description

Process for Manufacturing Semiconductor Device BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a process for manufacturing a semiconductor device, particularly to a process for forming a current-carrying part such as a wiring and an electrode composing a semiconductor device.

2. Description of the Related Art Recently, a two-dimensional design rule for a circuit pattern has been increasingly refined as a semiconductor device has been rapidly integrated.

A non-metal current-carrying part such as a non-metal wiring has been formed by adding an impurity such as phosphorous (referred to as "P") to a polysilicon (referred to as "Poly-Si") film to reduce its layer resistance, giving a conductivity, and by patterning it before or after the addition of the impurity.

Non-metal conductive materials have been used for a gate wiring part which does not allow any contamination by heavy metals, such as a capacitive part of DRAM, while it has become difficult to ensure an adequate conductivity due to problems such as increase of electric resistance caused by refinement of a circuit.

A process for formation of a non-metal currentcarrying part of the prior art will be described with reference to the accompanying drawings.

As shown in Figure 3(a), a gate oxide film (2) and an element separation region (3) are formed on a semiconductor substrate (1), and then a Poly-Si film (14) to be a gate wiring is formed by LP-CVD. The Poly-Si film is generally formed by introducing monosilane (SiH4) into a furnace kept at a pressure equal to or below 1 Torr, at a temperature of 600 to 650 OC.

A gas as an impurity source such as POCl3 is then introduced into the diffusion furnace kept at a temperature 700 to 950 OC, to diffuse the impurity in the Poly-Si film. During the diffusion, as shown in Figure 3(b), a PSG layer (5) grows on the surface of the Poly-Si film, and P diffuses along with a grain boundary from the PSG layer into the Poly-Si film. Then, it is heated at a temperature higher than that in the impurity diffusion process, generally at 750 to 1000 or, in an atmosphere of inert gas such as nitrogen, to activate the impurity for reducing the resistivity of the Poly-Si film.

The PSG layer is then removed and the substrate is subject to patterning, to form a gate wiring (4) as shown in Figure 3(c).

In the above process, the diffusion of the impurity into the Poly-Si film is generally conducted by ion implantation.

The patterning may be performed at any stage; for example, when performed before the diffusion of the impurity, the diffusion surface may be enlarged and the volume of Poly-Si being permeated may be reduced, so that a diffusion efficiency may be improved and the resistivity of the Poly-Si film may be favorably reduced .

Other methods have been also proposed; for example, P-doped polysilicon CVD and P-doped amorphous CVD using an impurity diffusion during deposition. Furthermore, for example, JP-A 6-20990 has disclosed a process in which a nitride is deposited on a substrate surface by forming growth seeds of Poly-Si in an atmosphere of NH3 and HCl gases.

However, these processes of the prior art for forming a non-metal wiring using Poly-Si and an impurity diffusion cannot form a current-carrying part with an adequately low resistance, and particularly, when applied to a capacitive part of DRAM, these processes have frequently caused a hold failure due to increase of the resistance by refinement of a contact size.

It is known that a resistivity after an impurity diffusion depends on the size of Poly-Si grains; the larger the grain size, the lower the resistivity. Thus, the above failure may occur because the processes of the prior art cannot give a sufficiently low resistance to support the recent refinement due to the small size of Poly-Si grains.

A process using P-doped amorphous CVD and annealing and subsequent recrystallization has a drawback that several thousands of particles caused by a P-dopant gas are generated during deposition of an amorphous material, which is inappropriate for mass production.

A process, as described in JP-A 6-20990, using a nitride to generate seeds for Poly-Si growth has a drawback that, as described in its detailed description, when applied to a capacitive part of DRAM, it increases an electric resistance between a lower electrode of capacitive layer and a diffusion layer due to deposition of an insulator on the bottom of the contact since the nitride itself is an insulating material, although the area of the capacitive part is increased.

SUMMARY OF THE INVENTION An objective of at least the preferred attod1rtnts of this invention is to provide a low-resistance current-carrying part for speeding up a semiconductor device.

Another such objective is to solve the problem of increased resistance in a current-carrying part associated with a recent refining trend for achieving a highly-integrated semiconductor device.

In cne aspect this invention provides a process for marxafacturlng a semiconductor device having at least a circuit pattern on a semiconductor substrate, comprising forming the non-metal current-carrying part in the circuit pattern with polysilicon; and adjusting a pressure during the initial stage of the formation of the polysilicon part to reduce generation of growth seeds.

In another aspect this invention provides a process for manufacturing a semiconductor device having at least a circuit pattern on a semiconductor substrate, comprising forming the non-metal current-carrying part in the circuit pattern with polysilicon; adjusting a pressure during the initial stage of the formation of the polysilicon part to reduce generation of growth seeds; and then forming the polysilicon part under a higher pressure than the initial pressure.

We have focused attention on the phenomenon that during formation of the Poly-Si film to be a current-carrying part such as a wiring, growth seeds are generated in the initial stage, single crystals grow centering the seeds, and then contact between the crystals determines the size of Poly-Si grains.

Thus we have attained this invention including a measures for controlling the grain size by appropriately adjusting a pressure in the initial stage of deposition for reducing generation of the seeds. Reducing generation of the seeds in the initial stage of Poly-Si deposition leads to increase of the size of Poly-Si grains growing thereafter, resulting in an adequate reduction in a layer resistance after an impurity diffusion.

An advantage of at least the preferred eibodits of this invention iS;that they can provide a wiring part having a sumciently low electric resistance to support a non-metal wiring which has been increasingly refined, to improve properties of a semiconductor device because this invention permits to increase the size of Poly-Si grains in the wiring part to reduce the layer resistance after an impurity diffusion.

Another advantage of the preferred entodiments is that they can be applied to formation of a capacitive part of DRAM, leading to reduction of the resistance of the electrode part and reduction of the incidence of a hold failure because it can reduce the layer resistance by increasing the size of the grains as described in terms of the above advantage.

In addition, the preferred embodiments can have the advant that a coverage is improved, ensuring a low contact resistance.

Because of these advantages, the preferred enbodiments of this invention can provide a high-speed and highly-integrated semiconductor device.

BRIEF DESCRIPTION OF THE DRAWIN The invention will be described merely by way of example with referee to the accompanying drawings wherein: Figure 1 is a manufacturing flowchart of an embodiment of this invention.

Figure 2 is a manufacturing flowchart of another embodiment of this invention.

Figure 3 is a manufacturing flowchart of a semiconductor of the prior art.

Figure 4 illustrates polysilicon films by manufacturing processes of this invention and of the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A gate oxide film (2) and an element separation region (3) are formed on a semiconductor substrate (1) as the prior art (Fig.l(a)).

A Poly-Si film (14) to be a gate wiring is then formed by LP-CVD, introducing an inorganic gas containing Si into a reaction furnace under a reduced pressure, preferably at a temperature of 600 to 650 or. In particular, it is recommended to keep the pressure equal to or below 0.4 Torr in the initial stage of the deposition. In an example of this embodiment, seeds were generated in the initial stage of the deposition by introducing 20 % monosilane gas diluted with He (20 % SiH4/He) at a rate of 2000 sccm into a reaction furnace kept at 650 OC and 0.33 Torr. It is recommended to continue the initial deposition under these conditions until a thickness of 100 to 500 A and then stop the seed generation step. In the above example, the deposition was continued under these conditions until the thickness became 300 A. The size of Poly-Si grains is determined in this step (Fig.l(b)). The Poly-Si grains are larger than those formed according to the prior art.

Then, a bulk Poly-Si is formed by increasing the inside pressure of the furnace from the above pressure, preferably to 0.4 to 1.0 Torr (Fig.l(c)). The size of Poly-Si grains has been determined in the above seed-generating step, and is kept until completion of the deposition.

The higher deposition pressure than that during the seed-generating step is selected for improving productivity by increasing the pressure, in the light of a low growing speed in deposition under a low pressure. In this example, a bulk Poly-Si was deposited under a pressure of 0.55 Torr, resulting in a final thickness of 1600 A of the Poly-Si film.

Finally, an impurity diffusion and patterning are performed as in the prior art, to form a gate wiring (4) shown in Fig.l(d).

This invention will be described in detail with reference to Fig.4.

As described above, in the deposition of the Poly Si film, growth seeds (11) are formed, single crystals are formed centering the seeds, and finally the size of the Poly-Si grains is determined due to contact between the single crystals having different orientations.

As shown in Fig.4(a), it is inevitable that the more the number of the growth seeds (11) generated per an area, the smaller the size of Poly-Si grains (12) , and therefore the higher the resistivity of the Poly-Si after an impurity diffusion.

In the process of this invention, this seed-generating process is conducted under a low pressure, to reduce the generation of growth seeds (11) per an area to increase the size of Poly-Si grains (12)(Fig.4(b)). Under a low pressure, a probability of adsorption of gas used in deposition on a substrate, and therefore, the number of the growth seeds (11) per an area is reduced.

Next, the following will describe why a large grain size leads to reduction of the resistivity after an impurity diffusion in Poly-Si, with reference to Figs.4(c) and 4(d). In a crystal zone (13) between grains, there are a number of dangling bonds of Si, causing an electric resistance against current. Assuming that the Poly-Si film is a one-dimensional model of current direction as shown in Figs.4(c) and 4(d), and each Poly-Si grain has an equal electric resistance, a smaller size of Poly-Si grains gives a higher electric resistance per a length due to more crystal zones as shown in Fig.4(c), whereas a larger size of Poly-Si grains gives a lower resistance because of less crystal zones as shown in Fig.4(d).

Table 1 shows the layer resistance (average) of the Poly-Si film after an impurity diffusion as evaluation results for the above example of this embodiment. For comparison, in the table are shown the results obtained when the process was conducted as described in the example except that the initial deposition pressure was 0.55 Torr, and when additionally the deposition temperature varied. In both cases, the thickness of the Poly-Si film was 1600 A and the impurity was diffused at 850 OC for 10 min. in an atmosphere of POCK3.

It is evident from Table l that the P6ly-Si film grown under a lower pressure has a lower resistance.

It is well-known that deposition may be conducted at an elevated temperature, in order to reduce a resistivity by increasing the size of Poly-Si grains. The deposition at an elevated temperature, however, has a drawback of an enlargement of a shallow diffusion layer in terms of thermal history. In contrast, the process of this invention can give better results than the process at a deposition temperature of 20 OC higher, and causes no problems due to deposition at an elevated temperature.

As described above, the process of this invention can readily give a non-metal wiring part with a low resistance.

Table 1

Initial Deposition Pressure \ 0.33 Torr 0.55 Torr Deposition Tern 630tic ~ 1159.6 650t 771.3 993.3 670t ~ 788.5 (Q/O) Embodiment 2 The following will describe the case where the process as described in Embodiment 1 is applied to a capacitive part of DRAM, particularly to formation of an electrode of lower capacitive part.

As shown in Fig.2(a), a circuit pattern (6) and an interlayer insulating film (7) are formed on a semiconductor substrate (1), a diffusion layer (8) is formed on the surface of the substrate, and to the interlayer insulating film is then formed a contact hole (9) penetrating to the diffusion layer.

On the substrate, an electrode of lower capacitive part (10) is formed with Poly-Si(Fig.2(b)).

In the process, as is in Embodiment 1, an inorganic gas containing Si is introduced into a reaction furnace under a low pressure of equal to or below 0.4 Torr, preferably at a temperature of 600 to 650 OC, to form growth seeds of Poly Si, and a bulk Poly-Si is formed under a higher pressure than the initial pressure. In this embodiment, an initial deposition accompanied by generating growth seeds is continued preferably until a thickness of 500 to 1000 A is attained, for supporting a recent trend of refinement of the contact hole.

Recently, the size of the contact hole has been increasingly refined; its opening has now become equal to or below 0.5 Wm.

Thus, to fill the hole without void, it is recommended to conduct the process under a low pressure where mean free path is long.

Then, as shown in Fig.2(b), the substrate is subject to patterning, an electrode of lower capacitive part (10) is formed, and an impurity is diffused to complete the formation of the electrode of lower capacitive part.

Generally, when Poly-Si grains are large and thus each crystal zone is long, an impurity can be more 'readily diffused than small Poly-Si grains, so that a device obtained can give an adequately low contact resistance even when the contact hole is small.

Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

The text of the abstract filed herewith is repeated here as part of the specification.

This invention relates to a process for manufacturing a semiconductor device having at least a circuit pattern on a semiconductor substrate, comprising forming the non-metal current-carrying part in the circuit pattern with polysilicon; adjusting a pressure during the initial stage of the formation of the polysilicon part to reduce generation of growth seeds; and then forming the polysilicon part under a higher pressure than the initial pressure.

The process of this invention in its preferred embodiments can provide a highspeed and highly-integrated semiconductor device.

Claims

What is claimed is:

1. A process for manufacturing a semiconductor device having a circuit pattern on a semiconductor substrate, comprising forming a non-metal current-carrying part in the circuit pattern with polysilicon; and adjusting a pressure during the initial stage of the formation of the polysilicon part to reduce generation of growth seeds.

2. A process for manufacturing a semiconductor device having a circuit pattern on a semiconductor substrate, comprising forming a non-metal current-carrying part in the circuit pattern with polysilicon; adjusting a pressure during the initial stage of the formation of the polysilicon part to reduce generation of growth seeds; and then forming the polysilicon part under a higher pressure than the initial pressure.

3. A process for manufacturing a semiconductor device as claimed in Claim 1 or 2, wherein the pressure in the initial stage of formation of the saidpolysilicon part is equal to or below 0.4 Torr.

4. A process as claimed in any precedig clalm, substantially as herein described.