CN1700415A - Semiconductor device and method for producing the same - Google Patents
Semiconductor device and method for producing the same Download PDFInfo
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- CN1700415A CN1700415A CNA2005100739635A CN200510073963A CN1700415A CN 1700415 A CN1700415 A CN 1700415A CN A2005100739635 A CNA2005100739635 A CN A2005100739635A CN 200510073963 A CN200510073963 A CN 200510073963A CN 1700415 A CN1700415 A CN 1700415A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 161
- 239000013078 crystal Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000007790 solid phase Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 63
- 208000005189 Embolism Diseases 0.000 claims description 48
- 239000007789 gas Substances 0.000 claims description 42
- 239000012535 impurity Substances 0.000 claims description 33
- 238000010438 heat treatment Methods 0.000 claims description 22
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 20
- 238000002425 crystallisation Methods 0.000 claims description 20
- 230000008025 crystallization Effects 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 11
- 229910000077 silane Inorganic materials 0.000 claims description 10
- 239000007787 solid Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001947 vapour-phase growth Methods 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 116
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 15
- 229910052698 phosphorus Inorganic materials 0.000 description 15
- 239000011574 phosphorus Substances 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 14
- 238000009413 insulation Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 230000033228 biological regulation Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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Abstract
A method for producing a semiconductor device includes the steps of forming silicon crystal nuclei on a substrate, depositing first amorphous silicon, depositing second amorphous silicon, and crystallizing the first amorphous silicon and the second amorphous silicon by allowing the crystal nuclei to grow in the solid phase.
Description
The application requires the priority of Japanese patent application JP2004-149647 formerly, and its disclosed content is incorporated herein by reference.
Technical field
The present invention relates to semiconductor device and make the method for these devices, particularly, the present invention relates to a kind of semiconductor device and manufacture method thereof with contact embolism, described contact embolism contains polysilicon.
Background technology
Continually develop out in recent years meticulousr semiconductor device with higher packaging density.For example, the dynamic random access memory (DRAM) with high power capacity (as 1Gbit) has dropped into practical application.
Each memory element among the DRAM all is made of gate transistor and capacitor basically.Be contained in one of diffusion layer in the gate transistor and be connected, and other diffusion layer is connected with an electrode of capacitor with bit line.
According to known method, these elements in the semiconductor device be connected by the contact embolism that forms with the electric conducting material filling contact hole.The spy opens the 2001-024170 Japanese Unexamined Patent Application and has disclosed a kind of polysilicon contact embolism.Te Kaiping 9-074188 Japanese Unexamined Patent Application has disclosed a kind of polysilicon plug structure, comprises heavily doped polysilicon layer and the lightly doped polysilicon layer down gone up.The purpose of this structure is partly to diffuse into the diffusion layer of silicon substrate in order to suppress impurity by embolism, to suppress the junction leakage in the diffusion layer region.
Raising day by day along with meticulous semiconductor integrated circuit is required reduces the cloth line resistance and becomes more and more important.Particularly, in above-mentioned DRAM memory element structure, polysilicon contact embolism is used to make a diffusion region of gate transistor to be connected with bit line, and other diffusion region is connected with capacitor.Herein, an important purpose is the contact resistance that reduces to contact embolism.
By at high temperature, for a long time heat treatment, adopt polysilicon contact embolism can obtain enough low contact resistance in advance.Yet present device is difficult under the long high temperature and anneals, because requirement on devices shallow junction and suppress diffusion of impurities, to obtain the transistor performance of peripheral circuit.
For example, design rule is that the annealing of device in diffusion furnace of 0.11 μ m is only carried out about a few minutes under 850 ℃ or lower temperature.Rapid thermal annealing (RTA) allows to heat-treat under higher temperature, and for example 900 ℃ or higher, but only handle about tens of seconds.
The resistance of above-mentioned wiring is contact interface (interface resistance) and the series resistance that contacts embolism.By the conventional heat treatment of long-time high heat load under the high temperature, can obtain two effects.An effect is to make usually to be gathered into sphere to reduce contact resistance at the interface at the oxide-film that forms naturally at the interface with substrate.Another effect is to allow the growth of contact embolism to have the big crystal grain of less grain boundary.This makes the resistance in the embolism reduce.
Yet as mentioned above, this heat treatment that relates to high heat load is difficult to carry out, and must reduce the cloth line resistance under the low-heat loading condition.The resistance of contact interface once was considered to main resistance.Yet, studies show that the semiconductor substrate surface that the resistance of contact-making surface can be by keeping in touch hole bottom enough cleaning reduces.It is clean that the surface of substrate can keep by the following method, for example, the etch damage layer that removal forms in the process that forms contact hole, as SiC, perhaps by in substrate feeder process, controlling the atmosphere (amount of oxygen and moisture is reduced to several ppm) of low-pressure chemical vapor phase deposition (LP-CVD) device.
On the other hand, to contact the method for embolism resistance be by making si deposition and annealing carry out solid-phase epitaxial growth in the bottom of substrate contact hole in initial feasible reducing.Yet this mode can not satisfy the low-heat load request, because stable solid-phase epitaxial growth requires carrying out the baking of about 10 minutes high temperature (900 ℃ or higher) hydrogen before the deposition of amorphous silicon in same reative cell.
Another feasible method is the impurity concentration that improves in the embolism.Resistance increases to predetermined concentration along with impurity concentration and reduces.On the contrary, if be higher than predetermined concentration, then can be owing to impurity makes resistance increase in the grain boundary isolation.This impurity concentration that embolism resistance is reduced makes and is difficult to further reduce resistance by increasing impurity concentration simply thus.
In addition, open shown in the flat 9-74188 Japanese Unexamined Patent Application as the spy, because the impurity in the contact embolism can be diffused into substrate, therefore excessive high impurity concentration is unfavorable for improving junction leakage.For fear of this problem,, can reduce the impurity concentration of contact embolism bottom and go into substrate to suppress diffusion of impurities according to the patent application of the disclosure.
Yet when this technology was applied to meticulous contact embolism, self can increase embolism resistance.This technology is difficult to ignore the inhibition junction leakage and low contact resistance is provided thus.
Summary of the invention
According to the result of study of the inventor in order to address the above problem, an object of the present invention is to provide a kind of manufacturing and place the low resistance contact embolism of contact hole and the method for low resistance wiring, the present invention also provides a kind of semiconductor device of making by this method.
The invention provides a kind of method of making semiconductor device.This method comprises the following steps: on substrate to form silicon wafer nuclear, deposit first amorphous silicon, and deposit second amorphous silicon, and make the first and second amorphous silicon crystallization by allowing nucleus to grow in the solid phase mode.
The present invention further provides a kind of semiconductor device of making by said method.
According to above-mentioned manufacturing method for semiconductor, form nucleus after, can the lightly doped amorphous silicon layer down of deposit and heavily dopedly go up amorphous silicon layer and heat treatment to form big silicon crystal grain.
The polysilicon contact embolism wiring that obtains contains big silicon crystal grain, and per unit volume contains less grain boundary to reduce resistance thus.This low resistance wiring makes to obtain having than the meticulousr semiconductor device of high assembled density and better performance and the method for this device of manufacturing and is achieved.
Description of drawings
Fig. 1 to 5 shows the technological process sectional view of making the method for semiconductor device according to first embodiment of the invention;
Fig. 6 shows the curve chart that concerns between amorphous silicon layer thickness and the resistance;
Fig. 7 A and 7B are the schematic diagram of grain boundary;
Fig. 8 A and 8B show the curve chart of crystal growth;
Fig. 9 to 15 shows the technological process sectional view of making the method for semiconductor device according to second embodiment of the invention;
Figure 16 to 18 shows the method technological process sectional view of making semiconductor device according to third embodiment of the invention.
Embodiment
Now, with reference to the accompanying drawings semiconductor device and the method for making these devices are described.
First embodiment
The following describes the first embodiment of the present invention.Fig. 1 to 5 shows the main technique flow process sectional view of making the method for semiconductor device according to this embodiment.
With reference to Fig. 1, deposit gate insulating film 2, polysilicon film 3, metal silicide film 4 and insulation mask 5 form gate electrode by photoetching and etching on Semiconductor substrate 1.Then, deposit side wall insulating film 6, and form diffusion layer region 7.Cover these elements with interlayer film 8.
Formation extends to the contact hole 9 (among Fig. 2) of diffusion layer region 7.Lightly doped amorphous silicon layer 10 down of these contact hole 9 usefulness and the heavily doped amorphous silicon layer 11 of going up cover, and the described phosphorus concentration of amorphous silicon layer 10 down is 1 * 10
20Atom/cm
3, and thickness is 3 to 30nm, the described phosphorus concentration of going up amorphous silicon layer 11 is 2 * 10
20To 6 * 10
20Atom/cm
3, and thickness is 100nm or thicker (among Fig. 3).
These amorphous silicon layers 10 and 11 can be grown placing on the wafer of reactor by low-pressure chemical vapor phase deposition (LP-CVD).By feeding 1800 to the monosilane gas of 2000cc/min, forming diameter through 30 to 120 seconds (preferably 60 seconds) on wafer under 520 ℃ to 540 ℃ (preferably 530 ℃), 5 to 40Pa (preferably 25Pa) is that the silicon wafer of about 2nm is examined.In deposit, relatively low pressure is examined very important for being isolated on the substrate 1 with the silicon wafer of specific density growth.Used gas is not limited to monosilane gas, also can be b silane gas.
Then, when wafer still places reactor, deposit air pressure is risen to 80 to 120Pa (preferably 90Pa), with the growth silicon fiml.In deposit, relatively high pressure is very important for deposition of amorphous silicon.
When deposition of amorphous silicon, by feeding PH
3Gas carries out the doping of phosphorus simultaneously.Earlier with PH
3The flow rate regulation of gas is 47 to 48cc/min, to form desirable low phosphorus concentration (1 * 10
20Atom/cm
3) amorphous silicon layer.Then with PH
3The flow rate regulation of gas is 180 to 190cc/min, to form desirable high phosphorus concentration (2 * 10
20To 6 * 10
20Atom/cm
3) amorphous silicon layer.
In the present embodiment, do not feed PH in the nucleating process
3Gas still, also can feed PH in the nucleating process
3Gas.In addition, used gas is monosilane gas among this embodiment, still, is not limited to monosilane gas, also can be b silane gas.
Make amorphous silicon layer 10 and 11 planarizations by dark etching or chemico-mechanical polishing (CMP), only keep embolism part (among Fig. 4).Make the amorphous silicon crystallization by 700 ℃ to 850 ℃ heat treatment in nitrogen atmosphere, so that amorphous silicon activated by electricity, to form polysilicon plug 12 (among Fig. 5).The contact embolism of Zhi Zaoing just has satisfied low contact resistance thus.
The purpose that forms nucleus is for the set-point of crystal grain solid state growth is provided.Nucleus serves as the seed crystal that makes down amorphous silicon and last amorphous silicon crystallization in solid state growth by subsequent heat treatment.
In addition, the inventor finds that the solid state growth speed of crystal changes according to the difference of impurity concentration in the amorphous silicon, and higher impurity concentration has solid state growth speed faster.
And the inventor finds that this phenomenon can be used to reduce to combine lightly doped amorphous silicon layer down and the heavily doped apparent density that goes up the nucleus of amorphous silicon layer.Nucleus can make each grain growth for bigger size than low bulk density, and can not influence each other.
If heat-treat with crystallization of amorphous silicon under the situation that does not form nucleus, then crystal can be grown in different set-points simultaneously being higher than under the predetermined temperature beginning.This processing procedure just is difficult to control the density of crystal grain thus, is difficult to grow bigger crystal grain.If same problem also can take place in deposit light dope amorphous silicon and heavily doped amorphous silicon under the situation that does not form nucleus.Thus, nucleus not only provides the set-point of solid state growth, has also determined the position of these set-points.Should be noted that effect of the present invention only could realize under with the situation of grown crystal forming nucleus, lightly doped amorphous silicon layer, heavily doped amorphous silicon layer and heat treatment with specific order.
In order to confirm above-mentioned discovery, in the contact hole that forms nucleus and do not forming in the contact hole of nucleus and form the lightly doped contact embolism of amorphous silicon layer down that comprises different-thickness.The diameter of contact hole is 90nm.Fig. 6 shows the result who forms nucleus (solid line) and do not form nucleus (two dot dot dash) situation.
With impurity concentration is 1 * 10
20Atom/cm
3Lightly doped down amorphous silicon layer and impurity concentration be 2 * 10
20Atom/cm
3The heavily doped amorphous silicon layer filling contact hole of going up.Lower floor thickness be that A is to the F level.Under 850 ℃, amorphous silicon is heat-treated to form polysilicon plug.The resistance of measuring embolism is with the thickness of evaluation lower floor and the relation between the resistance.
The lightly doped thickness of amorphous silicon layer down under the A level is 0nm, and the thickness under the B level is 3nm, and the thickness under the C level is 5nm, and the thickness under the D level is 10nm, and the thickness under the E level is 20nm, and the thickness under the F level is 30nm.
In Fig. 6, solid line has represented to form the resistance of nucleus, and two dot dot dash represent not form the resistance of nucleus.Under the situation that has formed nucleus, the contact resistance of (the lightly doped thickness of amorphous silicon layer down is 0nm) the contact embolism (solid line is represented) under the A level is about 900 Ω, the contact resistance of (the lightly doped thickness of amorphous silicon layer down is 3nm) under the B level is about 550 Ω, the contact resistance of (the lightly doped thickness of amorphous silicon layer down is 5nm) under the C level is about 570 Ω, the contact resistance of (the lightly doped thickness of amorphous silicon layer down is 10nm) under the D level is about 600 Ω, the contact resistance of (the lightly doped thickness of amorphous silicon layer down is 20nm) under the E level is about 700 Ω, and the contact resistance of (the lightly doped thickness of amorphous silicon layer down is 30nm) under the F level is about 820 Ω.
On the other hand, the contact resistance that does not form the contact embolism (two dot dot dash are represented) of nucleus in the prior art is about 1200 to 1500 Ω.According to these results, the present invention has the contact embolism of nucleus than the contact embolism that does not have nucleus, resistance low 20% to 50%.In addition, in the embodiment of the inventor's embolism with nucleus, the embolism that is formed by heavily doped amorphous silicon (under the A level) has demonstrated the highest resistance fully, although expect that owing to impurity concentration in whole embolism is very high this embolism demonstrates minimum resistance.
And because thicker lightly-doped layer may make that the impurity concentration in the limited embolism volume is lower, the resistance that therefore contacts embolism is along with the thickness of light dope lower floor increases and increases.The impurity concentration of contact embolism is by reducing under A to the F level, although the embolism that has under the A level of high impurity concentration has the highest resistance.
These results are discussed below.Fig. 7 A and 7B are the schematic diagram of scanning electron microscopy (SEM) photo of the polysilicon plug that obtains.These schematic diagrames show, contain the embolism (among Fig. 7 B) of the following amorphous silicon layer of any level, than the embolism that only contains heavily doped amorphous silicon layer (among Fig. 7 A), grow bigger crystal grain.
That is to say that behind the formation nucleus, in by the heat treatment crystallization process, lightly doped amorphous silicon layer down and heavily doped combination of going up amorphous silicon layer than single heavily doped amorphous silicon layer, grow bigger crystal grain.As a result, the density of grain boundary reduces, and makes to allow more electric current to pass through, and has improved resistance.
Below, with reference to Fig. 8 A and 8B this mechanism is described.Fig. 8 A is the curve chart of single heavily doped amorphous silicon layer, and Fig. 8 B combines lightly doped amorphous silicon layer down and the heavily doped curve chart of going up amorphous silicon layer.
In Fig. 8 A, go out crystal grain at the crystallization initial stage of causing by nucleus growth by heat treatment, filled up fully by crystal grain until contact hole.When contact hole was filled up fully, the growth of crystal stopped.Crystal grain group growth rate and size with statistical distribution (variation) in embolism grown.On an average, the crystal growth of heavily doped amorphous silicon is very fast, so contact hole is very fast is filled up fully.Correspondingly, although the granularity difference, less relatively crystal grain has occupied the most of space in the contact hole.
For the combination of following amorphous silicon layer and last amorphous silicon layer, among Fig. 8 B, by heat treatment, at the crystallization initial stage, crystal grain begins by the nucleus growth in the lightly doped amorphous silicon layer down.Because the statistical variations of crystal growth rate, some crystal grain of crystallization at first arrives the interface with heavily doped amorphous silicon layer in the lightly doped amorphous silicon layer.Lightly doped down amorphous silicon layer is with the low rate crystallization, and the border that is used for enlarging the crystal of growing in the solid phase mode thus arrives the temporal deviation of heavily doped layer.
The grain boundary that arrives heavily doped layer makes the solid state growth rate sharply raise, and the heavily doped amorphous silicon around making is crystallization immediately, and continues crystallization light dope amorphous silicon.The crystal grain that has arrived heavily doped amorphous silicon layer has suppressed the growth of crystal grain thereafter.Thus, these repressed crystal grain keep very little.
Heavily doped amorphous silicon continues crystallization and is grown to big crystal grain in the part that early arrives by grown crystal.As a result, formed the big crystal grain of minority and occupied most of space of contact hole.These megacrysts help conductivity, have reduced the resistance of contact embolism.
Correspondingly, lightly doped down amorphous silicon layer and heavily doped go up the thickness of amorphous silicon layer and size that impurity concentration should depend on contact hole and should pay the utmost attention to reduce resistance and still pay the utmost attention to and suppress impurity and diffuse into substrate by embolism.
Reduce resistance if pay the utmost attention to, then the thickness of light dope lower floor can be 3 to 5nm.If thickness is lower than 3nm, then crystal grain can arrive the heavy doping upper strata immediately, can't realize desirable effect thus.On the other hand, going into substrate if pay the utmost attention to the inhibition diffusion of impurities, then for example is the contact hole of 90nm for diameter, and the thickness of light dope lower floor can be 20 to 30nm.If thickness is less than 45nm, then contact hole can only be filled up by lightly-doped layer fully.As a result, resistance increases, and can't realize desirable effect thus.
According to this embodiment, form nucleus after, lightly doped amorphous silicon layer down of deposit and the heavily doped amorphous silicon layer of going up, and allow by heat treatment its crystal of growing.This method can be made big crystal grain so that the embolism of the contact with low contact resistance to be provided.
These technological processes can repeat twice or more times is to make the contact bolt plug structure of sandwich construction.
If can after forming nucleus, grow amorphous silicon, in the present invention, amorphous silicon even can be partially-crystallized by thermal history in deposition process before annealing then.If the amorphous silicon that has crystal block section and amorphous fraction concurrently is carried out the processing of for example dark etching and CMP, then crystal block section can carry out etching with unconventional two-forty.This etching meeting causes unusual structure, for example unusual embolism loss.
In order to address these problems, can by form lightly doped amorphous silicon layer (ground floor) down in the contact hole that reduces at thickness, in the contact hole that thickness reduces, form heavily doped on amorphous silicon layer (second layer) and on the second layer, form the 3rd lightly doped amorphous silicon layer that thickness equals ground floor and second layer thickness decrease, a kind of three-decker is provided.Preferably the 3rd amorphous silicon layer impurity concentration is 1 * 10
19To 1 * 10
20Atom/cm
3, and preferably pass through the LP-CVD deposit with first and second amorphous silicon layers.
Even crystal is grown before annealing, but its growth can slow down at the 3rd lightly doped amorphous silicon layer, to remain near the grown crystal of second heavily doped layer.The 3rd layer of anomalous structure that can suppress in the processing procedure thus.Yet if whole amorphous silicon is annealed before the processing of carrying out such as dark etching and CMP and crystallization, special requirement are the 3rd layer.
Second embodiment
Now the second embodiment of the present invention will be described.Below, with reference to the main technique flow process of Fig. 9 to 15 explanation according to the method for present embodiment manufacturing semiconductor device.Represent with same Reference numeral with components identical among first embodiment.
With reference to Fig. 9, deposit gate insulating film 2, polysilicon film 3, metal silicide film 4 and insulation mask 5 form gate electrode by photoetching and etching on Semiconductor substrate 1.Then, deposit side wall insulating film 6, and form diffusion layer region 7.With reference to Figure 10, cover these elements with lightly doped amorphous silicon layer 21 down and the heavily doped amorphous silicon layer 22 of going up, the described phosphorus concentration of amorphous silicon layer 21 down is 1 * 10
20Atom/cm
3, and thickness is 3 to 30nm, the described phosphorus concentration of going up amorphous silicon layer 22 is 2 * 10
20To 6 * 10
20Atom/cm
3, and thickness is 100nm or thicker.
These amorphous silicon layers 21 and 22 can be grown placing on the wafer of reactor by LP-CVD.By feeding 1800 to the monosilane gas of 2000cc/min, forming particle diameter through 30 to 120 seconds (preferably 60 seconds) on wafer under 520 ℃ to 540 ℃, 5 to 40Pa (preferably 25Pa) is that the silicon wafer of about 2nm is examined.In deposit, relatively low pressure for isolation liner at the bottom of on 1 the silicon wafer nuclear with the specific density growth very important.
When wafer still places reactor, deposit air pressure is risen to 80 to 120Pa (preferably 90Pa) with the growth silicon fiml then.The air pressure that increases deposit is very important for deposition of amorphous silicon.
When deposition of amorphous silicon, by feeding PH
3Gas carries out the doping of phosphorus simultaneously.Earlier with PH
3The flow rate regulation of gas is 47 to 48cc/min to form desirable low phosphorus concentration (1 * 10
20Atom/cm
3) amorphous silicon layer.Then with PH
3The flow rate regulation of gas is 180 to 190cc/min to form desirable high phosphorus concentration (2 * 10
20To 6 * 10
20Atom/cm
3) amorphous silicon layer.
In the present embodiment, do not feed PH in the nucleating process
3Gas still, also is to feed PH in the nucleating process
3Gas.In addition, used gas is monosilane gas among this embodiment, still, is not limited to monosilane gas, also can be b silane gas.
Then, deposit insulation mask 23 (Figure 11), and by resist, photoetching being provided and being etched with only at contact bolt plug portion reservation film 23 (Figure 12).Use the insulation mask 23 that keeps as mask then, the amorphous silicon layer 21 of etch-gate dielectric film 2 tops and 22 part, with reservation embolism part (Figure 13), and deposit interlayer dielectric 24 (Figure 14).
Make interlayer dielectric 24 planarizations by dark etching or CMP, to expose the top surface of heavily doped amorphous silicon layer 22.Make the amorphous silicon crystallization by 700 ℃ to 850 ℃ heat treatment in nitrogen atmosphere, so that amorphous silicon is activated to form polysilicon plug 25 (among Figure 15) by electricity.The contact embolism wiring of making thus just has satisfied low contact resistance.
Used mask is an insulation mask 23 in the present embodiment, but is not limited to dielectric film, also can use Etching mask.In addition, can provide a kind of three-decker by forming lightly doped amorphous silicon layer 21 (ground floor), formation heavily doped amorphous silicon layer 22 (second layer) and on the second layer, forming than the 3rd lighter amorphous silicon layer of second layer doping.
According to present embodiment, after forming nucleus, lightly doped amorphous silicon layer 21 down of deposit and the heavily doped amorphous silicon layer 22 of going up, and allow by heat treatment its crystal of growing.This method can be made big crystal grain so that the embolism of the contact with low contact resistance to be provided.
The 3rd embodiment
Now, with reference to Figure 16 to 18 explanation third embodiment of the present invention.In the 3rd embodiment, adopt according to the method for the foregoing description and make gate electrode and wiring.
With reference to Figure 16, deposit gate insulating film 33, lightly doped amorphous silicon layer 34, heavily doped amorphous silicon layer 35, metal silicide film 36 and insulation mask 37 on Semiconductor substrate 31 with insulation area of isolation 32.
The phosphorus concentration of lightly doped amorphous silicon layer 34 is 1 * 10
20Atom/cm
3, thickness is 5 to 10nm.The phosphorus concentration of heavily doped amorphous silicon layer 35 is 2 * 10
20To 6 * 10
20Atom/cm
3, thickness is 60 to 100nm or thicker.
These amorphous silicon layers 34 and 35 can be grown placing on the wafer of reactor by LP-CVD.By feeding 1800, form silicon wafer nuclear down in 530 ℃, 25Pa to the monosilane gas of 2000cc/min.Then deposit air pressure is risen to 90Pa.When deposition of amorphous silicon, by feeding PH
3Gas carries out the doping of phosphorus simultaneously.Earlier with PH
3The flow rate regulation of gas is 47 to 48cc/min to form desirable low phosphorus concentration (1 * 10
20Atom/cm
3) amorphous silicon layer.Then with PH
3The flow rate regulation of gas is 180 to 190cc/min to form desirable high phosphorus concentration (2 * 10
20To 6 * 10
20Atom/cm
3) amorphous silicon layer.
By sputter, deposit WN film and W gate electrode film are as metal silicide layer 36 on amorphous silicon layer 35.Between metal film and amorphous silicon layer 35, can form tungsten silicide layer to improve cementability therebetween.Deposit insulation mask 37 and resist on metal silicide layer 36, and by photoetching and etching formation gate electrode part 38 and wiring portion 39 (among Figure 17).Form side wall insulating film 40 and diffusion layer 41 (among Figure 18).Make the amorphous silicon crystallization by the heat treatment in 700 ℃ to 850 ℃, nitrogen atmosphere, so that the activation of amorphous silicon electricity.
In the present embodiment, do not feed PH in the nucleating process
3Gas still, also is to feed PH in the nucleating process
3Gas.In addition, used gas is monosilane gas in the present embodiment, still, is not limited to monosilane gas, also can be b silane gas.
Gate electrode of Zhi Zaoing and wiring just have satisfied low contact resistance thus.According to present embodiment, lightly doped amorphous silicon layer 34 of deposit and heavily doped amorphous silicon layer 35, and make its crystallization by heat treatment.This combination can be made bigger crystal grain than single heavily doped amorphous silicon layer, has more low-resistance wire structures to provide.
Below, the foregoing description is summarized.Lightly doped amorphous silicon layer of deposit and heavily doped amorphous silicon layer after forming nucleus.The heavily doped amorphous silicon layer that this sandwich construction is more single can produce bigger crystal grain and have more low-resistance polysilicon structure to provide in the process that makes recrystallized amorphous silicon by heat treatment.Lightly doped amorphous silicon layer down and the heavily doped amorphous silicon layer of going up preferably have 1 * 10
20Atom/cm
3Or bigger impurity concentration difference, and amorphous silicon layer preferably has lower impurity concentration down.The lightly doped preferred impurity concentration of amorphous silicon layer down is 1 * 10
19To 1 * 10
20Atom/cm
3, and the heavily doped upward preferred impurity concentration of amorphous silicon layer is 2 * 10
20To 6 * 10
20Atom/cm
3, to obtain lower resistance.By in the heat treated crystal growing process, under the difference help of descending between the higher crystal growth rate of lower crystal growth rate of amorphous silicon layer and last amorphous silicon layer, can form big crystal grain.The heat treatment that is used for crystallization is preferably carried out under 600 ℃ to 850 ℃ low temperature.If heat treatment is being carried out under up to 1000 ℃ high temperature above 850 ℃, then this processing is preferably being carried out to reduce heat load in the short time.Heat treatment is preferably carried out in inert gas atmosphere, more preferably carries out in nitrogen atmosphere.
According to this application, after forming nucleus, lightly doped amorphous silicon layer of deposit and heavily doped amorphous silicon layer.The heavily doped amorphous silicon layer that this sandwich construction is more single can be made big crystal grain and have more low-resistance polysilicon structure to provide in the process that makes recrystallized amorphous silicon by heat treatment.Thus according to should with manufacture method the semiconductor integrated circuit of the superior performance with lower power consumption and higher speed of service can be provided by the resistance that reduces embolism wiring.
By the foregoing description, understood the present invention specifically, but the invention is not restricted to these embodiment.Certainly, allow to carry out various modifications within the scope of the invention.
Claims (20)
1. a method of making semiconductor device comprises the following steps:
On substrate, form silicon wafer nuclear;
Deposit first amorphous silicon;
Deposit second amorphous silicon; And
By being grown in the solid phase mode, nucleus makes first amorphous silicon and the second amorphous silicon crystallization.
2. according to the method for the manufacturing semiconductor device of claim 1, wherein, regulate the solid state growth speed of crystal in second amorphous silicon, make it be higher than the solid state growth speed of crystal in first amorphous silicon.
3. according to the method for the manufacturing semiconductor device of claim 1, wherein, regulate the impurity concentration of second amorphous silicon, make it be higher than the impurity concentration of first amorphous silicon.
4. according to the method for the manufacturing semiconductor device of claim 3, wherein,
The impurity concentration of first amorphous silicon is 1 * 10
19To 1 * 10
20Atom/cm
3And
The impurity concentration of second amorphous silicon is 2 * 10
20To 6 * 10
20Atom/cm
3
5. according to the method for the manufacturing semiconductor device of claim 1, wherein, step, the step of deposit first amorphous silicon and the step of deposit second amorphous silicon of described formation silicon wafer nuclear are carried out in same reative cell continuously by low-pressure chemical vapor phase deposition (LP-CVD).
6. according to the method for the manufacturing semiconductor device of claim 5, wherein, the step of described formation silicon wafer nuclear is carried out in 520 ℃ to 540 ℃ and 25Pa or the lower gas system that mainly contains silane gas or b silane gas by LP-CVD.
7. according to the method for the manufacturing semiconductor device of claim 5, wherein, the step of the step of described deposit first amorphous silicon and deposit second amorphous silicon is carried out in 520 ℃ to 540 ℃ and 90Pa or the higher gas system that mainly contains silane gas or b silane gas by LP-CVD.
8. according to the method for the manufacturing semiconductor device of claim 1, wherein the thickness of first amorphous silicon is 3 to 30nm.
9. according to the method for the manufacturing semiconductor device of claim 1, wherein, carry out the step of crystallization first amorphous silicon and second amorphous silicon by 600 ℃ to 850 ℃ heat treatments.
10. according to the method for the manufacturing semiconductor device of claim 9, wherein in nitrogen atmosphere, carry out described heat treatment.
11., wherein, fill contact hole on the substrate with silicon wafer nuclear, first amorphous silicon and second amorphous silicon, to form the contact embolism according to the method for the manufacturing semiconductor device of claim 1.
12. according to the method for the manufacturing semiconductor device of claim 1, wherein,
Deposit silicon nucleus, first amorphous silicon and second amorphous silicon on the required contact zone of substrate;
Etching first amorphous silicon and second amorphous silicon keep its part on the contact zone; And
With dielectric film filling other zone except the contact zone.
13. method according to the manufacturing semiconductor device of claim 1, further comprise step: deposit the 3rd amorphous silicon on first and second amorphous silicons, then by making nucleus grow crystallization first amorphous silicon, second amorphous silicon and the 3rd amorphous silicon in the solid phase mode.
14. according to the method for the manufacturing semiconductor device of claim 13, wherein, regulate the solid state growth speed of crystal in the 3rd amorphous silicon, make it be lower than crystal solid state growth speed in second amorphous silicon.
15. according to the method for the manufacturing semiconductor device of claim 13, wherein, regulate the impurity concentration of the 3rd amorphous silicon, make it be lower than the impurity concentration of second amorphous silicon.
16. method according to the manufacturing semiconductor device of claim 13, wherein, step, the step of deposit first amorphous silicon, the step of deposit second amorphous silicon and the step of deposit the 3rd amorphous silicon of described formation silicon wafer nuclear are carried out in same reative cell continuously by LP-CVD.
17. according to the method for the manufacturing semiconductor device of claim 16, wherein, the step of described formation the 3rd amorphous silicon is carried out in 520 ℃ to 540 ℃ and 90Pa or the higher gas system that mainly contains silane gas or b silane gas by LP-CVD.
18., wherein, utilize that first and second amorphous silicons of deposit form gate electrode or wiring on substrate according to the method for the manufacturing semiconductor device of claim 1.
19. semiconductor device by making according to the method for claim 1.
20. semiconductor device by making according to the method for claim 11.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004149647A JP3872071B2 (en) | 2004-05-19 | 2004-05-19 | Semiconductor device and manufacturing method thereof |
| JP2004149647 | 2004-05-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1700415A true CN1700415A (en) | 2005-11-23 |
Family
ID=35375759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005100739635A Pending CN1700415A (en) | 2004-05-19 | 2005-05-19 | Semiconductor device and method for producing the same |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7351654B2 (en) |
| JP (1) | JP3872071B2 (en) |
| KR (1) | KR100702882B1 (en) |
| CN (1) | CN1700415A (en) |
| TW (1) | TWI261916B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009082840A1 (en) * | 2007-12-27 | 2009-07-09 | Applied Materials, Inc. | Method for forming a polysilicon film |
| CN101409232B (en) * | 2007-10-12 | 2012-04-25 | 东京毅力科创株式会社 | Method for forming polysilicon film |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7297983B2 (en) | 2005-12-29 | 2007-11-20 | Infineon Technologies Ag | Method for fabricating an integrated circuit on a semiconductor substrate |
| JP5034332B2 (en) * | 2006-06-14 | 2012-09-26 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| JP4249765B2 (en) * | 2006-07-05 | 2009-04-08 | エルピーダメモリ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2008244093A (en) * | 2007-03-27 | 2008-10-09 | Elpida Memory Inc | Method for manufacturing semiconductor device |
| JP5023004B2 (en) * | 2008-06-30 | 2012-09-12 | 株式会社日立国際電気 | Substrate processing method and substrate processing apparatus |
| US9583187B2 (en) * | 2015-03-28 | 2017-02-28 | Intel Corporation | Multistage set procedure for phase change memory |
| US10483102B2 (en) * | 2017-04-07 | 2019-11-19 | Applied Materials, Inc. | Surface modification to improve amorphous silicon gapfill |
| KR102525163B1 (en) | 2018-05-15 | 2023-04-24 | 삼성전자주식회사 | Integrated circuit device |
| KR102179167B1 (en) * | 2018-11-13 | 2020-11-16 | 삼성전자주식회사 | Semiconductor package |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2891A (en) * | 1842-12-21 | Mode of fastening door lock and latch knobs to their spindles | ||
| JPS63292617A (en) | 1987-05-26 | 1988-11-29 | Nec Corp | Manufacture of soi substrate |
| JP2708559B2 (en) | 1989-08-10 | 1998-02-04 | キヤノン株式会社 | Method for forming crystalline semiconductor film |
| JPH0680638B2 (en) | 1990-07-05 | 1994-10-12 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPH05109617A (en) | 1991-10-17 | 1993-04-30 | Nec Corp | Formation method of polycrystalline silicon film |
| JP3187364B2 (en) * | 1998-02-19 | 2001-07-11 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH11297852A (en) | 1998-04-14 | 1999-10-29 | Sony Corp | Semiconductor device and manufacture thereof |
| US6046083A (en) * | 1998-06-26 | 2000-04-04 | Vanguard International Semiconductor Corporation | Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications |
| JP3362839B2 (en) * | 1998-12-24 | 2003-01-07 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US6566181B2 (en) * | 1999-02-26 | 2003-05-20 | Agere Systems Inc. | Process for the fabrication of dual gate structures for CMOS devices |
-
2004
- 2004-05-19 JP JP2004149647A patent/JP3872071B2/en not_active Expired - Fee Related
-
2005
- 2005-05-18 KR KR1020050041649A patent/KR100702882B1/en not_active IP Right Cessation
- 2005-05-19 TW TW094116272A patent/TWI261916B/en not_active IP Right Cessation
- 2005-05-19 US US11/132,258 patent/US7351654B2/en not_active Expired - Fee Related
- 2005-05-19 CN CNA2005100739635A patent/CN1700415A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409232B (en) * | 2007-10-12 | 2012-04-25 | 东京毅力科创株式会社 | Method for forming polysilicon film |
| WO2009082840A1 (en) * | 2007-12-27 | 2009-07-09 | Applied Materials, Inc. | Method for forming a polysilicon film |
Also Published As
| Publication number | Publication date |
|---|---|
| US7351654B2 (en) | 2008-04-01 |
| TWI261916B (en) | 2006-09-11 |
| KR20060048000A (en) | 2006-05-18 |
| TW200603388A (en) | 2006-01-16 |
| JP3872071B2 (en) | 2007-01-24 |
| KR100702882B1 (en) | 2007-04-04 |
| JP2005332960A (en) | 2005-12-02 |
| US20050260862A1 (en) | 2005-11-24 |
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