GB2306816A - CMOS exclusive OR circuit - Google Patents

Abstract

A CMOS exclusive OR circuit comprises a pair of cross-coupled PMOS pass transistors 30,40 in combination with a pair of NMOS transistors 10,20 connected in series to the negative supply rail. When one input is high and the other low, the input signal that is high passes through one of the PMOS pass transistors to the node Q. When both inputs are high, the node Q is brought to a low level by the transistors 10 and 20. When both inputs are low the PMOS transistors are turned on but the voltage at node Q remains a threshold voltage above the negative rail. The inverters 50 provide a full logic swing output and enhance the fan-out.

Description

EXCLUSIVE OR CIRCUIT The present invention relates to an exclusive OR circuit having a high efficiency.

Generally, a low power exclusive OR circuit (referred to hereinafter as XOR circuit) has variously been used in application specific integrated circuits (ASICs) and other fields. In this connection, the XOR circuit must perform an XOR operation perfectly according to an input state, under the condition that the current consumption amount is small. In practice, when an XOR circuit satisfies conditions, such as a low power consumption, a high-speed operation, or a small number of components, it has a more efficient characteristic.

Fig. 1 of the accompanying drawings is a circuit diagram illustrating the construction of a previously proposed two-input XOR circuit. As shown in this drawing, the previously proposed XOR circuit includes at least eight MOS transistors and four inverters.

The XOR circuit in Fig. 1 has the disadvantage that there is a large number of components, although they are smaller in number than those in XOR circuits which were proposed even earlier.

XOR circuits are required in various fields such as a full adder, and a comparator. Also, an XOR circuit needs a large area and consumes a large amount of current as input bits are increased in number. For these reasons, an XOR circuit is required to have reliability in operation, to operate at high-speed, to have a low power consumption and to occupy a small area.

A feature of an XOR circuit to be described below by way of example in illustration of the invention is that it has a small number of transistors and a low consumption of power.

In an illustrative embodiment of the present invention to be described below, by way of example, an exclusive OR circuit includes an output terminal for outputting an exclusive ORed value of data input at first and second input terminals, first and second transistors connected in series between the output terminal and a ground voltage terminal, the first transistor having a gate for inputting data at the first input terminal, the second transistor having a gate for inputting data at the second input terminal, a third transistor connected between the first input terminal and the output terminal, the third transistor having a gate for inputting data at the second input terminal, a fourth transistor connected between the second input terminal and the output terminal, the fourth transistor having a gate for inputting data at the first input terminal.

An embodiment, illustrative of the invention will now be described, by way of example, with reference to Fig. 2 of the accompanying drawings which is a circuit diagram of a two-input XOR circuit.

The characteristics of an XOR circuit illustrative of the present invention will first be described briefly.

In the arrangement to be described the need for inverted values at the input terminals of an XOR circuit are removed. That is, whereas in the previously proposed XOR circuit a perfect operation could only be performed when there was a complement /A of an input A and a complement /B of an input B. However, in the arrangement to be described below, the XOR circuit does not require complement values of input data. Therefore, the effect is that any unnecessary area and current consumption of the XOR circuit is minimised.

Secondly, an XOR circuit should have a drive capability. Namely, an XOR circuit must be able to drive a subsequent stage which is connected to it.

Thirdly, an XOR circuit should have a small number of transistors and perform an XOR operation reliably and at a low voltage level.

Fourthly, an XOR circuit should have a comparatively small power consumption.

Referring to Fig. 2, an XOR circuit is shown which includes first and second NMOS transistors 10 and 20, first and second PMOS transistors 30 and 40, and a buffer 50.

The first and second NMOS transistors 10 and 20 are connected in series between an output terminal Q and a ground voltage terminal. The first NMOS transistor 10 has a gate for inputting data A from a first input terminal and the second NMOS transistor 20 has a gate for inputting data B from a second input terminal.

The first and second PMOS transistors 30 and 40 are connected in a cross-coupled manner between the first and second input terminals and an output terminal Q. The first PMOS transistor 30 has its gate connected to one terminal of the second PMOS transistor 40 which is also connected to the second input terminal, and the second PMOS transistor 40 has its gate connected to one terminal of the first PMOS transistor 30 which is also connected to the first input terminal. The first and second PMOS transistors 30 and 40 have their other terminals connected in common to the output terminal Q. Namely, the PMOS transistor 30 is connected between the first input terminal and the output terminal Q and inputs data B from the second input terminal at its gate.The second PMOS transistor 40 is connected between the second input terminal and the output terminal Q and inputs data A from the first input terminal at its gate.

The buffer 50 performs a full swing operation with respect to a signal voltage from the output terminal Q and transfers the resultant signal voltage to a final output terminal OUT. To this end, the buffer 50 is provided with two inverters connected in series to the output terminal Q.

As mentioned above, in the particular embodiment being described, the XOR circuit is simply provided with the four transistors 10-40 and the buffer 50.

The operation of the XOR circuit with the above mentioned construction will now be described in detail.

When the input data A and B are both at a logical high, the series first and second NMOS transistors 10 and 20 are both turned on, thereby causing the signal at the output terminal Q to go to a logical low. To the contrary, in the case in which the input data A and B are both at a logical low, the parallel first and second PMOS transistors 30 and 40 are both turned on. As a result, the input low values are directly transferred to the output terminal Q.

On the other hand, in the case in which the input data A and B have opposite logic values, any one of the series first and second NMOS transistors 10 and 20 is turned off to prevent the signal at the output terminal Q from going to a logical low. Also, in this case, any one of the parallel first and second PMOS transistors 30 and 40 is turned on to allow the signal at the output terminal Q to go to a logical high.

In the case in which the input data A and B are both at a logical high, or only one of them is at a logical high, namely, A = 1 and B = 0, A = 0 and B = 1, or A = 1 and B = 1, no problem is caused. However, when both the input data A and B are at a logical low, namely, A = 0 and B = 0, a voltage corresponding to Vtp (threshold voltage of PMOS transistor) remains at the output terminal Q. In order to compensate for such a voltage, the buffer 50 is connected to the output terminal Q to allow the signal at the final output terminal OUT to have a full swing voltage value. As a result, the XOR circuit is stable in operation and can enhance the capability of driving a device (not shown) connected to the final output terminal OUT.

As is apparent from the above, the XOR circuit described has a comparatively small number of transistors, resulting in a reduction in the amount of power consumed. Therefore, the XOR circuit described can perform an XOR operation according to the input state in a stable manner. Further, because the components are reduced in number, the device can be reduced in size and the data processing speed can be enhanced.

Although a preferred embodiment has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the protection sought by the appended claims.

Claims (8)

1. An exclusive OR circuit including an output terminal for outputting an exclusive ORed value of data at first and second input terminals, first and second transistors connected in series between the output terminal and a ground voltage terminal, the first transistor having a gate for inputting data at the first input terminal, the second transistor having a gate for inputting data at the second input terminal, a third transistor connected between the first input terminal and the output terminal, the third transistor having a gate for inputting data at the second input terminal, and a fourth transistor connected between the second input terminal and the output terminal, the fourth transistor having a gate for inputting data at the first input terminal.

2. An exclusive OR circuit as set forth in claim 1, further including a buffer connected to the output terminal, for performing a full swing operation with respect to a signal voltage from the output terminal and transferring the resultant signal voltage externally.

3. An exclusive OR circuit as set forth in claim 2, wherein the buffer includes a plurality of inverters connected in series to the output terminal.

4. An exclusive OR circuit as set forth in claim 1, wherein the first and second transistors are NMOS transistors.

5. An exclusive OR circuit as set forth in claim 4, wherein the third and fourth transistors are PMOS transistors.

6. An exclusive OR circuit as set forth in Claim 2, wherein the first and second transistors are NMOS transistors.

7. An exclusive OR circuit as set forth in claim 6, wherein the third and fourth transistors are PMOS transistors.

8. An exclusive OR circuit as claimed in claim 1 substantially as described herein with reference to Fig.

2 of the accompanying drawings.