GB2293899A

GB2293899A - Reference voltage generating circuit

Info

Publication number: GB2293899A
Application number: GB9524129A
Authority: GB
Inventors: Katsuji Kimura
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1992-02-05
Filing date: 1993-02-05
Publication date: 1996-04-10
Anticipated expiration: 2013-02-05
Also published as: GB9524129D0; GB2293899B

Abstract

A reference voltage generating circuit comprises two transistors Q1, Q2 of which the emitter size ratio is 1:K1 and the bases are commonly connected and which operate as a diode; a first current mirror circuit M1, M2 consisting of two P channel FET's whose capacity ratio is K2:1, and a second current mirror circuit M3, M4 consisting of two N channel FET's whose capacity ratio is K2:1. The FET's of equal capacities in the first and second current mirror circuits are connected to each other in series; the output ends of the FET's whose capacity is K2 being connected via a first resistor R1 to the emitter of that transistor of the two transistors whose emitter size is 1; the output ends of the FET's whose capacity is 1 being connected via a series circuit of second and third resistors R2, R3 to the emitter of that transistor of the two transistors whose emitter size is K1. The circuit may also include a third current mirror. <IMAGE>

Description

REFERENCE VOLTAGE GENE.SkTING CIRCUIT BACKGROUND OF THE INVENTION The present invention relates to a reference voltage generating circuit for use in the generation o a reference voltage in a constant-voltage circuit in C-MOS technolcgy.

As is well known to persons skilled in the art, the most commonly used reverence voltage generating circuit according to the prior art is a widlar band-gap reference circuit, but no reference voltage generating circuit solely consisting of MOS transistors is knows to be available for practical use. A paper on an N.OS reference voltage generating circuit utilizing the threshold voltage difference between an enhancement MOS transistor and a depletion MOS transistor was published (1978, ISSCC, No. WAL 3.5) , but its performance characteristics are not adequate for practical application either.

MOS transistors, however, have many advantages, and it is called for to develop a reference voltage generating circuit that can be realized on a CMOS integrated circuit.

Notably, such a circuit should be excellent in temperature performance, but, since MOS transistors are significantly uneven in manufactured state and, moreover, their temperature dependence is curvilinear unlike bipolar transistors whose temperature dependence is liar, how to control this characteristic possesses a major problem.

On the other hand, among reference voltage generating circuits consisting of MOS and bipolar transistors, what is illustrated in FIG. 8 is known, for instance. This reference voltage generating circuit is commonly known as a band-gap voltage reference circuit, and FIG. 8 illustrates an example realized by executing a CMOS process over an N type substrate with a view to large-scale integration.

Its configuration centers on an OP amplifier 31 and socalled parasitic transistors (Q1 and Q2). Its outline will be described below.

In FIG. 8, the base-emitter voltage VBE1 of Q1 is represented by equation (1), and the base-emitter voltage VBE2 of Q2, by equation (2). In equations (1) and (2), IS1 and IS2 are the saturation currents of Q1 and Q2, respectively, VT being equal to kT/q, where k is Boltzmann's constant, q, the charge of an electron and T, absolute temperature.

VBE1 = VT ln (11/151) .... (1) VBE2 = VT ln (I2/IS2) .... (2) From equations (1) and (2) are derived equation (3), which represents the difference voltage oVBE of the base-emitter voltages of Q1 and Q2.

#VBE = VBE1 - VBE2 = VT ln {(I1/I2) (IS2/IS1)}.... (3) Since Q1 and Q2 are equal here in emitter area, IS1 equals IS2- Therefore, the difference voltage #VBE is represented by equation (4).

AVBE = VT in (I1/I2) .... (4) Further, I2 = #VBE/R3. Therefore, the output reference voltage VREF can be obtained by equation (S).

VREF = (R1 + R3)I2 + VBE2 = (1 + R1/R3) #VBE + VBE2 = VBE1 + (R1/R3) #VBE .... (5) The temperature dependence of this output reference voltage VREF can be represented by equation (6) because the ratio R1/R3 is independent of temperature.

d VREF d VBE1 R1 d #VBE = + ( ) (6) dT dT + dT .... (6) The first term of the right side of this equation (6) is approximately -2 mV/deg. Because the ratio between I1 and 12 in equation (4) can be considered to be substantially constant and is logarithmically compressed, the temperature dependence of the difference voltage #VBE is represented by equation (7).

d#VBE/d T t + 0.085 mV/deg x ln (I1/I2) .... (7) Therefore, if (R1/R3)ln(I1/I2) is set to be 23.5, dVREF/dT will be approximately 0. If VBE1 is approximately 0.6 V here, VREF can be calculated to be approximately 1.211 V.

The above-described prior art reference voltage generating circuit illustrated in FIG. 8, on account of its use of an OP amplifier as the control element, involves the problems of a large circuit scale and a large drain current.

This application is divided from our co-pending UK application no.

9302329.9 (published as specification 2 264 573), the disclosure of which is incorporated herein by reference.

SUMMARY OF THE INVENTION An object of the present invention, therefore, is to provide a reference voltage generating circuit whose configuration is suitable for integration into a CMOS circuit.

Another object of the invention is to provide a reference voltage generating circuit of a new configuration combining MOS and bipolar transistors, which make it possible to reduce the circuit scale and the drain current.

According to the present invention, a reference voltage generating circuit comprises: a reference voltage generating circuit comprising two transistors of which the emitter size ratio is 1 :K, and the bases are commonly connected and which operate as a diode; a first current mirror circuit consisting of two P channel FET's whose capacity ratio is ?4:1, and a second current mirror circuit consisting of two N channel FET's whose capacity ratio is K2:1, wherein FET's of equal capacities in said first and second current mirror circuits are connected to each other in series; the output ends of the FET's whose capacity is K2 being connected via a first resistor to the emitter of that transistor of said two transistors whose emitter size ratio 1; the output ends of the FET's whose capacity is 1 being connected via a series circuit of second and third resistors to the emitter of that transistor of said two transistors whose emitter size ratio is Kt.

BRIEF DESCRIPTION OF DRAWINGS The above-mentioned and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, wherein: FIG. 1 is a diagram illustrating a reference voltage generating circuit; FIG. 2 is a diagram illustrating a second reference voltage generating circuit; FIG. 3 is a diagram illustrating a third reference voltage generating circuit FIG. 4 is a diagram illustrating a fourth reference voltage generating circuit; FIG. 5 is a temperature dependence diagram (SPICE simulation diagram) of the output reference voltage; FIGS. 6A, 68 and 6C are diagrams illustrating a reference voltage generating circuit according to a first embodiment of the present invention; ; FIG. 7 is a diagram illustrating a reference voltage generating circuit according to a second embodiment of the present invention; and FIG. 8 is a diagram illustrating a reference voltage generating circuit according to the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a reference voltage generating circuit basically consists of two n-channel NOS transistors (M1 and M2) provided on the grounding side and two p-channel MOS transistors (XH3 and M4) provided on the D.C. power source VDD side. Thus it has a CMOS configuration.

The M1:M2 capacity ratio (the ratio of gate width/ gate length) is l:Xl. The drain of M1 and the gate of M2 are commonly connected. Of M1, the source is directly grounded, the gate is connected to the source of M3 via a (first) resistor R1, and the gate is connected to the resistor R1 via a (second) resistor R2. Thus, the gate and the drain are connected to each other via the resistor R2, and the drain is connected to the source of .3 via a series circuit of the resistors R2 and R1. Of M2, the source is directly grounded, and the drain is connected to the source of M4.

Then, the M3:M4 capacity ratio is K2:l. Their drains are commonly connected to the D.C. power supply VDD, and their gates are commonly connected. The gate and source of M4 are directly-connected. In short, M3 and M4 constitute a current mirror circuit well known to those skilled in the art, and drives M1 and M2 in a current ratio of X2:1.

In FIG. 1, the resistor R1 can be dispensed with and, if it is, the gate of M1 will be directly connected to the source of M3. Therefore, the output terminal for the output voltage of the reference voltage generating circuit is provided at the connection end of the resistor R1 and the source of M3 (referred to as Vg-F in the drawing) or, in the absence of the resistor R1, at the connection end of the resistor R2 and the source of M3, i.e. the gate of M1 (referred to as VREF1 in the drawing) . In either the configuration of FIG. 1 or the configuration in which the resistor RI is absent, the output terminal can be provided at the gate of M2 (referred to as VREF2 in the drawing).

Further, the configuration of FIG. 1, in which the resistor R1 may be either absent or present, can be replaced by a configuration in which the resistor R2 is transferred to between the source of M2 and the ground, i.e., the gate and the drain of Ml are directly connected and the source of M2 is grounded via a (third) resistor R2 as illustrated in FIG. 2, wherein the resistor R1 is absent.

The output terminal can be provided at the middle point of a resistance pattern, which consists of the resistor R2, in the configuration of FIG. 1, in which the resistor R1 may be either absent or present. FIG. 3, for instance, shows a configuration in which the p-channel and the n-channel are interchanged. In this configuration, a resistor R2A and a resistor R2B have resulted from the bisecting of the resistor R2, and the output terminal is provided at the middle point between them (referred to as VREFr in the drawing).

Further, the configuration of FIG. 1, in which the resistor RI may be either absent or present, can be replaced by a configuration in which the drain of M2 is connected to the source of M4 via a (fourth) resistor, and the output terminal may be provided at the connection end of this fourth resistor and the source of M4. FIG. 4, for instance, shows a configuration in which the p-channel and the n-channel are interchanged. In this configuration, a resistor R2A and a resistor R2B have resulted from the bisecting of the resistor R2, and the output terminal is provided at the connection end of the (fourth) resistor R4 and the source of M4 (referred to as VREF4 in the drawing) The operation of the circuit will be described below with reference to FIG. 1.The difference voltage between the gate-source voltage VGSl of Ml and the gate-source voltage VGS2 of M2 being represented by VGS, the output reference voltage VREF can be represented by equation (8).

R1 VREF = VGS1 + #VGS .... (8) R2 The drain current I1 of M1 and the drain current I2 of M2 are determined by the capacity ratio between M3 and M4 (K2:l) constituting the current mirror circuit, Il being equal to K2I2. The drain current 11 of Ml is represented by equation (9) using the gate-source voltage VGSl, a threshold voltage VTHN and a transconductance ssN, and the drain current I2 of M2 is represented by equation (10) using a transconductance K1BN, the gate-source voltage VGS2 and the threshold voltage VTHN.The transconductance aN is represented by equation (11) using a mobility YN, a gate oxide film capacity per unit area cox, a gate width W and a gate length L.

I1 = ssN (VGS1 - VTHN)2 .... (9) I2 = K1 ssN (VGS2 - VTHN)2 ... (10) Cox W ssN = N # # ... (11) 2 L Therefore, the difference voltage aVGS can be represented by equation (12), which can. be rearranged into equation (13).

Since I1 is not 0 during operation, the drain current I1 can be eventually represented by equation (14).

If equations (9) and (14) are substituted into equation (8), the output reference voltage VREF can be represented by equation (15) .

It may be relevant here to consider the temperature dependence of the output reference voltage VREF. In the SPICE model, the conductance ssN is represented by equation (16) and the mobility N, by equation (17).

Incidentally, ssN0 and UNO in equations (9) and (10) indicate the values of ssN and pN, respectively, at T = To.

Therefore, 1/ssN is represented by equation (18), and the fractional temperature coefficient of 1/ssN at T0 = 3000K is 5,000 ppm/deg.

The threshold voltage VTHN, on the other hand, can be modelled into equation (19), in which t equals -4 mV/deg in the standard VTHN process or -2.7 mV/deg in the low VTHN process according to W.M. Penney and L. Lau, MOS Integrated Citcuits Theory, Design, and Systems Applications of MOS LSI (Van Nostrand Company) .

VTHN = VTHN0- α (T - TO) ... -(19) Now, if equations (18) and (19) are substituted into equation (15), the output reference voltage VREF Will be represented by equation (20), which can be differentiated with respect to the temperature T to give equation (21), and the fractional temperature coefficient of the output reference voltage VREF (TCF(VREF)) at the room temperature To of 300 K can be represented by equation (22), wherein VREFO is, the value of VREF at T = To - 300 K.

Therefore, in order that TCF(VREF) equal 0, equation (22) requires that equation (23) should hold.

{ 5,000 - TCF(R) } (VREFO - VTHNO) = α ... (23) If, for example, VTHN0 is 0.8V, d is 2.7 mV/deg and TCF(R) is 600 ppm/deg, the output reference voltage to make TCF(VREF) equal 0 will be represented by equation (24).

VREFO = 1.414 V ... (24) Then, supposing R1 to be 0, equation (14) will still hold. Whereas the output reference voltage is VREF1 in this case, equation (25) holds here because of equation (8), and this case is equal to equation (15) at R1 = 0.

If equations (18) and (19) are substituted into this equation (25), VREF1 will be represented by equation (26), and its temperature dependence, by equation (27). Thus equations (22) and (23) are applicable here, and a value indicated by equation (24) is obtained.

Further, if the reference voltage is to be taken out of the gate of M2, the output reference voltage will be VREF2, which is represented by equation (28).

VREF2 = VGS2

Comparison of this equation (28) with equation (25) reveals that equation (29) holds, and accordingly the output reference voltage VREF2 is represented by equation (30).

Because of this equation (30), TCF(VREF2) is smaller than 0 when fractional temperature coefficient TCF(VREFl) is 0. Similarly, when TCF(VREF1) is greater than 0, TCF(VREF2) can be set to he smaller than 0.

Therefore, if the intermediate voltage of the resistor R2 is the output reference voltage VREF3 (FIG. 3), TCF(VREF3) will equal 0, and TCF(VREF1) and TCF(VREF2) can be set respectively greater and smaller than 0, there being obtained a voltage whose temperature dependence is positive or negative or zero, provided that, when both K1 and K2 are greater than 1, VREF1 is greater than VREr3 and VREF3 is greater than VREF2.

Further, if the output terminal (of the output reference voltage of VREF4) is provided at the drain of M2 as shown in FIG. 4, the drain current I2 will be represented by equation (31), and the output reference voltage VRSF47 by equation (32).

VREF4 = VG54 + + R4 I2

Therefore, TCF(VREF4) can be set to be a for this output reference voltage VREF4 as well.

Now, FIG. 5 shows the result of SPICE simulation.

It is seen that the temperature dependence of the output reference voltage VREF is approximately 0 when VDO is above 2.5 V. It is supposed here: K1 = 1, K2 = 2, RI = 3RK , R2 = 4RH , TCF(R) = 600 ppm/deg, W/L - 50 Lim/ 5 pm, and the oxide film thickness tox = 280 angstroms.

As described above, the reference voltage generating circuit in which two MOS transistors difrering in capacity ratio, i.e. differing in gate-source voltage, are driven at different amperages, makes it possible for the temperature dependence of mobility and that of threshold voltage to cancel each other and the temcerature dependence of the output reference voltage can be thereby reduced.

Therefore, this has the benefit of providing a reference voltage generating circuit haring a suitable configuration for realization on 2 COS integrated circuit.

Next will be described a reference voltage generating circuit according to the present invention.

FIG. 6A illustrates a reference voltage generating circuit which is one embodiment of the present invention.

Although the same reference codes are used for transistors as in FIG. a, this does not man tat the same transistors are used. The same symbols are used for other elements as well for the convenience of description, but this does not mean that they are the same elements either. The same applies hereinafter.

This reference voltage generating circuit primarily consists of two PNP transistors (Q1 and Q2) and two current mirror circuits t(Ml and M2) and (M3 and M4).

The two transistors Q1 and Q2, whose emitter size ratio (Q1:Q2) is l:K1, have their bases commonly connected and the grounded via an analog ground VAG, their collectors being also grounded. Thus, these Q1 and Q2 are diodeconnected. The analog ground VAG may be dispensed with.

One (first) current mirror circuit consists of MOS transistors (M1 and M2), which are P channel FET's, and the capacity ratio (mirror ratio) between them (Ml:M2) is K2:l. The other (second) current mirror circuit consists of MOS transistors (M3 and M4), which are N channel FET's, and the capacity ratio (mirror ratio) between them (M3:M4) is K:1. These two current mirror circuits constitute a single current mirror circuit through the pairing of transistors equal in capacity (Ml and M3, and M2 and 4) in series connection.

In the illustrated example, one (first) current mirror circuit (M1 and M2) is arranged on the power source VDD side, and the other (second) current mirror circuit (M3 and M4), on the driving side. Thus in the second current mirror circuit (M3 and M4), the source of the transistor M31 whose capacity is K2, is connected to the emitter of the transistor QI, whose emitter size ratio is 1, via a (first) resistor RI, and the source of the transistor M4, whose capacity is 1, is connected to the emitter of the transistor Q2, whose emitter size ratio is K1, via a series circuit of a (second) resistor R2 and another (third) resistor R3.

In the above-described configuration, the current flowing through the resistor R1 being represented by I1, and that flowing through the resistors R2 and R3 by I2, 11 is equal to R2 x I2 because the mirror ratio of M1 and M2 of the first current mirror circuit is K:l. As the mirror ratio of M3 and M4 of the second current mirror circuit also is K2:t, the source voltage VREF of M4 and the source voltage VREF' of M3 are equal.

Here, the base-emitter voltage VBE1 of Q1 is represented by equation (33) , and the base-emitter voltage V3E2 of Q2, by equation (34), so that the differential voltage #VBE can be represented bv equation (35).

VBE1 = VT ln (K2 I2/IS) ... (33) VBE2 = VT ln I2/(K1 Is) ... (34) #VBE = VEE1 - VBE2 = VT ln (K1 K2) ... (35) Further, since VREF is dqual to VREF', I2 equals VBE/R3. Therefore, the output reference voltage VREF' can be represented by equation (36).

VREF = VBE2 + (1 + R2/R3) #VBE = VBE1 + (R2/R3) #VBE = VBE1 + (R1/R3) K2#VBE ... (36) The temperature dependence o tis output reference voltage VREF is represented by equation (37).

dVREF/dT = dVBE1/dT + (R2/R3) d #VBE/dT = dVBE1/dT + (R1/R3) K2 d #VBE/dT (37) In equation (37) here, dVBE1/dT is approximately 2 mV/deg, and d VBE/dT is 0.085 mv/deg. Therefore, if (R2/R3) ln(K1K2) = (R1/R3) K2 ln(K1K2) is set to be 23.5, dREF/dT will be approximately O. If the value of VBE1 is about 0.6 V at this time, VREF will be approximately 1.211 V. Thus, there is realized z reference voltage generating circuit having comparable performance characteristics to what is illustrated in FbG. 3.

FIG. 63 shows a reference voltage generating circuit, according to another embodiment of the present invention, in which 2 current mirror circuit composed of MOS transistors (M5 and M6) is added to improve the regulation efficiency. FIG. 6C shows a reference voltage generating circuit according to a further embodiment of the present invention in which the so-called cross-coupled trrnsistors (M5 and M6) are added to improve the regulation efficiency further, ccmpz-ed with the FIG. 63 circuit.

Next, FIG. 7 illustrates a reference voltage generating circuit, which is a second embodiment of the present invention. This circuit is 2 variation of the above-described first-embodiment illustrated in FIG. 6, a which the PNP transistors are replaced by NPN transistors, the P channel MOS transistors, by N channel MOS transistors, and the N channel MOS transistors, by P channel MOS transistors, and has comparable performance characteristics.

This reference voltage generating citcuit can be realized in any one of three ways. First, individual parts can be assembled into a circuit. As the circuit dimensions are small, if the circuit is to be used by itself, this option has its own advantages. Second, the circuit can be realized by a CMOS process. The configuration of FIG. 6 can be applied to a CMOS integrated circuit using a P substrate, while that of FIG. 7 can be applied to a CMOS integrated circuit using an N substrate.

In these cases, so-called parasitic transistors will be used as Ql and Q2, and the analog ground VAG, ir necessary, will be supplied from outside. A third option is the use of a Bi-CMOS process to form bipolar transistors and MOS transistors over the same substrate.

As described above, the reference voltage generating circuit according to the present invention, using no OP amplifier, is composed of two transistors differing in emitter size end operating as a diode, and a current mirror circuit consisting of two current mirror circuits separately driving the two transistors via resistors, each of te two current mirror circuits comprising two P (or N) channel FET's and FET's of equal capacities being paired in series connection.

Accordingly, it has the benefit of enabling bot th circuit size and the circuit current to be reduced.

To summarise, in the circuits shown in Figures 1 to 5, M1 and M2, because their capacity ratio is 1:K1, have different gate-source voltages. 3 and M4 , which constitute a current mirror cicuit, have a capacity ratio of K2:1. Thus, M1 and M2 are driven at a current ratio af K2:1. As a result.

the temperature dependence of mobility and that of threshold voltage can cancel each other to make it possible ta realize on a CMOS integrated circuit a reference voltage generating circuit with reduced temperature dependence. As the output reference voltage, VREF will be used if a resistor R1 is present, ar VRE- will be used if the resistor RI is dispensed with. The output may as well be taken out of the gate of M2 (VREF2), or out of the drain of M2, in which case the drain is provided with a resistor. In the preferred embodiments of the present invention shown in Figures 6 and 7 Q1 and Q2, which are PNP transistors, have an emittter size ratio (Q1:Q2) of 1:K1, and their bases are commonly connected and grounded via an analog ground VAC. their collectors being also grounded.Thus Q1 and A2 are diode-connected. P channel MOS transistors (M1 and M2) and N channel MOS transistors (M3 and M4) constitute a current mirror circuit each, and their mirror ratio (M1:M2 = M3:M4) is K2:1. In these two current mirror circuits, transistors equal in capacity (M1 and M3, and M2 and M4) are connected to each other n series. :ne source of M3 is connected to the emitter of Q1 via R1, and the source of M4 is connected to the emitter of A2 via a series circuit of R2 and R3. V and are e output reference voltages favourable in temperature dependence.

Each feature disclosed in this specification (which inciudes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

The text of the abstract filed herewith is hereby deemed to be repeated here in full as part of the specification.

Claims

1. A reference voltage generating circuit comprising two transistors of which the emitter size ratio is 1 :K1 and the bases are commonly connected and which operate as a diode; a first current mirror circuit consisting of two P channel FET's whose capacity ratio is K2:1, and a second current mirror circuit consisting of two N channel FET's whose capacity ratio is K2:l, wherein FET's of equal capacities in said first and second current mirror circuits are connected to each other in series; the output ends of the FET's whose capacity is K2 being connected via a first resistor to the emitter of that transistor of said two transistors whose emitter size ratio is 1; the output ends of the FET's whose capacity is 1 being connected via a series circuit of second and third resistors to the emitter of that transistor of said two transistors whose emitter size ratio is K,.

2. A reference voltage generating circuit as claimed in Claim 1, further comprising a third current mirror circuit consisting of third and fourth transistors, said third transistor being connected between the output ends of the FET's whose capacity is K2 and said first resistor, and said fourth transistor being connected between the output ends of the FET's whose capacity is 1 and said second resistor.

3. A reference voltage generating circuit as claimed in Claim 2, wherein said third and fourth transistors are cross-coupled transistors.

4. A reference voltage generating circuit as claimed in any preceding claim, wherein said current mirror circuits, two transistors and said resistors are fabricated on a CMOS integrated circuit using MOS technology and provide means for reducing temperature variations in the constant voltage.

5. A reference voltage generating circuit substantially as herein described with reference to Figures 6 to 7 of the accompanying drawings.