GB2293665A

GB2293665A - A look-ahead scheme.

Info

Publication number: GB2293665A
Application number: GB9419614A
Authority: GB
Inventors: Richard Simpson
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1994-09-29
Filing date: 1994-09-29
Publication date: 1996-04-03
Also published as: DE69526618D1; JPH08185310A; US5739745A; EP0704793B1; DE69526618T2; JP3696669B2; GB9419614D0; EP0704793A2; EP0704793A3

Description

2293665 IMPROVEMENTS IN OR RELATING TO A COMPARATOR SCHEME This invention

relates to improvements in comparator schemes, as carried out in the Arithmetic Logic Unit (ALU) ofa microprocessor.

A typical microprocessor includes the following functional blocks. A central Processing Unit (CPU) which comprises circuitry required to access the appropriate locations in memory and interpret resulting instructions. The execution of the instructions take place in the CPU. The CPU contains the Arithmetic Logic Unit (ALU), a control section, various registers etc.. The exact content of the CPU will obviously vary depending on the application of the microprocessor. The ALU is a combinational network that performs arithmetic and logical operations on data. Typical operations which are carried out include adding, subtracting, multiplying, dividing and comparing operations.

In operation the speed of the processor is dependent on the speed of' operation of any of the individual blocks within the processor. In addltlol-i there is constant effort being undertaken to make the components of the, processor both smaller and less speed critical.

Certain methods have been proposed to determine whether the sun-, of' t,, %,o number will be equal to a third. One such method is disclosed iii (jur patent application GB9404377.5 (TIL-17549 GW. In this method the surti of two or more variables is compared with a predetermined constant value.,L\ 1 test is carried out which confirms that the sum is either equal to or not equal to the constant value.

One problem With this niethod is that if the test confirms that the sum is not equal to the constant there is no way of knowing which is larger than the other. There are methods which determine the larger of two numbers, but this obviously causes a delay and requires more hardware.

One object of the present invention is to provide a method which tests whether the sum is equal to, greater than or smaller than the constant value with one simple test.

According to one aspect of the present invention, there is provided comparator scheme for determining the result of a mathematical operatio without carrying out said mathematical operation, comprising the steps of. obtaining the value of two or more variables; comparing said variables with a plurality of predetermined conditions thereby determiMng whether the result of the mathematical operation will be equal to a predetermined value; determining if the test is positive in which case concluding that the result of the mathematical operation is the predetermined value; determiming if the test is negative in which case concluding that the result of the mathematical operation is not the predetermined value; and in the event that the test is negative using the results of the comparison to determine whether the result of the mathematical operation is greater than or less than the predetermined value.

This has the advantage that is possible to determine ".hether the sum is equal to, greater than or smaller than the constant value.

2 Reference will now be made, by way of example, to the accompanyingg drawings, in which:

Figure 1 is a diagram of one part of the circuit of the. invention; Figure 2 is a diagram of the structure postion of a magnitude comparator according to the present invention; and Figure 3 is a diagram of the functions included in each block of the Figure 1 structure.

The invention is concerned with identifying the value of the sum of A and B relative to a predetermined value V.

The first part of the new circuit is based on the method for perfonaling an A+13=V test. This relies on comparing the possible carry values with those required to produce the correct target result. It checks if there are any occurences where the carry path cannot have the value required to produce the sum, if there are no occurences then A+B equals V. If there are occurences, then A+B does not equal V. The following is one method by which the method operates.

The INPUTS to the carry ripple portion of an adder at any bit position [n] can be represented using three MUTUALLY EXCLUSIVE variables, namelY- P[n] Propagate, Cout=Gin G[n] Generate, Cout=1 3 When adding 1+0, or 0+ L When adding 1+1; and K[n] Kill, Cout=0 When adding 0+0.

Consider the following simple sum.

Sum[n]=PM xor Cout[n-11.

If P[ii-11 is false, then Cout[n-11 is known and so Sum[n] can be determined with certainty. If PIn-11 is true, then Cout[n-11 is not known and so Sum[n] is not known. But, if P[n] is also true then Sum[n] will be the same as Sum[n- 11. Or, if P[n] is false then Sum[n] will be the opposite to Sum[n- 11.

From this it can be seen that examination of P[n,n-fl, G[ii,n-1] and K[n, n-1] will lead to four possible conditions:- 1 2 3 4 Surn[n]=0; Sum[n]=1; Sum[n]=Sum[n-11; and Sum[n]=Sum[ri- 11.

From this information it is possible to make further assumptions. If' P[n11=0 for a certain Sum[n]=O, then:P[n1=1 and G[n-11=1; and/or P[n]=O and K[n-11=1.

Similarly if P[n-1]=O for a certain Sum[n]=1, then:P[n1=0 and G[n-11=1; and/or P[n1=1 and K[n-11=1.

4 It further follows that if P[ri-11=1 for Sum[n]=Sum[n-11 then P[nj=1 and for Sum[n]=-Sum[ri-11 then PM=0 As can be seen, EITHER the Sum is known, OR the relationship to the previous bit is known. If the full result of the ADD is known, all that is required to test if the answer is the required value, is for each bit to say if it is correct, (i.e. invert if testing for zero, pass if testing for 1), and put these into a wide fast parallel AND gate.

This method does not wait on the SUM at each bit to be available, but considers overlapping pairs. The TEST at each bit is a double test, EITHER Sum[n] is known, and it is correct, OR IF Surn[n] is not known, its relationship to Surn[n-11 must be correct. If the double test PASSES at EVERY bit position the answer WILL be the required result. If this double test FAILS at ANY bit position the result WILL NOT be the required result.

The tests are as fol-lows:- If the target result is 00 i.e., we want to know if Sum[nj=0 and Sum[n11=0 then EITHER Sum[ril=0, OR Surn[n]=Sum[ri-11 which yields the following:- PM=1 and G[ri-11=1 Sum[ril=0; P[nj=0 and K[ri-l]=1 Sum[ril=0; and P[nl=l and Rri-11=1 Sumlnl=Sum[n-11.

This can be simplified to be P[n] xor Ktn- 11.

If the target result is 01 i.e., we want to know if Sum[nj=0 and Sum[n l]=1 then EITHER Sum[n]=O, OR Sum[n]=Sum[ii-11 which yields the following:

P[n]= l and G[ii-11=1 Sum[nj=0; PM=0 and Ktri-11=1 Sum[n]=0; and P[nj=0 and Rn-11=1 Sum[n]=Sum[n-11.

This can be simplified to be P[n] xor G[n-11.

If the target result is 10 i.e., we want to know if Sum[n]= l and Sum[n l]=0 then EITHER Sum[n]=l, OR Sum[n]=Sum[n-11 which yields the following:

P[n]=0 and G[n-11=1 Sum[n]=1; P[n]=1 and K[n-11=1 Sum[n]=1; P[nj=0 and P[n-11=1 Sum[n]=Sum[n- 11.

This can be simplified to be P[n] xor KIn-11.

If the target result is 11 i.e., we want to know if Sum[n]=1 and Sum[n 11=1 then EITHER Sum[ril=l, OR Sum[n]=Sum[ii-11 which yields the following:

Rnl=0 and G[ri-11=1 Sum[n]=1; P[n]= l and K[n-11=1 Sum[n]= l; and P[n]=1 and Rn-11=1 Sum[n]=Sum[ii-11.

This can be simplified to be P[n] xor G[n-11.

If we create two new variables, i.e.:P[n] xor K[n-l]=Z[n]; and PM xor G[n11=H[n], then the 00 test is Z[n], the 01 test is -H[n], the 10 test is Z[n] and the 11 test is H[n]. The test for bit zero is slightly 6 different. Here it is necessary to test for a 1 with P[O1 xor cIn; and test for a 0 with P[O1 xor cin. (i.e. evaluate it). The table below illustrates, this.

1 1 1 100 1 1 HI-IHZZ11H these must be ANDed together.

One way of implementing all this is to build 2 extra xor gates per ALU bit, and create the Z[n] and H[n] terms. These are then used, as appropriate, as inputs to a wide AND gate to detect any required value. This is very simple for a constant, for example C.

To compare against a register value, R, the circuit of figure I may be used. This circuit uses eight more transistors than the XOR gate that is required if the Sum is used, but these gates are now not speed critical, and so could be substantially smaller than would previously have been the case. As can be seen from the figure a circuit to carry out the invention may comprise two XNOR gates 12, 14 and a MLTX 16. Outputs of the XNOR gates are passed to the MLTX and the register value R[n-11 determines which to pass to the AND gate. Obviously this is just one means by which the function of this invention can be acheived. As will be apparent to the man skilled in the art other Boolean architectures can be chosen which have the same result.

The second part of the new circuit takes these results a stage further by indicating what the effect of the incorrect carry value will be. This is achieved by comparing the required "carry in" at every bit position to produce the target result with the actual carry in. If the carry required to produce, the target value is a 1, but the actual carry is a 0 the result will be less than the 7 target value. If' the required carry is a 0, but the actual carry is a 1, the result Arill be more than the target value.

Within an addition it is quite possible for there to be niany places where the required carry and the actual carry differ. It is necessary to use, the difference with the most significant bit (MSB) position to determine the result of the A+13≥V test. This is where the conventional (A≥13) magnitude comparator is used. A simple two operand magnitude comparator finds the most significant bit position where the two operands are different and this is used to say if A>B or B>A. (If, at this position, A[n]=1 and B[iil=0 then AA3, or, ir A[rol=0 and B[nl=l then B>A.

The required carry in (Cinr[n]) is easy to determine. The result at any position is Sum[n] = P[n] xor Cin[n], where Cina[n] is the actual carry, in. From this, it can be seen that the required carry in Cinr[n] = (P[n] xor KM).

Referring to Fig-ure 2, in this case the comparator will transfer the value of the required carry in (Cinr[n] at the most significant bit position where the M values indicate the carry path will not produce the required target value V. Figure 3 shows the detail of each block.

If ZH[n] = 0, then the corresponding Cinr[n] is irrelevant.

Only if ZH[n] = 1 is Cin-r[n] relevant, and then the value of'Clnr which corresponds to the most significant zero of ZI-Itn] is the one that determines the result.

8 The method shown in Figures 2 and 3 is a way of transferring to the output value of Cinr[n] which corresponds to the most significant zero of ZH[n].

For example:

n 7 6 5 4 13 2 1 0 Cinr 0 1 0 0 1 0 1 0 M 1 1 0 1 0 1 0 1 In this case Z1-1[5] is the most significant zero and so Cinr[51 (0) must be transferred to the output For example:

n 7 6 5 4 3 2 1 0 Cinr 0 1 0 0 1 0 1 0 M 1 1 1 0 1 0 1 In this case Z11[31 is the most significant zero and so CirirM (1) must be transferred to the output Figure 3 shows the basic building block for this.

2 adjacent input values of Cinr and ZH are combined and reduced to a single set of Cinr(out) and Z11(out) in the following manner. If both M inputs are 1, then both Cinr[O1 and Cinr[l] are irrelevant and this is indicated by Z11(out) also being al. (The AND gates does this).

If Z1-1[11 = 0 then Cinr[l] is the value which determines Cinr(out) and so it is transferred to the output. If ZH[II = 1 then Cinr[O1 will be transferred to the output. (The MUX does this).

9 This can be summarised as follows:

M[11 ZW01 ZE1[out] transfer 0 0 0 Cindll 0 1 0 Cindll 1 0 0 Cinr[O] 1 1 1 Cinr[O] The last case where M[11 = ZH[O] = 1, the transfer out is actually a 'don't care'.

Figure 2 shows how the basic building block is recursively combined in order to keep reducing the number of terms until eventually there is only a single ZH (the AND of all input ZH's) and a single Cinr which has come from the most significant ZH[n]=O, if there is one.

The Z and H values are used to determine if the sum A+B will be equal to K. If they are not, the value of the required carry-in at the left most failing position determines which is the larger, A+B or K.

The advantages are that this circuit is significantly faster than performing the addition and then passing the result to a magnitude comarator. The number of transistor per bit required for this circuit is constant, and the delay increases only logarithmically.

Examle 1 Compare 29 + 7 with 33 33 100001 requires Z ZZZ -ZH 29 011101 +7 H -H z _z Cinr = V xor p 000111 kppgpg 010000 101111 011011 100100 ZM2H_ 111010 <--- fails at [21 and [01 111011 left most fail is in bit [21. V[2] = 0 p[21 = 0 Cind21 = V121 xor p[2] = 0 required carry in is 0, therefore A+B >V Exami)le 2 Compare 29 + 7 with 38 38 requires 29 +7 H H z Z 100110 -2 ZW H 011101 000111 kppgpg 010000 101111 011011 100100 Z ZW H 111001 <--- fails at [21 and [11 left most fail is in bit [21. V121 1 p[21 0 Cind21 = V[21 xor p[2] = 1 required carry in is 1, therefore A+B < V 12

Claims

1. A comparator scheme for determining the result of a mathematical operation without carrying out said mathematical operation, comprising the steps of. obtaining the value of two or more variables; comparing said variables with a plurality of predetermined conditions thereby determining whether the result of the mathematical operation will be equal to a predetermined value; determining if the comparison is positive in which case concluding that the result of the mathematical operation is the predetermined value; determining if the comparison is negative in which case concluding that the result of the mathematical operation is not the predetermined value; and in the event that the comparison is negative using the results of the comparison to determine whether the result of the mathematical operation is greater than or less than the predetermined value.

A comparator scheme according to claim 1, wherein the comparing step comprises inputing the variable values and the predetermined conditions into a logic circuit which compares them to determine equality.

3. A comparator scheme according to claim 2, further comprising providing the logic circuit including two XNOR gates.

4. A comparator scheme according to claim 3, further comprising feeding the outputs from the XNOR gates to a MUX.

cl 13

5. A comparator according to any preceding claim, wherein said step of' determining if the test is negative or positive further comprising using an AND gate.

6. A comparator scheme, according to any preceding claim, wherein the step of using the results of the comparison comprises, determining the magnitude and position of the most significant bit in which the value of the bit in the result is not the same as the equivalent one in the predetermined value; using the magnitude and position to determine whether the result is greater than or less than the predetermined value.

7. A comparator scheme substantially as hereinbefore described, with reference to and as illustrated in the accompanying drawings.

8. A comparator for determining the result of a mathematical operation without carrying out said mathematical operation, comprising: comparing means for comparing the value of two or more variables with a plurality of predetermined conditions thereby determining whether the result of the mathematical operation will be equal to a predetermined value; testing means for determining if the comparison is positive in which case concluding that the result of the mathematical operation is the predetermined value or for determining if the comparison is negative in which case concluding that the result Qf the mathematical operation is not the predetermined value; and determining means for using the results c 11 of the comaprison in the event that the comparison is 14 negative to determine whether the result of the mathematical operation is greater than or less than the predetermined value.

9. A comparator according to claim 8, wherein the comparing means comprises a logic circuit.

10. A comparator according to claim 9, wherein the logic circuit includes two XNOR gates.

A comparator according to claim 10, further comprising a MUX connected c c to the outputs from the XNOR gates.

A comparator according to any of claims 8 to 11, wherein the determining means comprise circuitry for determing the magnitude and position of the most significant bit of the result in which the value of the bit in the result is not equal to the equivalent bit in the predetermined value and circuitry for using the magnitude and position to determine whether the result is greater than or less than the predetermined value.

13. A comparator substantially as hereinbefore described, with reference to and as illustrated in the accompanying drawings.