GB2293503A - Switched mode power supply circuit - Google Patents

Abstract

A power supply circuit operating in switched-mode comprises a plurality of switching devices 12 connected to a common output 26 each to provide an output current to a common load. An arrangement 22, 21 is provided to ensure that the output current provided by each of the switching devices is shared such that at the maximum rating of the power supply each switching device contributes current substantially equivalent to its maximum current rating so that no switching device is overloaded. Many applications of the power supply are described, such as speed control of a motor. Control is by means of PWM 16a and current sensor 24 may be a Hall effect device. <IMAGE>

Description

SWITCHED MODE POWER SUPPLY CIRCUIT This invention relates to control of current equalisation in paralleled switched-mode circuits and includes any circuit operating in switched-mode, in which the switching circuits are paralleled to supply current to a load. A particular example of a switched-mode circuit is in inverters.

Inverters are used in many applications such as variable speed drives for ac motors and uninterruptible power supplies.

A number of different power semi-conductor devices have been used in the manufacture of inverters such as Thyristors, Gate-Turn-Off Thyristors (GTO), and Bipolar Transistors, all of which have maximum practical switching frequencies in the order of lkHz. The use of fast switching power-semiconductors, such as the Insulated Gate Bipolar Transistor (IGBT), allows a switching frequency of several kilo-hertz to be used; which has the benefit of producing a better quality output current waveform (i.e. lower harmonic distortion). Due to the better quality waveform the motor requires less de-rating and is therefore cheaper for a chosen shaft power.

Currently, for inverters above 100kW, commercially priced IGBT's are not available, (partly due to the relatively low demand for such devices). This limit may increase, but at some point will reach a technical/commercial limit. Therefore to achieve IGBT inverters of high power, the IGBT, or entire inverters must be operated in parallel. Due to economies of scale, it is often cheaper to parallel multiple inverter modules rather than develop/manufacture higher power units.

A problem with paralleling the inverter modules of any type, is that due to component tolerances the modules do not supply equal proportions of the current. As a consequence, the total rating of the combined equipment must be reduced in order to prevent the inverter module which is carrying the most load from being overloaded.

This derating limits the economic value by under-utilising the full capability of each inverter module.

The component tolerances are attributable to the power semiconductor itself and triggering circuit components such as optical-couplers. Component tolerancing in the triggering circuit result in a variation of delay in the triggering signal which becomes more significant at higher switching frequencies.

In an attempt to overcome this problem in parallel switching the devices, one method known to us is to hand tune the relative delays of the switching signal applied to each of the parallel switching devices to ensure that each device contributes substantially its maximum current capability at maximum load. In the case of identical parallel switching devices this adjustment will result in all devices delivering an equal proportion of the total load current. However, this is a time consuming process and variation of circuit components due to temperature variation and ageing can result in an imbalance occurring and limitation of the available power without overloading one of the devices.Alternatively, an attempt to avoid unequal sharing of current can be made by attempting to arrange for very tight tolerances of timing errors and voltage drop mismatch in order to keep the current imbalance as low as practically possible. With the tightest practical tolerancing, it is difficult to achieve an imbalance of less that about 7% on TGBT inverters. In order to keep all bridges operating within their rating, the total power output of the equipment would have to be reduced by 7%.

The present invention seeks to provide a circuit which ensures that at maximum loading each of the parallel switching devices provides substantially its maximum rated current and/or in the case of the use of identical switching devices supplies a substantially equal share of the current.

According to the invention there is provided a switched-mode power supply circuit, comprising a plurality of switching devices connected to a common output each to provide an output current to a load, characterised in that means is provided to ensure that the output current provided by each of the switching devices is shared such that at the maximum rating of the power supply each switching device contributes current substantially equivalent to its maximum current rating so that no switching device is overloaded or derated. Preferably, the relative contribution of current to the output by each switching device is controlled as a function of the ratio between its maximum current rating and the aggregate current ratings of the switching devices.The switching device may be identical such that the contribution of current to the output by each switching device is the same and is the total current divided by the number of switching devices.

In an implementation of the invention, means is provided for deriving an electrical signal representative of the output current to a load and for determining therefrom electrical signals representative of the contribution of current to be supplied by each of the switching devices, means is provided for deriving electrical signals representative of the current actually supplied by each of the switching devices and comparator meons is arranged to compare, for each switching device, the signal representative of the actual supplied current and the current being supplied and to provide a control signal for correcting the actual supplied current. In this arrangement the switching devices supply at all times a proportion of the total load current dependent upon their maximum rated load current capability.

In order that the invention and its various other preferred features may be understood more easily, some embodiments will now be described, but by way of example only, with reference to the drawings, in which: Figure 1 is a basic block diagram of a three phase inverter employing two parallel inverters in each phase to clarify the terminology used in this specification, Figure 2 is a basic block diagram showing a single phase for illustrating the problem resulting from timing errors in switching of parallel inverters, Figures 3a to 3c show pulse timings for the basic block diagram of Figure 2, Figures 4a to 4c show pulse timings for the block diagram of Figure 2, Figure 5 is a block diagram of one embodiment of the invention of a single phase switched-mode power supply employing multiple inverters only three of which are illustrated, and Figure 6 is a basic block diagram of a shift register and gating circuit useable in the circuit of Figure 4.

Throughout this specification the same reference numerals or characters will be used for similar elements or devices.

The drawing of Figure 1 shows an inverter having three phases P1, P2, P3, each having a first bridge or switching device B1 and a second bridge or switching device B2 each of which is connected between common d.c. voltage supply lines VDC+, VDC-. The bridges each comprise identical top arms 10 and a bottom arm 11 each of which comprises one or more semiconductor power devices or switching elements 12.

Each of the switching devices has an anti parallel reverse biased diode 13 connected between collector and emitter or source and drain. The base or gate of the semiconductor switch is driven by a gate drive 14 fed from a pulse input 15 via a signal isolation circuit 16. Referring now to Figure 2 there is illustrated a single phase comprising two bridges which are triggered from the output of a pulse width modulated square wave generator 16a via their associated signal isolator circuit 16 and gate driver 14.

The square wave generator operates at a frequency of 3.3kHz or higher and the voltage output from each bridge (averaged over 1 cycle of the square wave) is proportional to the mark to space ratio of the generator 16a whilst the output frequency from the bridge is proportional to the rate at which the mark to space ratio is modulated and is normally arranged to be 0 to 50 Hz. However, in particular applications such as the control the speed of a motor, the generator 16a may be arranged to provide variable mark to space ratio and variable speed of modulation. The output of the generator 16a may be coupled to the gate drive for example via a pulse transformer or by optical coupling to provide the signal isolation. The output from the junction between the switching elements 12 of each bridge is coupled via a series arrangement of inductor 17 and parasitic resistance 18 (which is representative of the sum of all series resistance in that current path) . The inductor limits the rate of rise of current in each of the paralleled arms, such that in the event of the semiconductor in one arm being triggered marginally before thAt in the paralleled arm, it will not conduct the total of the load current. Figure 2 illustrates the effect of timing errors caused by signal isolation and gate-drives assuming idealised switching elements. All voltages shown are referenced to VDC-.

Figures 3a to 3c show the relative pulse displacements in the circuit of Figure 2 in which Figure 3a is the waveform provided by the top arm 10 of the upper bridge, Figure 3b is the waveform provided by the top arm 10 of the lower bridge and Figure 3c is error waveform.

The average error voltage over one cycle pulse width modulation (PWM) due to timing errors is VERR.

T1-T2 VERR = # VDC P where T1 is the time period during which the top arm of the upper bridge is conductive.

T2 is the time period during which the top arm of the lower bridge is conductive P = PWM period Therefor V, = fp, # VDC .(T1 - T2) = fPWM # VDc # TERR Eqn. 1 Where TERR = T1 - T2 fPWM=1/P The error voltage VERR causes a differential mode current 1ERR to flow such that dIERR VERR = IERR # (R1 + R2) + # (L1 + L2) Eqn. 2 In steady state fPWM # VDC # TERR IERR = R1 + R2 = fPWM # VDC # TERR 2R where R1 = R2 = R Eqn.3 The error current as a proportion of the total current in each phase is Let Per-Unit Imbalance = IERR I1 fSWITCH # VDC # TERR 2.R.I1 fSWITCH # VDC # TERR 2. VR1 Where VR1 = Voltage drop across R1 Eqn. 4 On a typical inverter if fPWM = 3.103Hz TERROR = 1.10-6S VDC = 650V VR1 = 5V Then Per-Unit Imbalance = 0.2 i.e. one bridge will carry 20% more than the other.

Consequently, in order to keep the current within the rating of the bridge carrying the most current, the rating of the total equipment would have to be reduced by 20% compared with perfectly balanced bridges.

In order to ensure that a maximum current is available from the power supply circuit it is necessary to ensure that each of the bridges supplies substantially their maximum rating at the maximum rating of the power supply.

One way of doing this is to monitor the current from each of the paralleled arms, and modify the switching signals on the next PWM cycle to correct for an error in the current share. The fundamental principle of this arrangement can be seen from the waveform diagrams of Figures 4a to 4c, which can be compared with Figures 3a to 3c, and where Figure 4a illustrates the correction required to the top arm 10 of the upper bridge which results in the reduction of average error as can be seen in Figure 4c.If the error current in an arm is positive, (i.e. the arm is carrying more than the average current of the paralleled arms) then the rising edge of the next turn on pulse will be delayed by a predefined amount, TCORRECTION@ As with the timing error TERROR, the difference in voltage (averaged over one PWM cycle) caused by TCORRECTION is: VCORRECTION fPWB VDC . TCORRECTION Eqn. 5 The delay, TcORREcTrON is selected to be greater than the worst case time error TERROR, therefore VCORRECTION is always greater than VERROR.Consequently whenever the delay TCORRECTION is introduced, the resulting voltage imbalance (VERROR- VCORRECTION) becomes negative causing a reduction (ramping down) of error current 1ERROR (due to the inductor) IERR = ##### # (VERR - VCORRECTION) Eqn.6 When 1ERROR reaches zero the delay, TCORRECTION is removed.

Applying the delay, TION, when the current is greater than the average (IERROR > O) ; and removing the delay when the current is less than average (IERROR S 0 ), thereby controls the error current to zero and therefore equalises the current output from each of the paralleled arms.

An identical function is performed on the paralleled arm of the second bridge, therefore whenever it carries more than average current, its turn on signals are delayed causing a reduction in its current (and a corresponding increase in the current from bridge 1). Note that, as it is not possible for both bridges to carry more than average current, then at any time, at least one of the arms will not have a delay introduced. (If they are perfectly balanced i.e. TERROR = 0 then neither bridge will have a delay introduced.

In practice due to measurement error, it is necessary to set the threshold (the level of IERROR at which the delay is introduced) to slightly higher than zero (typically 3%).

This prevents the possibility of a delay occurring on all arms at the same time, which would prevent operation.

Note that for the top power-device in each arm, (i.e.

the one which is connected to VDC+) the definition of positive current is that current which is flowing out of the bridge: for the bottom power-device, positive current is regarded as current flowing into the bridge. The condition for delay on the bottom power-device is therefore based on the inversion of the current and average current signals.

The same principle can be applied to paralleling more than two bridges: i.e. if the current in a particular arm is greater than the average current from the paralleled arms (see Fig. 4). In a three phase bridge, each of the six arms has this function. For a three phase inverter comprising 3 bridges there are 18 such circuits.

Figure 5 shows schematically how the correction can be put into effect and shows a single phase circuit with three paralleled bridge circuits specifically illustrated but it will be appreciated that in principle any number of bridges could be employed in parallel operating in the same way.

As can be seen from the drawing the pulse width modulation generator is connected to each arm of each bridge by an individual delay circuit 21. Upper and lower arms of each bridge are driven by separate signals from output terminals of the generator 16a so that they are driven substantially in antiphase. Each delay circuit is responsive to a switching control input signal from a comparator 22 which is effective to cause the pulses from the generator 16a to pass straight through without delay or to be delayed by a predetermined amount which must be slightly greater than that which is required to correct the maximum anticipated imbalance between the bridges. The comparator has a first input 23 which receives a voltage related to the current supplied by the particular bridge as detected by a sensor 24 which may be for example a Hall Effect device. The voltage sensed by each of the sensors 24 are added together via a chain of summing circuits 25 to produce a voltage representative of the total current delivered to an output 26. This voltage is coupled via a divider having a divisor substantially equal to the number of bridges, to produce an output voltage representative of the current expected to be provided by each of the bridges. This voltage is coupled to a second input 28 of the comparators of each arm of all of the bridges such that when the voltage provided at input 23 exceeds the voltage at input 28, indicative that the arm is delivering too great a proportion of the current, the comparator provides an output which switches in the delay of the circuit 2 to compensate during the next cycle. When the situation is corrected, as determined by the comparator 22, the delay is no longer applied.

One way of providing the delay is to employ a shift register as is shown in Figure 6. Referring to Figure 6, the shift register is shown to have four switching stages and has a first input 31 which receives a pulse signal from the generator 16 a second input CK which receives a clock signal input of frequency higher than the pulse modulation frequency, and an output 33 coupled to a first input 34 of selector circuit 35. The PWM signal at the input 31 is also coupled to the "clear" input CL of each stage of the shift register so that the register is cleared by each PWM pulse. The selector circuit 34 has a second input 36 which is coupled to the first input 31 of the delay circuit so that it receives the PWM signal from the generator 16a.A third input 37 to the delay circuit 21 is coupled to the output from the comparator 22 (Figure 5) and forms a third input 38 to the selector circuit. The selector circuit selects either the delayed PWM signal or the undelayed signal in dependence upon the control signal received from the comparator.

As indicated in Eqn.5 the effect of the introduced turn-on delay, TCORECTI0N is to cause a correction voltage, VCORRECTION, which reduces the current imbalance. In addition to correcting the current imbalance caused by timing errors, VC0EECTION inherently compensates for current imbalance cause by other errors such as differences in voltage drop across power-devices, and different voltage drops across parasitic resistances. For correct operation, TCOFECTI0N must be large enough to generate a VOORRECTION which is greater than the sum of the voltage errors (caused by variation in timing, resistance, forward voltage drop in power-device etc).

By using this invention, tolerances of components are not critical to achieve a balanced current, thereby requiring minimal derating. This results in a significantly lower cost solution than previous arrangements, with the opportunity to parallel a greater number of bridges utilising all power-devices closer to their maximum rating.

In the embodiment described in connection with Figure 5 identical switching elements 12 were employed and it will be appreciated that this simplifies the circuits in that a common divider circuit 27 can be employed as each switching element is required to contribute an equal share of the total current supplied by the power supply circuit.

however, this need not be the case and different switching elements can be employed in different bridges in which case different division ratios would be necessary and as each element would be required to supply a contribution of current which is substantially equivalent to the ratio between its maximum current rating and the aggregate current ratings of the switching devices in order that each switching device contributes its maximum rated current at the maximum supply rating of the power supply circuit.

Such an arrangement is considered to fall within the scope of this invention.

There are various alternative arrangements to the embodiment described which result in constructions which are intended to fall within the scope of this invention.

The embodiment described uses the principle of controlling the position of the PWM edges to individual arms of paralleled inverters (relative to a nominal position) in orjer to cause a difference in voltage which is used to control the current imbalance to near zero (typically 3% imbalance). It implements the above principle by using "bang-bang" control of the delay (delay/no delay) of the turn-on edges of the signal. Other variations of implementation could be as follows.

1. Controlling the degree of advance of turn-on or turn off edges. This would require additional signalling from the PWM generator (as it is not possible to predict when an edge will occur).

2. Controlling the delay of the turn-off edges. This would cause a reduction in dead-time. Dead-time is the time between the turn-off edge of top power-device and the turn-on edge of the bottom power-device, and vice versa; required to prevent a short circuit caused by top and bottom devices conducting at the same time.

In order to allow for this reduction in dead-time, the nominal dead-time would have to be increase by the delay value Tco cTIoN- This would cause degradation in the performance of the drive.

3. Linear/incremental control of the advance/delay of the edges e.g. delay is proportional to error.

4. Multiple synchronised PWM generators each of which controls the relative position of the PWM edges.

5. The principle of this invention could be implemented in software such that PWM signals are separately generated for each of the paralleled arms.

There are many uses for the current invention some examples of which are as follows: Any power circuit which uses switched-mode power semiconductors. (power inverter/converter/chopper topology.) Such topologies may be used in, the following applications: Un-interruptible Power Supplies (UPS) High power Switched Mode Power Supplies (SMPS) High power Class D Audio amplifiers (when technology becomes available) Welding Power Supplies Solid State Power Factor Correction Equipment Solid State Harmonic Current Compensators Photo Voltaic Cells (charging control) Plating Systems power supplies Ozone/Gas Production Equipment power supplies Induction/Resistive Heating Equipment.

The invention is applicable to any type of power circuit which uses controlled power devices operating in switched-mode.

Claims (17)

CLAIMS:

1. A switched-mode power supply circuit, comprising a plurality of switching devices connected to a common output each to provide an output current to a load, characterised in that means is provided to ensure that the output current provided by each of the switching devices is shared such that at the maximum rating of the power supply each switching device contributes current substantially equivalent to its maximum current rating so that no switching device is overloaded or derated.

2. A switched-mode power supply circuit as claimed in Claim 1, characterised in that the relative contribution of current to the output by each switching device is controlled as a function of the ratio between its maximum current rating and the aggregate current ratings of the switching devices.

3. A switched-mode power supply circuit as claimed in Claim 2, characterised in that the switching devices are identical such that the contribution of current to the output by each switching device is the same and is the total current divided by the number of switching devices.

4. A switched-mode power supply circuit as claimed in Claim 2 or 3, characterised in that means is provided for deriving an electrical signal representative of the output current to a load and for determining therefrom electrical signals representative of the contribution of current to be supplied by each of the switching devices, means is provided for deriving electrical signals representative of the current actually supplied by each of the switching devices and comparator means is arranged to compare, for each switching device, the signal regresentative of the actual supplied current and the current to be supplied and to provide a control signal for correcting the actual supplied current.

5. A switched-mode power supply circuit as claimed in Claim 4, characterised in that the electrical signals representative of the current actually supplied by each of the switching devices are coupled to a summing circuit forming the means for deriving an electrical signal representative of the output current to the load.

6. A switched-mode power supply circuit as claimed in Claim 5, characterised in that the switching devices are identical and the output from the summing circuit is coupled to a divider, with a divisor value equal to the number of switching devices, to provide a common signal representative of the contribution of current to be supplied by each of the switching devices which common signal is coupled to individual comparators of the comparator means.

7. A switched-mode power supply circuit as claimed in Claim 4, 5 or 6, characterised in that, for each switching device, a controllable delay device is provided which is responsive to the control signal to advance or delay the leading edge of a switching pulse as supplied to the particular switching device thereby to adjust the contribution of current by the switching device and compensate for incorrect current sharing.

8. A switched-mode power supply circuit as claimed in Claim 7, characterised in that the controlled delay device is an on/off device arranged to provide a predetermined delay in response to an appropriate control signal.

9. A switched-mode power supply circuit as claimed in Claim 8, characterised in that the predetermined delay is arranged to be greater than that which is required to correct the predicted maximum incorrect current share by the switching device.

10. A switched-mode power supply circuit as claimed in Claim 7, 8 or 9, characterised in that the delay device comprises a shift register having a first input for the power supply switching signal, a second input for a clock frequency which is high compared with the frequency of the switching signal and an output which provides an output switching signal having the predetermined delay, and the delayed switching signal and the non delayed switching signal are coupled with selection means for each switching device which is responsive to the control signal to route selectively one or other of them to the switching device.

11. A switched-mode power supply circuit as claimed in any one of Claims 7 to 10, characterised in that the switching devices are normally responsive to unmodified switching pulses for the power supply and the control signal for each device is effective to select delay of the pulses to that device when its supplied current share is determined to be too high.

12. A switched-mode power supply circuit as claimed in any one of Claims 7 to 10, characterised in that the switching devices are normally responsive to delayed switching pulses for the power supply and the control signal for each device is effective to select non delay of the pulses to that device when its supplied current share is determined to be too low.

13. A switched-mode power supply circuit as claimed in any one of the preceding claims, characterised in that each of the switching devices is coupled to the common output via an inductor to prevent instantaneous rise/fall of load current when the device switches.

14. An inverter comprising a switched-mode power supply as claimed in any one of the preceding claims, characterised in that each switching device comprises a pair of switching elements connected in series between positive and negative voltage supply lines, a junction between each pair of switching elements being connected to a common output.

15. An inverter comprising a switched-mode power supply as claimed in any one of Claims 4 to 13, characterised in that each switching device comprises a pair of switching elements connected in series between positive and negative voltage supply lines, a junction between each pair of switching elements is connected to a common output, each controllable delay device comprises a pair of delay circuits, one for each switching element of the pair, which delay circuits of each pair have a first input coupled to a different one of the two output terminals of a pulse generator such that they receive opposite going pulses therefrom and a second input for receiving a control input for effecting delay.

16. A switched-mode power supply circuit substantially as described herein with reference to the drawings.

17. An inverter substantially as described herein with reference to the drawings.