GB2292028A

GB2292028A - Low cost sigma-delta modulator

Info

Publication number: GB2292028A
Application number: GB9512071A
Authority: GB
Inventors: Kenneth G Richardson
Original assignee: Hewlett Packard Co
Current assignee: HP Inc
Priority date: 1994-07-28
Filing date: 1995-06-14
Publication date: 1996-02-07
Also published as: JPH0865166A; GB9512071D0; DE19518508A1

Description

LOW COST SIGMA-DELTA MODULATOR

FIELD OF INVENTION

2292028 This invention relates generally to electronic signal processing and more specifically to sigma-delta analog-to-digital converters.

BACKGROUND OF THE INVENTION

Many electronic or electro-mechanical products have requirements for conversion of analog electronic signals into numerical representations (analog-todigital conversion) for use by a microprocessor. A commonly used design for analog-to-digital conversion is the sigma-delta analog-todigital converter. Sigmadelta analog-to-digital converters are widely used in various applications such as digital audio, modenis and digital signal processors. There are two parts to the converter, a sigma-delta modulator and a digital filter. There are numerous articles describing extensive research efforts to improve these converters in the areas of sample rate, linearity, resolution and signal-to-noise ratio. Higher order architectures, the effects of over-sampling, improved digital filters and so forth have all been extensively described. For general background, a selected bibliography may be found in Temes, G.C. and Candy, J.C., "A Tutorial Discussion of the Oversampling Method for A/D and D/A Conversion," 1990 IEEE International Symposium on Circuits and Systents, 1990, Vol. 2, pp 910-913. In general, the published improvements increase the complexity and cost of the converter design by adding additional analog feedback loops and by adding analog circuitry to compensate for analog parameter tolerances and analog component mismatch. The invention is in the opposite direction, focusing on cost over precision and performance.

There are applications in which an analog-to-digital converter is needed for simple mcasurcinent and control and in which precision is not as important as cost. For example, residential lighting control systems, motor control systems in consumer electronics products, computer peripherals such as printers and mass Is memory products, automotive control systems and factory floor automation often have requirements for a rudimentary, relatively low precision analog-to-digital converter. Many products having a microprocessor also have an all-digital Application Specific Integrated Circuit (ASIC) or they perhaps have a microprocessor and ASIC combined into one chip. In products having an ASIC, typically the most cost effective design for the electronics is to put as much functionality as possible into the ASIC. Analog-to-digital conversion, however, typically requires separate active analog components or a relatively expensive integrated circuit process that permits mixed analog and digital circuitry within one integrated circuit. There is a need for an analog-to-digital converter for various measurement and control applications, providing low to moderate precision and performance but at the lowest possible cost. In many cases, lowest possible cost ineans minimizing die number of active analog components external to a microprocessor or ASIC.

SUMMARY OF THE INVENTION

The invention provides a sigma-delta modulator with all active analog ftinctions implemented entirely by digital circuitry. In particular, the invention can he implemented within an all-digital ASIC. The only external components are resistors and optional capacitors. In the invention, the functionality of an analog integrator and an analog comparator is realized using digital inverters. One inverter is operated in an analog mode. In one embodiment, the output is single bit scrial. In an alternative embodiment, two identical one-bit modulators are configured to provide a differential-in differential-out modulator. The differential mode reduces the effects of offset and non-linearities inherent to digital circuitry.

W CASE# 1003egs BRIEF DESCRIPTION OF THE DRAWINGS

Figure IA is a block diagram schematic of a simple amplifier circuit.

Figure 1B is a block diagram schematic of a sigma-delta analog-to-digital converter.

Figure 2A is a block diagram schematic of a sigma-delta analog-to-digital converter in accordance with the present invention.

Figure 2B is a block diagram schematic of a sigma-delta analog-to-digital converter in accordance with die present invention have improved performance relative to the circuit of figure 2B.

is Figure 2C is a block diagram schematic of the circuit of figure 213 illustrating the analog functions provided by digital inverters in figures 2A and 2B.

Figure 3 is a block diagram schematic of a differential sigma-delta analog-todigital converter in accordance with die invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION

Figure IA depicts a simple differential amplifier circuit. In general, if the amplifier 100 in figure IA is within its linear operating region, the amplifier output 102 is the open loop gain K times the differential input voltage (the difference between the voltages at input terminal 102 and input terminal 104). With a sufficiently high open loop gain K, the differential input voltage is Hp CASE# 1093095 essentially zero so that die voltage at input terminal 104 is driven to equal the reference voltage at terminal 106. The output voltage 102 is proportional to the input voltage 108 and the output voltage 102 tracks die input voltage 108 essentially instantaneously (as compared to die digital circuits described below).

Is Figure III illustrates a typical sigma-delta analog-to-digital converter circuit comprising a sigi na-delta modulator 110 followed by a digital filter 112. The' sigma-delta modulator 110 has a summing junction 114 followed by an integrator 118, an analog comparator 120 and a clocked latching circuit 122. A feedback path has a one-bit digital-to-analog converter 124, which is often just a simple resistor. Modulator 110 may be viewed as a variation of the amplifier circuit in figure IA except that after a change in the input, steady state conditions are not achieved instantaneously. The binary output (and subsequent feedback signal) is updated periodically rather than continuously. At each clock period, the feedback signal from the binary output of latch 122 drives the summing junction 114 in the direction required to minimize the input 116 to the integrator 118 but steady state conditions may require several clock cycles to achieve. Viewing die summing junction output 116 as an error signal, the closed loop modulator I 10 drives the average error signal, over a time period, to equal zero. That is, the average (over time) of the binary output of latch 122 is proportional to the input voltage 108 (relative to the reference voltage of integrator 118). If the analog input voltage to the delta-signia modulator 100 is constant, the output of the delta-sigma modulator 100 is binary bit serial with the number of logical "ones" per unit time proportional to the analog input voltage. Therefore, one solution for the digital filter 102 is to simply nurnerically add the modulator output logical "ones" over a unit time. Of course, there are more optimal filters than simple adding. In many applications, the digital filter is an implementation of a class of filters called decimation filters. A decimation filter for a delta-sigma modulator is designed to attenuate out of band signals, to suppress quantization noise and further optimize W CASE # 100095 the overall analog-to-digital circuit frequency response, signal-to-noise ratio and linearity.

The summing junction 114 is typically a passive resistor network as in figure IA but may also be a switched capacitor circuit. Tile integrator 118 is typically an analog operational amplifier with capacitive feedback. The combination of an analog comparator 120 and latch 122 is sometimes describid as a one-bit analog-to-digital converter.

In general, a digital inverter is just. a high gain amplifier, but optimized for its saturation characteristics and deliberately operated in a saturation mode rather than in a linear mode. For a digital inverter, there is a narrow range of input signal amplitudes that will cause the output signal to be non-saturated (an intermediate voltage between the power supply voltages). lit most digital applications, a digital inverter is driven by other digital circuitry having low output impedance and sufficient output current to drive the inverter/amplifier rapidly from one non-linear saturated output state through a linear non-saturated range into the opposite non-linear saturated output state. With a high impedance driver and resistive feedback from output to input, however, a digital inverter can act as a feedback amplifier. In addition, a digital inverter can be modeled as an analog comparator. An analog comparator is basically a high gain differential input amplifier with an output stage optimized for digital characteristics. A single stage (unbuffered) digital inverter has a single input but also effectively has an internal reference voltage at the midpoint of the output logic levels. Therefore, a 5 Volt digital inverter call also be modeled as an analog comparator having a fixed internal threshold, typically at 2.5 Volts. In the following discussion, an inverter is sometimes specified as a single stage (unbuffered) inverter. All example of a single stage inverter is the 74HCU04 available from a variety of vendors. Some digital inverters have multiple stages, typically an input stage, a gain stage and an output stage. In the invention, multiple stage inverters can be used but they are more expensive than single-stage inverters. In addition, in the following discussion, W CASE P 1093695 to is where an internal capacitance is referred to, if the inverter is multiple staged, only the first stage internal capacitance is relevant.

The invention will now be explained relative to the circuits illustrated in figures I A and IB and the above comparisons of inverters, amplifiers and comparators. Figure 2A illustrates a very low cost sigma-delta modulator circuit in accordance with the invention, in which all active elements are implemented by digital circuitry, preferably within an alldigital ASIC. In general, the most simple integrator is a passive capacitor or a passive inductor. Accordingly, in the circuit illustrated in figure 2A, the integration function 118 of figure 1B is realized by a capacitor 200. If needed, additional passive R-C integrator stages may be added. In addition, in the circuit illustrated in figure 2A, the comparator function 120 of figure IB is realized by a single stage (unbuffered) digital inverter 202. The inverter 202 and the latch 206 may be implemented in an all-digital ASIC. The only components outside the ASIC are the three passive components (capacitor 200, resistor 210 and resistor 212).

Figure 2B illustrates an improved embodiment of the invention using digital inverters not only as comparators as in figure 2A but also as an amplifier. In tile embodiment illustrated in figure 213, a single-stage (unbuffered) digital inverter 216 has a feedback path and is driven through high impedance sources. As a result, digital inverter 216 operates in a non-saturated mode and functions as all analog amplifier.. Digital inverter 218 is driven by the low impedance output of inverter 216 and functions as an analog comparator. Ideally the output of inverter 218 is saturated. This may not be true however when the output of inverter 216 is very close to the threshold of inverter 218. Therefore, to ensure a saturated input to the latch 206, additional inverters 220 and 222 provide additional gain (if needed) for the comparator function, as explained in more detail below.

Networks 226 and 228 are passive networks. Networks 226 and 228 may each be a single resistor as in illustrated in figure 2A by resistors 210 and 212 respectively. In general, however, with additional passive elements, networks 226 HP CASE 0 1093M is and 228 can help tune the overall modulator frequency response, provide AC coupling, or other filtering functions.

Figure 2C is the same circuit as figure 2B but drawn to emphasize the analog functions being performed by the digital inverters. Inverter 216 inside box 230 in figure 2B is equivalent to the circuitry within the dashed box 230 in figure 2C. In figure 2C, the 5 volt single stage digital inverter 216 of figure 2B is depicted as an analog amplifier 238 with an internal fixed reference voltage at approximately 2.5 volts and an inherent integrating capacitance 234. Likewise, the three inverters within box 232 in figure 2D are depicted as a single analog comparator 232 in figure 2C.

Functionally, the circuits in figure 2A-2C operate the same as the mixed analog/digital circuit illustrated in figure 113. The circuit in figure 2A operates to make the average over time of the binary output 208 proportional to the input voltage 214 (relative to the inherent threshold within inverter 202). The circuit in figures 2B and 2C operate to make the average over thme of the binary output 224 proportional to the input voltage 214 (relative to the inherent threshold within amplifier/inverter 216).

In figure 2C, capacitance 234 is an inherent internal capacitance. All transistors and amplifiers have some inherent capacitance from input to output. When the effects of the capacitance are amplified by the gain of the amplifier, the capacitance is sometimes called the Miller capacitance. In the case of MOS single stage digital inverters, the capacitance 234 is on the order of I picoFarad. When driven by low-impedance high-current digital circuits the capacitance 234 is insignificant. In the invention, the series resistances of networks 226 and 228 are chosen to be high resistance and the clock rate is relatively high so that the capacitance 234 is not negligible. Instead, capacitance 234 provides an important integration function for the amplifier 238. The integrated error voltage at input terminal 240 is driven to equal the inherent reference voltage 242, causing the amplifier 238 (inverter 216 in figure 213) to operate in an analog (non-saturated) lip CASE# 1093696 1.5 mode. An optional external capacitor 236 may be added to ensure a particular capacitance value or to achieve a specific frequency response.

Inverters, of course, are optimized for digital applications. There are numerous specifications that make them non-ideal for analog applications. In general, a sigma-delta modulator needs high forward gain and minimal loop delay. In the circuit illustrated in figure 2C, high forward gain is needed to ensure that signal amplitudes very near the voltage reference 242 of the integrating amplifier 238 will result in a digital (saturated) input to the latch 206. If a single inverter is used as a comparator, loop delay is minimized at the expense of forward gain. Adding additional inverters improves forward gain at the expense of loop delay. If.in odd number of inverters is used, the outputs of the latch 206 may be exchanged to ensure that the sign of the feedback is negative.

The binary output 224 is illustrated as coming from one latch output and the feedback signal is illustrated as coming from the other latch output. However, the modulator output can come froin the saine latch output as the feedback signal if appropriate for the digital filter for the analogto-digital converter.

In the circuits illustrated in figures 2A-2C, the effects of some part-topart variations and non-linearities ate minimized by integration and feedback. For example, the specific value of die comparator threshold of comparator 232 is relatively noncritical. Some parameters in the systems illustrated in figure 213, however, lead to an inherent offset in the system. In particular, the value of the reference voltage 242 for the amplifier/inverter 238 relative to the specific values for logical ones and zeros from latch 206 is important. For single stage digital MOS inverters, a logical zero is nominally one-third of the power supply voltage, a logical one is nominally two-thirds of the power supply voltage and tile switch point is nominally half way between the output logic levels. The requirements for a digital application arc such that tlicse voltage values can vary substantially from one integrated circuit to another or from one vendor to another while remaining within the specifications. In addition, for any one inverter, the voltages may not be lip CASE# 1093095 Is symmetrical. However, within any one integrated circuit, these voltage values tend to be consistent from inverter to inverter. One approach to minimizing the effect of these voltage variations is to implement a differential converter with all tile active parts within one integrated circuit.

Figure 3 illustrates a differential embodiment. The analog-to-digital converter of figure 3 receives differential input signals 300 and 302. Externai capacitors 300 and 302 are optional and remove any DC offsets in the input signal.,rhe two input signals are separately digitized by two identical modulators of the type illustrated in figure 2B. Then, digital differences are computed within a differential-input, single-output digital filter 308. At least the two inverter/amplifiers 310 and 312 should be within one integrated circuit. Preferably, all eight inverters as well as the two latches illustrated in figure 3 are within one integrated circuit. Computing the digital difference at the output cancels some of the effects of non-ideal but consistent parts within a single integrated circuit.

As discussed above, a goal of the invention is adequate performance and precision at low cost. With the differential embodiment of figure 3, the accuracy of the digital output 314 is limited to about seven bits with a signal-to-noise ratio better than 30 dB. Digital clock rates for embedded microprocessor applications are typically 16-20 MHz so that the circuit is useful in measurement and control applications requiring up to 100,000 6-bit samples per second. As discussed above, this performance and accuracy is adequate for many applications and when implemented within a digital ASIC, the invention provides a very low cost solution.

The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations inay be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its

MI CASE 9 1093696 practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative emboditnents of the invention except insofar as limited by the prior art.

W CASE# 1093095

Claims

What is claimed is:

11 1. A signal modulator having an analog input (214) and a digital output (208), the signal modulator comprising:

a capacitor (200) having a first terminal and a second terminal, the first terminal resistively connected to the analog input (214) of the signal modulator, the second terminal connected to a ground potential; a digital latch (206) having a latch input and a latch output, the latch output being the digital output (208) of the signal modulator, the latch output resistively connected to the first terminal of the capacitor; and at least one inverter (202), connected in series between the capacitor and the digital latch, having an inverter input and an inverter output, the inverter input conected to the first terminal of the capacitor and the inverter output connected to the latch input.
2. A signal modulator according to claim 1 modified in that the digital latch (206) is replaced by a digital latch as follows: a digital latch (206) having a latch input, a first latch output, and a second latch output, the second latch output being the logical complement of the first latch output, the first latch output being the digital output (208) of the signal modulator, the second latch output resistively connected to the first terminal of the capacitor.
3. A signal modulator having an analog input (214) and a digital output (224), the signal modulator comprising: a first inverter (230), having a first inverter input and a first inverter output, the first inverter operating in an analog mode; a passive input network (228) connected between the analog input and the first inverter input; a digital latch (206) having a latch input and a latch output, the latch output being the digital output (224) of the signal modulator; 17at least one inverter (232) connected in series between the first inverter output and the latch input; and a passive feedback network (226) connected between the latch output and the first inverter input.
4. The signal modulator of claim 3 fta-ther comprising: a capacitor (236) connected from the first inverter input to the first inverter output.
5. A signal modulator according to claims 3 or 4 modified in that the digital latch (206) is replaced by a digital latch as follows: a digital latch (206) having a latch input, a first latch output, and a second latch output, the second latch output being the logical complement of the first latch output, the first latch output being the digital output (224) of the signal modulator; and the passive feedback network (226) connected between the second latch output and the first inverter input.
6. A differential signal modulator comprising: first and second differential analog inputs (300, 302); first and second differential digital outputs; first and second passive input networks; first and second modulators, the first modulator having a first modulator input connected through the first passive input network to the first differential analog input and a first modulator output connected to the first differential digital output, the second modulator having a second modulator input connected through the second passive input network to the second differential analog input and a second modulator output connected to the second differential digital output.
7. The differential signal modulator of claim 6, the first modulator further comprising: a first inverter (310), having a first inverter input and a first inverter output, the first inverter input being the first modulator input, the first inverter operating in an analog mode; 13 a digital latch having a latch input and a latch output, the latch output being the first differential digital output; at least one inverter connected in series between the first inverter output and the latch input; and a passive feedback network connected between the latch output and the first inverter input.
8. The signal modulator of claim 7 further comprising: the first passive input network having a first coupling capacitor (304) connected in series between the first differential analog input and the first modulator input; and the second passive input network having a second coupling capacitor (306) connected in series between the second differential analog input and second modulator input.
9. The signal modulator of claim 8 further comprising:

an integrating capacitor connected from the first inverter input to the first inverter output.
10. A differential signal modulator according to claims 7, 8, or 9, modified in that the digital latch is replaced by a digital latch as follows:

a digital latch having a latch input, a first latch output, and a second latch output, the second latch output being the logical complement of the first latch output, the first latch output being the first differential digital output; and the passive feedback network connected between the second latch output and the first inverter input.