GB2290413A - Processing silicon in a plasma etch system - Google Patents

Processing silicon in a plasma etch system Download PDF

Info

Publication number
GB2290413A
GB2290413A GB9511873A GB9511873A GB2290413A GB 2290413 A GB2290413 A GB 2290413A GB 9511873 A GB9511873 A GB 9511873A GB 9511873 A GB9511873 A GB 9511873A GB 2290413 A GB2290413 A GB 2290413A
Authority
GB
United Kingdom
Prior art keywords
etching
gas
plasma
silicon
passivating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9511873A
Other versions
GB9511873D0 (en
GB2290413B (en
Inventor
Andrea Schilp
Gerhard Benz
Horst Muenzel
Franz Laermer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of GB9511873D0 publication Critical patent/GB9511873D0/en
Publication of GB2290413A publication Critical patent/GB2290413A/en
Application granted granted Critical
Publication of GB2290413B publication Critical patent/GB2290413B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01PMEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0802Details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • H01L21/30655Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Description

Method of Processing silicon
Prior art
2290413 The invention proceeds from a method of processing silicon in accordance with the generic class of independent Claim 1. US-4 784 720 has already disclosed a method of processing silicon in a plasma etching system, in which method an etching gas and a passivating gas are used. Employing the etching gas and the passivating gas creates a trench having a side-wall passivation. The etching gas used is a chlorine or bromine supplier. Since chlorine and bromine bring about an appreciable etching of silicon only at relatively high ion energies in the plasma, only strongly anisotropic etching profiles can be achieved with these etching gases. DE 39 27 163 AI discloses a method of processing silicon in which an etched trench is generated which has a side-wall passivation. Proceeding from the floor regions of the trenches, structures can then be underetched by isotropic plasma etching. Since a lowtemperature oxide or low-temperature nitride is provided as side-wall passivation, the method requires a plurality of processing steps in different etching systems and deposition systems (plasma etcher, PECW system or LP= system).
Advantages of the invention On the other hand, the method according to the invention having the characterizing features of independent Claim 1 has the advantage that not only can a trench having a side-wall passivation be generated but the structures so formed can also be isotropically underetched in one and the same etching system without the waf er having to be removed f rom the system in the meantime. A particularly simple method with which underetched silicon structures can be generated is thus specified.
The measures cited in the dependent claims make possible advantageous further developments and improvements of the method specified in the independent claim. The reinforcement of the side-wall passivation improves the lateral etching resistance of the silicon structures in the subsequent isotropic underetching. Silicon can be processed particularly easily and at high etching rates by means of a fluorine plasma. Process gases containing a fluorocarbon or fluorinated hydrocarbon form a side-wall passivation composed of a chemically particularly resistant fluoropolymer. As a result of low ion energy, simple and thin etch maskings can be used and large differences in the etching rate of silicon substrate and masking substance can nevertheless be achieved. This applies, in particular, at high plasma densities and low ion energy. Deep and narrow trench structures having a side-wall passivation can be formed by the alternating or simultaneous use of etching gas and passivating gas.
Drawings Exemplary embodiments of the invention are shown in the figures and explained in greater detail in the description below. Figure 1 shown a silicon substrate with an etch masking, Figure 2 shows etched trenches with side wall passivation introduced into the latter, Figure 3 shows the underetching proceeding from the floor region of the trenches and Figure 4 shows a plasma etching system.
Description of the invention
Figure 1 shows a silicon substrate 1 with an tl 3 - applied etch masking 2. The etch masking 2 does not cover the surface of the silicon substrate in specified regions. In these regions, an etch attack on the silicon is carried out in the subsequent process steps. Suitable an materials for the etch masking 2 are, for example, a thin layer of photoresist or silicon oxide. The silicon substrate 1 is introduced into a plasma etching system for subsequent processing.
Figure 2 shows the silicon substrate 1 after a first plasma etching step. Trenches 3 are introduced by etching in the regions which were not covered by the etching mask 2. At the same time, the trenches 3 have a side-wall passivation 4. in the region of the floor 5, the trenches 3 are not covered by a passivating layer 4, with the result that the silicon of the substrate 1 is exposed at that point. The trenches 3 are etched in by employing a gas which etches silicon isotropically and a gas which forms a passivating layer. The isotropically etching gas used is a gas which supplies fluorine, for example SF, or NF3. The passivating gas used is a Teflon forming monomer, as a rule a fluorocarbon or fluorinated hydrocarbon (CEF3. C2P61 C2F41 C4F8). The etching gas and passivating gas can be used simultaneously in the plasma etching system in a suitable mixture. Alternatively, it is possible to carry out alternately a multiplicity of consecutive etching and passivating steps. In this way, perfectly anisotropically etched trenches 3 of great depth (several 10 gm) and small width (a few g=) can be achieved in the plasma even at low ion energies (a few electron volts) assuming a high plasma density. Because of the low ion energy, the erosion of the etching mask 2 is small. As a consequence of the ion action, the floor 5 of the trenches 3 remains tree and is not covered by the Tefloiitype fluoropolymer film of the side-wall passivation 4. Furthermore, it is also possible to add additional gases such as nitrogen, oxygen or argon in order to modify the processing properties of the etching process. In order to ensure an adequate plasma density, i.e. an adequately high concentration of chemically reactive ions, despite the low ion energy, the plasma etching system should have a suitable source and, for example, a microwave or magnetron plasma excitation system.
After the desired etched depth of the trenches 3 has been reached, the actual etching gas su lying fluorine can be shut off and only the Tefloriforming passivating gas supplied. As a result of this process, the thickness of the side-wall passivation 4 can be increased. During this process, simultaneous ion action ensures that the passivating film forms selectively only on the side walls of the trenches 3 and not on the etched floor 5.
Figure 3 shows the trenches 3 after a further etching step. in said further etching step, the silicon substrate 1 is processed exclusively with the fluorinesupplying etching gas. In this process, the chosen energy of the plasma is in the order of magnitude of only a few electron volts, with the result that the etching takes place almost perfectly isotropically. The underetching 6 then forms proceeding from the exposed etched floor 5 of the trenches 3, as is shown in Figure 3. In this process, the ion energy is not set exactly equal to zero electron volts in order to still be able to remove accidental microscopic deposits on the floor 5 during the isotropic underetching. Because of the low ion energy, ions accidentally striking the side wall are scarcely responsible for any attack on the side-wall passivation 4 or on the etching mask 2. if, as is shown in Figure 3, two trenches 3 are disposed immediately next to one another, a silicon web 7 which is disposed between the two trenches 3 can be completely detached from the substrate 1 by the isotropic underetching 6. Such structures make it possible to achieve, for example, thin deflection tongues or comb structures which can be used as acceleration sensors.
A particular advantage of the process sequence shown in Figures 1 to 3 is that all the etching processes can be carried out in one process without interruption or outward transfer of the wafer in one and the same plasma system. The etching gases and passivating gases mentioned can be utilized with one another or after one another in one and the same etching system. Furthermore, they enable the formation of particularly narrow and deep trenches 3 which can be underetched in a subsequent process step. In this way, structures can be generated 10 which can be employed as sensors.
Figure 4 shows diagramnatically a plasma etching system 11. The silicon substrate 1 and a further plasmagenerating means 10 are introduced into the plasma etching system 11. A high-frequency voltage which 15 determines the energy with which ions strike the substrate 1 can be applied to the substrate 1. The further plasma-generating means 10 can be designed an a simple electrode, a microwave generator, a magnetron or any other plasma source which generates a high plasma 20 density.

Claims (8)

Claims
1. Method of processing silicon, in which a silicon substrate (1) is provided with an etch masking (2) and introduced into a plasma etching system and exposed to a plasma, a trench (3) having a side-wall passivation (4) being generated by processing with an etching gas and a passivating gas, characterized in that an underetching (6) proceeding from the etched floor (5) of the trench (3) is introduced in the etching system by the etching gas in a further processing step.
2. Method according to Claim 1, characterized in that the side-wall passivation (4) is reinforced by a deposition step prior to introducing the underetching (6) by etching.
3. Method according to one of the preceding claims, characterized in that a fluorine-supplying gas (for example, SF, or NP3) is selected for the etching gas.
4. Method according to one of the preceding claims, characterized in that a gas supplying fluorocarbon or fluorinated hydrocarbon (for example, CEF3. C2F6t C2P40 C4ps) is selected as passivating gas.
5. Method according to one of the preceding claims, 25 characterized in that the plasma energy is less than 50 electron volts, preferably less than 10 electron volts.
6. Method according to one of the preceding claims, characterized in that, to introduce the trench (3), the silicon substrate (1) is alternately processed with the etching gas and the passivating gas.
7. Method according to one of Claims 1 to 5, characterized in that, to introduce the trench (3), the silicon substrate (1) is simultaneously processed with a mixture of the etching gas and the passivating gas.
8. A method of processing silicon substantially as herein described with reference to the accompanying drawings.
GB9511873A 1994-06-16 1995-06-12 Method of processing silicon Expired - Fee Related GB2290413B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19944420962 DE4420962C2 (en) 1994-06-16 1994-06-16 Process for processing silicon

Publications (3)

Publication Number Publication Date
GB9511873D0 GB9511873D0 (en) 1995-08-09
GB2290413A true GB2290413A (en) 1995-12-20
GB2290413B GB2290413B (en) 1998-04-15

Family

ID=6520681

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9511873A Expired - Fee Related GB2290413B (en) 1994-06-16 1995-06-12 Method of processing silicon

Country Status (2)

Country Link
DE (1) DE4420962C2 (en)
GB (1) GB2290413B (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489248B2 (en) 1999-10-06 2002-12-03 Applied Materials, Inc. Method and apparatus for etch passivating and etching a substrate
US6555480B2 (en) 2001-07-31 2003-04-29 Hewlett-Packard Development Company, L.P. Substrate with fluidic channel and method of manufacturing
US6554403B1 (en) 2002-04-30 2003-04-29 Hewlett-Packard Development Company, L.P. Substrate for fluid ejection device
US6818562B2 (en) 2002-04-19 2004-11-16 Applied Materials Inc Method and apparatus for tuning an RF matching network in a plasma enhanced semiconductor wafer processing system
US6867061B2 (en) * 2001-02-06 2005-03-15 Robert Bosch Gmbh Method for producing surface micromechanical structures, and sensor
US6910758B2 (en) 2003-07-15 2005-06-28 Hewlett-Packard Development Company, L.P. Substrate and method of forming substrate for fluid ejection device
US6981759B2 (en) 2002-04-30 2006-01-03 Hewlett-Packard Development Company, Lp. Substrate and method forming substrate for fluid ejection device
US7312553B2 (en) 2001-10-20 2007-12-25 Robert Bosch Gmbh Micromechanical component and method for producing same
US8524112B2 (en) 2007-12-21 2013-09-03 Solvay Fluor Gmbh Process for the production of microelectromechanical systems
EP2879165A1 (en) 2013-11-28 2015-06-03 Solvay SA Etching Process

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19641288A1 (en) * 1996-10-07 1998-04-09 Bosch Gmbh Robert Process for anisotropic plasma etching of various substrates
DE19706682C2 (en) 1997-02-20 1999-01-14 Bosch Gmbh Robert Anisotropic fluorine-based plasma etching process for silicon
DE19736370C2 (en) 1997-08-21 2001-12-06 Bosch Gmbh Robert Process for anisotropic etching of silicon
DE19847455A1 (en) 1998-10-15 2000-04-27 Bosch Gmbh Robert Silicon multi-layer etching, especially for micromechanical sensor production, comprises etching trenches down to buried separation layer, etching exposed separation layer and etching underlying silicon layer
DE19906100C2 (en) * 1999-02-13 2003-07-31 Sls Micro Technology Gmbh Thermal flow sensor in microsystem technology
US6383938B2 (en) * 1999-04-21 2002-05-07 Alcatel Method of anisotropic etching of substrates
DE10234589A1 (en) 2002-07-30 2004-02-12 Robert Bosch Gmbh Layer system used in the production of micro-electromechanical structures comprises a passivating layer consisting of an inorganic partial layer and a polymeric partial layer formed on a silicon layer
DE10237249B4 (en) * 2002-08-14 2014-12-18 Excelitas Technologies Singapore Pte Ltd Method for the selective removal of material from the surface of a substrate
DE10237787A1 (en) 2002-08-17 2004-03-04 Robert Bosch Gmbh Layer system with a silicon layer and a passivation layer, method for producing a passivation layer on a silicon layer and their use
DE102004036803A1 (en) 2004-07-29 2006-03-23 Robert Bosch Gmbh Method for etching a layer on a substrate
CH708113B1 (en) 2007-09-13 2014-12-15 Stéphane Von Gunten Anchor for a watch escapement.
EP2232533A1 (en) * 2008-01-16 2010-09-29 Ipdia High aspect ratio holes or trenches
US8481400B2 (en) 2010-09-17 2013-07-09 Infineon Technologies Ag Semiconductor manufacturing and semiconductor device with semiconductor structure
DE102022212453A1 (en) 2022-11-22 2024-05-23 Robert Bosch Gesellschaft mit beschränkter Haftung Method for producing a micro-electronic-mechanical vibration system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3927163A1 (en) * 1989-08-17 1991-02-21 Bosch Gmbh Robert Structuring disc-shaped monocrystalline semiconductor - using photomask for ion-etching of recess(es), orthogonal to semiconductor main surfaces
EP0414372A2 (en) * 1989-07-21 1991-02-27 Sony Corporation Dry etching methods
WO1991003074A1 (en) * 1989-08-17 1991-03-07 Robert Bosch Gmbh Process for structuring a semiconductor body
EP0624900A2 (en) * 1993-05-10 1994-11-17 Delco Electronics Corporation Method of micro-machining an integrated sensor on the surface of a silicon wafer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4784720A (en) * 1985-05-03 1988-11-15 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
CA1260365A (en) * 1985-05-06 1989-09-26 Lee Chen Anisotropic silicon etching in fluorinated plasma
JPS61278146A (en) * 1985-06-03 1986-12-09 Toshiba Corp Optical treatment method
US4729815A (en) * 1986-07-21 1988-03-08 Motorola, Inc. Multiple step trench etching process

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0414372A2 (en) * 1989-07-21 1991-02-27 Sony Corporation Dry etching methods
DE3927163A1 (en) * 1989-08-17 1991-02-21 Bosch Gmbh Robert Structuring disc-shaped monocrystalline semiconductor - using photomask for ion-etching of recess(es), orthogonal to semiconductor main surfaces
WO1991003074A1 (en) * 1989-08-17 1991-03-07 Robert Bosch Gmbh Process for structuring a semiconductor body
EP0624900A2 (en) * 1993-05-10 1994-11-17 Delco Electronics Corporation Method of micro-machining an integrated sensor on the surface of a silicon wafer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
0PI Abstract Accession No. 91-058893/09 & DE-A-3 927 163 (BOSCH) 21.02.91 (SEE ABSTRACT) *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489248B2 (en) 1999-10-06 2002-12-03 Applied Materials, Inc. Method and apparatus for etch passivating and etching a substrate
US6867061B2 (en) * 2001-02-06 2005-03-15 Robert Bosch Gmbh Method for producing surface micromechanical structures, and sensor
US6555480B2 (en) 2001-07-31 2003-04-29 Hewlett-Packard Development Company, L.P. Substrate with fluidic channel and method of manufacturing
US7312553B2 (en) 2001-10-20 2007-12-25 Robert Bosch Gmbh Micromechanical component and method for producing same
US6818562B2 (en) 2002-04-19 2004-11-16 Applied Materials Inc Method and apparatus for tuning an RF matching network in a plasma enhanced semiconductor wafer processing system
US6893577B2 (en) 2002-04-30 2005-05-17 Hewlett-Packard Development Company, L.P. Method of forming substrate for fluid ejection device
US6981759B2 (en) 2002-04-30 2006-01-03 Hewlett-Packard Development Company, Lp. Substrate and method forming substrate for fluid ejection device
US7282448B2 (en) 2002-04-30 2007-10-16 Hewlett-Packard Development Company, L.P. Substrate and method of forming substrate for fluid ejection device
US6554403B1 (en) 2002-04-30 2003-04-29 Hewlett-Packard Development Company, L.P. Substrate for fluid ejection device
US6910758B2 (en) 2003-07-15 2005-06-28 Hewlett-Packard Development Company, L.P. Substrate and method of forming substrate for fluid ejection device
US8524112B2 (en) 2007-12-21 2013-09-03 Solvay Fluor Gmbh Process for the production of microelectromechanical systems
CN104979188A (en) * 2007-12-21 2015-10-14 苏威氟有限公司 Process for production of microelectromechanical systems
EP2879165A1 (en) 2013-11-28 2015-06-03 Solvay SA Etching Process

Also Published As

Publication number Publication date
GB9511873D0 (en) 1995-08-09
DE4420962A1 (en) 1995-12-21
DE4420962C2 (en) 1998-09-17
GB2290413B (en) 1998-04-15

Similar Documents

Publication Publication Date Title
GB2290413A (en) Processing silicon in a plasma etch system
US5354417A (en) Etching MoSi2 using SF6, HBr and O2
KR100515424B1 (en) Anisotropic Plasma Etching Method for Various Substrates
US6303512B1 (en) Anisotropic, fluorine-based plasma etching method for silicon
EP0482519B1 (en) Method of etching oxide materials
Blauw et al. Balancing the etching and passivation in time-multiplexed deep dry etching of silicon
EP1676302B1 (en) Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation
US10580657B2 (en) Device fabrication via pulsed plasma
US6261962B1 (en) Method of surface treatment of semiconductor substrates
JP5207406B2 (en) Plasma processing method
US5498312A (en) Method for anisotropic plasma etching of substrates
JP4601113B2 (en) Anisotropic etching method for substrates
JP3574680B2 (en) Plasma etching using xenon
US6355181B1 (en) Method and apparatus for manufacturing a micromechanical device
EP0814500B1 (en) Method for etching polycide structures
JP2010283362A (en) Etching process for producing silicon having substantially no undercut on insulator structure
JPH06163478A (en) Dry etching method of semiconductor
JPH05308062A (en) Dry etching method
Schwarzenbach et al. High mass positive ions and molecules in capacitively-coupled radio-frequency CF 4 plasmas
US5211804A (en) Method for dry etching
JP2010021442A (en) Plasma processing method and apparatus
US7166536B1 (en) Methods for plasma etching of silicon
Pang et al. Sub‐100‐nm‐wide, deep trenches defined by reactive ion etching
Mieth et al. Anisotropic plasma etching of polysilicon using SF6 and CFCl3
Selamoglu et al. Tapered etching of aluminum with CHF3/Cl2/BCl3 and its impact on step coverage of plasma‐deposited silicon oxide from tetraethoxysilane

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20130612