GB2284912B - Data processor with speculative instruction fetching and method of operation - Google Patents

Data processor with speculative instruction fetching and method of operation

Info

Publication number
GB2284912B
GB2284912B GB9424323A GB9424323A GB2284912B GB 2284912 B GB2284912 B GB 2284912B GB 9424323 A GB9424323 A GB 9424323A GB 9424323 A GB9424323 A GB 9424323A GB 2284912 B GB2284912 B GB 2284912B
Authority
GB
United Kingdom
Prior art keywords
data processor
instruction fetching
speculative instruction
speculative
fetching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9424323A
Other languages
English (en)
Other versions
GB2284912A (en
GB9424323D0 (en
Inventor
Danny K Jain
David S Levitan
Paul C Rossbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of GB9424323D0 publication Critical patent/GB9424323D0/en
Publication of GB2284912A publication Critical patent/GB2284912A/en
Application granted granted Critical
Publication of GB2284912B publication Critical patent/GB2284912B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB9424323A 1993-12-20 1994-12-01 Data processor with speculative instruction fetching and method of operation Expired - Fee Related GB2284912B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16926293A 1993-12-20 1993-12-20

Publications (3)

Publication Number Publication Date
GB9424323D0 GB9424323D0 (en) 1995-01-18
GB2284912A GB2284912A (en) 1995-06-21
GB2284912B true GB2284912B (en) 1998-04-22

Family

ID=22614895

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9424323A Expired - Fee Related GB2284912B (en) 1993-12-20 1994-12-01 Data processor with speculative instruction fetching and method of operation

Country Status (5)

Country Link
US (1) US5553255A (OSRAM)
CN (1) CN1127899A (OSRAM)
GB (1) GB2284912B (OSRAM)
IE (1) IE940855A1 (OSRAM)
TW (1) TW260767B (OSRAM)

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DE69425377T2 (de) * 1994-11-29 2001-02-15 International Business Machines Corp., Armonk Einzel-Zyklus-Prozessor zur Echtzeitsverarbeitung
US5732242A (en) * 1995-03-24 1998-03-24 Silicon Graphics, Inc. Consistently specifying way destinations through prefetching hints
US6185674B1 (en) 1995-04-05 2001-02-06 International Business Machines Corporation Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor
US5774685A (en) * 1995-04-21 1998-06-30 International Business Machines Corporation Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative conditions
US5802346A (en) * 1995-06-02 1998-09-01 International Business Machines Corporation Method and system for minimizing the delay in executing branch-on-register instructions
US5878255A (en) * 1995-06-07 1999-03-02 Advanced Micro Devices, Inc. Update unit for providing a delayed update to a branch prediction array
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5721864A (en) * 1995-09-18 1998-02-24 International Business Machines Corporation Prefetching instructions between caches
US5765208A (en) * 1995-09-29 1998-06-09 Motorola, Inc. Method of speculatively executing store instructions prior to performing snoop operations
US5860150A (en) * 1995-10-06 1999-01-12 International Business Machines Corporation Instruction pre-fetching of a cache line within a processor
US5634103A (en) * 1995-11-09 1997-05-27 International Business Machines Corporation Method and system for minimizing branch misprediction penalties within a processor
US5819080A (en) * 1996-01-02 1998-10-06 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor
US5611063A (en) * 1996-02-06 1997-03-11 International Business Machines Corporation Method for executing speculative load instructions in high-performance processors
US5742791A (en) 1996-02-14 1998-04-21 Advanced Micro Devices, Inc. Apparatus for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor
US5752014A (en) * 1996-04-29 1998-05-12 International Business Machines Corporation Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction
US6170053B1 (en) * 1996-06-27 2001-01-02 Texas Instruments Incorporated Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy
US5949995A (en) * 1996-08-02 1999-09-07 Freeman; Jackie Andrew Programmable branch prediction system and method for inserting prediction operation which is independent of execution of program code
US5832205A (en) * 1996-08-20 1998-11-03 Transmeta Corporation Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed
US6199152B1 (en) 1996-08-22 2001-03-06 Transmeta Corporation Translated memory protection apparatus for an advanced microprocessor
US6871275B1 (en) * 1996-12-12 2005-03-22 Intel Corporation Microprocessor having a branch predictor using speculative branch registers
US5935238A (en) * 1997-06-19 1999-08-10 Sun Microsystems, Inc. Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles
US5964869A (en) * 1997-06-19 1999-10-12 Sun Microsystems, Inc. Instruction fetch mechanism with simultaneous prediction of control-flow instructions
US5958047A (en) * 1997-06-25 1999-09-28 Sun Microsystems, Inc. Method for precise architectural update in an out-of-order processor
US6085305A (en) 1997-06-25 2000-07-04 Sun Microsystems, Inc. Apparatus for precise architectural update in an out-of-order processor
US5838988A (en) * 1997-06-25 1998-11-17 Sun Microsystems, Inc. Computer product for precise architectural update in an out-of-order processor
US5996060A (en) * 1997-09-25 1999-11-30 Technion Research And Development Foundation Ltd. System and method for concurrent processing
US5978909A (en) * 1997-11-26 1999-11-02 Intel Corporation System for speculative branch target prediction having a dynamic prediction history buffer and a static prediction history buffer
US6370415B1 (en) 1998-04-10 2002-04-09 Medi-Physics Inc. Magnetic resonance imaging method
US6012134A (en) * 1998-04-09 2000-01-04 Institute For The Development Of Emerging Architectures, L.L.C. High-performance processor with streaming buffer that facilitates prefetching of instructions
US6032248A (en) * 1998-04-29 2000-02-29 Atmel Corporation Microcontroller including a single memory module having a data memory sector and a code memory sector and supporting simultaneous read/write access to both sectors
JP3439350B2 (ja) * 1998-10-02 2003-08-25 Ｎｅｃエレクトロニクス株式会社 キャッシュ・メモリ制御方法及びキャッシュ・メモリ制御装置
US6560629B1 (en) * 1998-10-30 2003-05-06 Sun Microsystems, Inc. Multi-thread processing
US6880152B1 (en) 1999-10-13 2005-04-12 Transmeta Corporation Method of determining a mode of code generation
US6766442B1 (en) * 2000-03-30 2004-07-20 International Business Machines Corporation Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value
US6678820B1 (en) 2000-03-30 2004-01-13 International Business Machines Corporation Processor and method for separately predicting conditional branches dependent on lock acquisition
US6658558B1 (en) 2000-03-30 2003-12-02 International Business Machines Corporation Branch prediction circuit selector with instruction context related condition type determining
US6859875B1 (en) 2000-06-12 2005-02-22 Freescale Semiconductor, Inc. Processor having selective branch prediction
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
US7107437B1 (en) * 2000-06-30 2006-09-12 Intel Corporation Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB)
KR100518538B1 (ko) * 2002-10-26 2005-10-04 삼성전자주식회사 데이터 독출 동작과 기입 동작을 동시에 수행할 수 있는집적 회로 및 방법.
US6826088B2 (en) * 2002-10-26 2004-11-30 Samsung Electronics Co., Ltd. Method and integrated circuit capable of reading and writing data simultaneously
US7343481B2 (en) * 2003-03-19 2008-03-11 Arm Limited Branch prediction in a data processing system utilizing a cache of previous static predictions
DE602004025913D1 (de) * 2003-03-27 2010-04-22 Nxp Bv Aufzeichnen von aktivität nach sprüngen
US20040225866A1 (en) * 2003-05-06 2004-11-11 Williamson David James Branch prediction in a data processing system
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US8001363B2 (en) * 2005-04-04 2011-08-16 Globalfoundries Inc. System for speculative branch prediction optimization and method thereof
US7437543B2 (en) * 2005-04-19 2008-10-14 International Business Machines Corporation Reducing the fetch time of target instructions of a predicted taken branch instruction
CN100395731C (zh) * 2006-02-23 2008-06-18 华为技术有限公司 处理器及其数据操作方法
US9304773B2 (en) * 2006-03-21 2016-04-05 Freescale Semiconductor, Inc. Data processor having dynamic control of instruction prefetch buffer depth and method therefor
US7627742B2 (en) * 2007-04-10 2009-12-01 International Business Machines Corporation Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system
US8949581B1 (en) * 2011-05-09 2015-02-03 Applied Micro Circuits Corporation Threshold controlled limited out of order load execution
US9182991B2 (en) 2012-02-06 2015-11-10 International Business Machines Corporation Multi-threaded processor instruction balancing through instruction uncertainty
US10585801B2 (en) * 2012-11-26 2020-03-10 Advanced Micro Devices, Inc. Prefetch kernels on a graphics processing unit
US20160350116A1 (en) * 2015-05-29 2016-12-01 Qualcomm Incorporated Mitigating wrong-path effects in branch prediction
US9934041B2 (en) * 2015-07-01 2018-04-03 International Business Machines Corporation Pattern based branch prediction
US10296463B2 (en) * 2016-01-07 2019-05-21 Samsung Electronics Co., Ltd. Instruction prefetcher dynamically controlled by readily available prefetcher accuracy
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Also Published As

Publication number Publication date
TW260767B (OSRAM) 1995-10-21
GB2284912A (en) 1995-06-21
CN1127899A (zh) 1996-07-31
GB9424323D0 (en) 1995-01-18
IE940855A1 (en) 1995-06-28
US5553255A (en) 1996-09-03

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19981201