GB2282940A - A word synchronous system for a word interleave method in a digital communication system - Google Patents

Abstract

A word synchronous system for a word interleave method in a digital communication system includes a line demultiplexing unit 10 that receives a higher order signal HDS for demultiplexing lower order signals DATA-1 to DATA-n therefrom; a window generating unit 12 operatively connected to the line demultiplexing unit 10 for generating windows WNDW-1 to WNDW-n to demultiplex the lower order signals from the higher order signal in the line demultiplexing unit 10; and a plurality of subdemultiplexing units SUB-DMUX1 to SUB-DMUXn operatively connected to the line demultiplexing unit 10 for receiving corresponding lower order signals from the line demultiplexing unit 10 and generating a synchronous signal SYNC to the window generating means; and word synchronous detection means operatively connected to the line demultiplexing means and the window generating means for receiving the higher order signal and generating a detection signal DS to the window generating means. <IMAGE>

Description

A WORD SYNCHRONOUS SYSTEM FOR A WORD INTERLEAVE METHOD IN A DIGITAL COMMUNICATION SYSTEM The present invention relates to a word synchronous system for a word interleave method in a digital communication.

As is well known, there are twmethods, in a digital communication system, i.e., a bit interleave method and a word interleave method. The former means that lower order signals are multiplexed for every bit to form a higher order signal (so-called, bit multiplex). The latter means that the lower order signals are multiplexed for every word to form a higher order signal (so-called, word multiplex).

The present invention is applied to a word interleave method.

In the word interleave method, the lower order signals are multiplexed to the higher order signal in a transmitting side and the higher order signal is sent to a receiving side. In the receiving side, the higher order signal is demultiplexed to the lower order signals.

In the receiving side, it is necessary to obtain word synchronization when demultiplexing the higher order signal. The present invention relates to a word synchronous system for the word interleave method in the reception side.

The object of the present invention is to provide a word synchronous system for a word interleave method enabling high speed word synchronization.

According to the present invention, a word synchronous system for a word interleave method in a digital communication system, comprises: line demultiplexing means receiving a higher order signal (HDS) for demultiplexing lower order signals (DATA-1 to DATA-n) therefrom; window generating means operatively connected to the line demultiplexing means for generating windows (WNDW-1 to WNDW-n) to demultiplex the lower order signals from the higher order signal in the line demultiplexing means; a plurality of sub-demultiplexing means (SUB-DMUX1 to SUB-DMUXN) each operatively connected to the line demultiplexing means for receiving corresponding lower order signals from the line demultiplexing means and each generating a synchronous signal (SYNC) to the window generating means; and word synchronous detection means operatively connected to the line demultiplexing means- and the window generating means for receiving the higher order signal and generating a detection signal (DS) to the window generating means.

In the drawings: Fig. 1 is a view explaining the relationship between lower order signals and a higher order signal in a transmission side; Fig. 2 is a view explaining demultiplex in a reception side; Fig. 3 is a schematic block diagram of a conventional frame synchronous system; Fig. 4 is a timing chart explaining windows generated by the window generator shown in Fig. 3; Fig. 5 is a schematic block diagram of the window generator shown in Fig. 3; Fig. 6 is a basic block diagram of another example of a synchronous system in a conventional art; Fig. 7 is a basic block diagram of a word synchronous system for a word interleave method according to the present invention; Fig. 8 is a detailed block diagram of the example shown in Fig. 7; and Fig. 9 is a signal timing chart in the circuit shown in Fig. 8.

Before describing the preferred embodiments, an explanation will be given of a conventional art.

Figure 1 is a view explaining the relationship between lower order signals and a higher order signal in a transmitting side in a digital communication system. In Fig. 1, "Trib-l" to "Trib-n" denote the lower order signals, and HDS denotes the higher order signal. Further, FAW-l to FAW-n denote frame synchronous words, and DATA-ll to DATA-n3 denote data words. As shown in the drawing, each lower order signal has one frame synchronous word FAW and a plurality of data words DATA.The higher order signal HDS is obtained in such a way that, first, the frame synchronous words FAW-1 to FAW-n of the lower order signals Trib-1 to Trib-n are multiplexed-to a train of the frame synchronous words FAW-1 to FAW-n of the higher order signal HDS, second, the data words DATA-11 to DATA-nl of the lower order signals Trib-l to Trib-n are multiplexed to the train of the data words DATA-11 to DATA-nl of the higher order signal HDS. Similarly, the data words DATA-12 to DATA-n2 and DATA-13 to DATA-n3 of the lower order signals Trib-1 to Trib-n are multiplexed to the train of the data words of he higher order signal HDS, respectively. As a result, the higher order signal HDS is constituted by the frame synchronous words FAW-1 to FAW-n and the data words DATA-11 to DATA-nn.

Figure 2 is a view explaining demultiplex in a reception side. In Fig. 2, WNDW-1 to WNDW-n denote windows for demultiplexing the higher order signal HDS into the data words DATA-11 to DATA-nn of the lower order signals Trib-1 to Trib-n. The window WNDW has the same word width as the word length of the data word DATA. The higher order signal HDS is demultiplexed (i.e., separated) into the data words DATA by the window WNDW. That is, the window WNDW-1 is used for obtaining the data words DATA-li, DATA-12, DATA-ln of the lower order signal Trib-1. Similarly, the window WNDW-2 is used for obtaining the data words DATA-21, DATA-22, ..., DATA-2n of the lower order signal Trib-2, and the window WNDW-n is used for obtaining the data words DATA-nl, DATA-n2, ..., DATA-nn of the lower order signal Trib-2 (see, Fig. 1).The frame synchronous words FAW-1 to FAW-2 are also separated by the window WNDW in each lower order signal Trib-l to Trib-n.

Figure 3 is a schematic block diagram of a conventional frame synchronous system in the reception side. In Fig. 3, reference number 10 denotes a line demultiplexer (LINE-DMUX), 12 denotes a window generator (WNDW-GEN), and SUB-DMUX1 to SUB-DMUXn denote sub-demultiplexers. The sub-demultiplexer SUB-DMUX has a frame synchronous word detection circuit 22, an additional bit separation circuit 24, and -a channel unit 26. All sub-demultiplexers SUB-DMUX2 to SUB-DMUXn have the same structure as the sub-demultiplexer SUB-DMUX1.

The line demultiplexer 10 receives the higher order signals HDS and separates them into the data words DAT -1 to DATA-n of the lower order signals in accordance with the corresponding window WNDW from the window generator 12. The data words DATA-1 to DATA-n correspond to the lower order signals Trib-l to Trib-n shown in Fig. 1. For example, the data word DATA-1 corresponds to the lower order signal Trib-l. The window generator 12 receives clock signals CLK and counts them to generate the windows WNDW-1 to WNDW-n.

The clock signal CLK corresponds to bit clocks generated by a PLL circuit (not shown) based on the higher order signal HDS.

For example, the data word DATA-1 is input to the sub-demultiplexer SUB-DMUX1, and the data word DATA-2 is input to the sub-demultiplexer SUB-DMUX2. Similarly, the data word DATA-n is input to the sub-demultiplexer SUB-DMUXn. The frame synchronous word detection circuit 22 detects the frame synchronous word FAW of the data word DATA and outputs a synchronous signal SYNC indicating a result of the detection (high or low level) to the window generator 12. For example, in the sub-demultiplexer SUB-DMUX1, the frame synchronous word detection circuit 22 detects the frame synchronous word FAW-1 of the data word DATA-1 and outputs the synchronous signal SYNC-1 to the window generator 12.Similarly, in the sub-demultiplexer SUB-DMUXn, the frame synchronous word detection circuit 22 detects the frame synchronous word FAW-n of the data word DATA-n and outputs the synchronous signal SYNC-n to the window generator 12.

The additional bit separation circuit 24 is provided for separating additional bits, for example, frame synchronous words and parity bits from the data word DATA.

Further, the channel unit 26 is provided for smoothing the data word DATA to send to the next stage. The detailed explanations of these units 24 and 26 are omitted in this specification because said circuits do not relate directly to the problems of the conventional art. The lower order signals Trib can be obtained from the sub-demultiplexer SUB-DMUX. These lower order signals Trib-1 to Trib-n at the output of the sub-demultiplexer do not contain the frame synchronous word FAW because the data word DATA is already synchronized with the window WNDW.

Figure 4 is a timing chart for generating the window from the window generator 12. In Fig. 4, "m" is one word length (i.e., one data word DATA has "m" bits). This word length is also equal to the window width. Further, "n" is the number of word multiplexes, "N" is the number of stages (repetition) for establishing synchronous protection.

Usually, N is three times. Still further, "7" is a frame period of the lower order signals. That is, the n "7" is equal to a waiting time for detecting the frame synchronous word FAW until the synchronous protection is established in the frame synchronous word detection circuit 22.

In the first stage (N = 1), when the time "t" is "0" (t = 0), the window is shifted by one bit. After the time t = T, the window is further shifted by one bit. Still further, after the time t = 2T, the window is further shifted by one bit. Accordingly, after the time t = (mn 1) T the first synchronous stage is started so that the first synchronous protection is obtained in the data word DATA-12. Similarly, in the second and third stages (N = 2, 3), the window is shifted in the same way as that of the first stage so that it is possible to establish synchronous protection and obtain a synchronous return.

In the above operation, first, the window WNDW is not synchronized with the synchronous signal SYNC. That is, in Fig. 3, the frame synchronous word detection circuit 22 outputs a low level synchronous signal SYNC (1) to the window generator 12. In this case, the window generator 12 performs an OR operation among synchronous signals SYNC-1 to SYNC-n. When the result of the OR operation is low (i.e., this interval is equal to-the waiting time T), the window is shifted by one bit as explained above.

When the frame synchronous word FAW is synchronized with the window WNDW, the synchronous signal SYNC becomes high (H). When the window generator 12 receives a high level synchronous signal SYNC, the shift operation by the window generator 12 is stopped after N repetition, for example, three times repetition (N = 3).

Figure 5 is a schematic block diagram of the window generator shown in Fig. 3. In Fig. 5, 12a denotes an OR gate having multi-inputs, 12b denotes a shift timing generator, 12c and 12d denote OR gates, 12e denotes a "m x n" dividing circuit, and 12f denotes an edge detector (EDET). The OR gate 12a receives the synchronous signals SYNC-1 to SYNC-n, and outputs the high level signal when any one of synchronous signals SYNC is high. This high level signal is input to the OR gate 12c. The shift timing generator 12b generates a shift timing signal ST having "TN" of one period to shift the window for every one bit.

When the output of the OR gate 12a is high, the OR gate 12c outputs only a high level signal regardless of the level of the shift timing signal ST. Accordingly, the edge detection circuit 12f detects the edge of the high level signal from the output of the OR gate, and outputs the high level signal to the OR gate 12d. The clock signal CLK obtained by the higher order signal HDS is also input to the OR gate 12d. Accordingly, when the high level signal is input to the OR gate 12d, the OR gate 12d outputs only the high level signal regardless of the level of the clock signal CLK so that it is possible to stop the shift operation of the window. Further, the m x n diving circuit 12e counts the number of clocks CLK and outputs windows WNDW-1 to WNDW-n.

When the output of the OR gate 12a is low, the OR gate 12c alternately outputs a high or low level in accordance with the shift timing signal ST. The edge of the shift timing signal ST is always detected by the edge detector 12f. In this case, since the shift timing signal ST is generated by the shift timing generator 12b based on the period "rN", the edge detection circuit 12e generates the edge signal in the timing of the "7N". Accordingly, the clock signal CLK is inhibited by the edge detection signal in the timing of the "7N" so that the window can be shifted by one bit.

In the above conventional art shown in Fig. 3, the frame synchronous word detection circuit 22 is provided for the lower order signals. Further, the window WNDW is sequentially shifted by one bit until the window WNDW is synchronized with the data word DATA. Accordingly, as explained in Fig. 4, much waiting time "T" is necessary to obtain synchronization in the frame synchronous word detection circuit 22. As the worst case, the time (mn-l)TN is necessary as the waiting time in the frame synchronous word detection circuit 22.

Figure 6 is another example of a synchronous system for a word interleave method. This structure is used to explain the present invention. In Fig. 6, reference number 12f denotes a majority decision circuit. The majority decision circuit 12f performs the decision by majority among the synchronous signals SYNC-1 to SYNC-n, and the result of the majority is output to the OR gate 12c.

In this case, synchronous protection is not necessary for the frame synchronous word detection circuit 22 (i.e., number of repetition N = 1). That is, when the frame synchronous word FAW is detected, the synchronous signal SYNC is set at a high level. When the number of high level synchronous signals SYNC is more than that of low level signals, the majority decision circuit 12f outputs an inhibit signal "inh" to the OR gate 12c so that the bit shift operation in the window WNDW is stopped in accordance with the inhibit signal "inh" as explained in Fig. 5.

According to this structure, it is pos.sible to quickly obtain synchronous protection compared with the conventional art shown in Fig. 3, because synchronous protection is not necessary.

In our co-pending application GB-A-2250896 from which this application is divided, a system is disclosed in which the demultiplexed lower order signals are used fro synchronization at higher speed than in the prior art.

The present invention is explained in detail hereinafter. The same reference numbers as used in Figs. 1 to 6 are attached to similar components in the following drawings.

Figure 7 is a basic block diagram of a word synchronous system for a word interleave method according to the present invention. In Fig. 7, reference number 14 denotes a word synchronous detection unit that detects the data word DATA in the higher order signal HDS. In the present invention, the word synchronous detection is performed for the higher order signal HDS. The detection signal DS at the word synchronous detection circuit 14 is input to the window generator 12 to control the bit shift and to generate the window WNDW-1 to WNDW-n synchronized with the word. After this synchronization, the frame synchronous word FAW is detected from the lower order signals extracted by this window. Further, the bits are shifted in accordance with the synchronous signals SYNC-1 to SYNC-n to synchronize the window with the frame.

As explained above, the word synchronous detection unit 14 is provided for the side of the higher order signal HDS. After word synchronization is established in the side of the higher order signal HDS, the frame synchronization is established in the side of the lower order signals Trib.

The higher order signal HDS is input to the word synchronous detection unit 14. The window WNDW is shifted by one bit in response to the output of the word synchronous detection unit 14 so that word synchronization is established.

In the present invention, it is possible to quickly establish synchronous protection compared with the conventional art. That is, the word detection is performed from the higher order signal HDS; the bits are shifted in response to the detected signals, and the word is synchronized with the word. After this synchronization, the bits are shifted by the synchronous signals SYNC-1 to SYNC-n so that the windows are synchronized with the word.

Figure 8 is a detailed block diagram of the present invention as shown in Fig. 7, and Figure 9 is a signal timing chart in the circuit shown in Fig. 8. In Fig. 8, reference number 14a denotes a"1/2" dividing circuit, 14b denotes a twenty-five bits shift register, 14c denotes an inhibit gate, 14d denotes a "1/25" dividing circuit, 14e denotes an exclusive OR gate, 14f denotes a register for synchronous protection, and 14g denotes an OR gate. In this case, twenty-five bits are constituted by twenty-four bits plus one parity bit.

As shown in Fig. 9, according to a code rule of "24 bit plus one parity bit" (i.e., code rule of 24 B-1-P), since the number of "1" of each parity block is an even number, when the exclusive OR operation is performed between the higher order signal HDS and the data bit obtained by a 1/2 dividing operation from the higher order signal and shifted by 25 bits, the input signals coincide with each other (H and H, or L and L) for every 25 bits so that the exclusive OR gate 14e outputs a low level. As another case, in some kinds of data patterns, since the output of the exclusive OR gate becomes low, it is necessary to perform synchronous protection. This synchronous protection is performed by the shift register 14f and the OR gate 14g. The output of the 1/2 dividing circuit 14a is sent to the 25 bits shift register 14b in response to the clock signal CLK of the higher order signal HDS.Further, the output of the 1/25 dividing circuit 14d is sent to the synchronous protection register 14f.

When word synchronization is established, the output of the exclusive OR gate 14e becomes low for every 25 bits and this low level is input to the register 14f.

Accordingly, the outputs Q0, Q1 , of the register 14f becomes low, and the output of the OR gate 14g becomes low.

This low level from the OR gate 14g is input to the inhibit gate 14c so that the inhibit gate 14c does not inhibit the clock CLK.

When word synchronization is not established, the output of the exclusive OR gate 14e becomes low or high for every 25 bits. Accordingly, the output of the OR gate 14g changes between a low and high level. Since this low or high level is input to the inhibit gate 14c, the inhibit gate 14c inhibits one clock of the clock signal CLK at every 25 bits so that it is possible to shift the window by one bit.

Claims (2)

1. A word synchronous system for a word interleave method in a digital communication system, said word synchronous system comprising: line demultiplexing means (10) receiving a higher order signal (HDS) for demultiplexing lower order signals (DATA-1 to DATA-n) therefrom; window generating means (12) operatively connected to the line demultiplexing means for generating windows (WNDW-1 to WNDW-n) to demultiplex the lower order signals from the higher order signal in the line demultiplexing means; a plurality of sub-demultiplexing means (SUB-DMUX1 to SUB-DMUXN) each operatively connected to the line demultiplexing means for receiving corresponding lower order signals from the line demultiplexing means and each generating a synchronous signal (SYNC) to the window generating means; and word synchronous detection means operatively connected to the line demultiplexing means and the window generating means for receiving the higher order signal and generating a detection signal (DS) to the window generating means.

2. A word synchronous digital communication system substantially as described with reference to Figures 7 to 9 of the accompanying drawings.