GB2281814A - Film carrier with interconnections for I.C. chips - Google Patents
Film carrier with interconnections for I.C. chips Download PDFInfo
- Publication number
- GB2281814A GB2281814A GB9417926A GB9417926A GB2281814A GB 2281814 A GB2281814 A GB 2281814A GB 9417926 A GB9417926 A GB 9417926A GB 9417926 A GB9417926 A GB 9417926A GB 2281814 A GB2281814 A GB 2281814A
- Authority
- GB
- United Kingdom
- Prior art keywords
- die
- interconnection
- polyimide
- polymer film
- conducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract
A plurality of integrated circuit chips 1 each has one or more interconnection pads 2 disposed thereon. A polymer film 4 overlies the integrated circuits 1 and has a plurality of via openings 7 therein. Some of the via openings 7 are aligned with at least some of the interconnection pads 2. A pattern of interconnection conductors 5 disposed on one side of the polymer film 4 connects at least some of the via openings 7, and a conducting substance 8 connects at least some the interconnection conductors 5 to at least some of the interconnection pads 2. The polymer film acts as the sole mounting substrate for the chips. <IMAGE>
Description
INTERCONNECTION STRUCTURE
The invention relates to a method of mounting semiconductor die onto a substrate, and thereby producing multiple simultaneous connections between the semiconductor die and the substrate.
The present invention is applicable in particular, though not exclusively, to bonding of silicon die.
A silicon die is a monolithic microcircuit fabricated using geometries in the region of a micron (one millionth of a metre). In contrast, the smallest features on a circuit board connecting multiple die is of the order of hundreds of microns. To connect a silicon die to other electronic components, including other die, this disparity in size between the die and the circuit board is overcome by fanning out the connections from a silicon die to large bonding pads. The bonding pads are then connected to a chip carrier package which, in turn, is connected to a circuit board. Wire bond or tape automated bonding methods are used to make interconnections from the pads of the chip to the pins of the package.
In packaging VLSI (Very Large Scale Integrated) circuit devices a large percentage of the space needed for the device is taken up with interconnecting the semiconductor die to the rest of the circuit. Advances made in decreasing the size of integrated circuits cannot be exploited fully because of the large area wasted on interconnections. If the bond pads of a semiconductor die could be connected to a circuit board directly, without fanning out the connections, then less circuit board space would be wasted. A large number of solutions have been proposed to overcome the problem of connecting the bonding pads of a silicon die directly to a circuit board.
Chip On Board (COB) uses fine line lithography to integrate the carrier onto the circuit board. The silicon die is then fixed to the circuit board directly, with the bonding pads connected by a wire bonder using ultrasonic, pressure gold ball or thermal techniques. The disadvantages associated with this method include a poor yield and a significantly larger board area is required for COB than for the die-alone.
Flip Chip technology relates to chips that have their top surface connected to a circuit board. One type of Flip Chip technology has a metal ball placed on each pad of the die, the die is then inverted and positioned over matching metallic fingers on the circuit board. The bond is made by exerting pressure on the die, causing the metal ball on the pads to collapse.
Most Flip Chip systems use more than one metal in the ball. The metals are chosen such that the collapsed balls form a Eutectic joint. The main disadvantage associated with this process is that it is unreliable, so there is a poor yield of correctly bonded die. A typical process involving Flip Chip technology is described in EPA-0522593.
Tape Automated Bonding is another common chip connection technique. In this process a die is connected to a film, (in the form of a tape) usually polyimide, onto which has been deposited a wiring pattern. The film is punched out at the time of board assembly to form a carrier linking the die to the circuit board. To bond the die to the film, metallic bumps are formed on the pad sites of the chip to allow an electrical connection between the die and film to be achieved by thermocompression bonding. It is possible to use the Tape
Automated Bonding process to interconnect multiple die, but such a process would be serial in nature, in contrast to the novel process described herein where the majority of pads are connected simultaneously to multiple die.
Anisotropic bonding is a process which uses a sheet of anisotropically conductive material sandwiched between a die and circuit board, as described by EPA-0521672. This process suffers from problems with semiconductor chemistry, particularly oxidation of the lands and maintaining contact with the die.
The process described herein is similar in some ways to Flip Chip technology. However, the present invention is novel in that a multiplicity of electrical connections are formed simultaneously between the pads of multiple semiconductor die and a flexible substrate, the substrate itself providing the interconnection paths. An application of the process is the interconnection of multiple silicon die on a single polymer layer to achieve a high die density on a circuit board, whilst maintaining an adequate yield.
US patent number 4783 695 describes a method of bonding semiconductor die to a polymer film containing an interconnecting metallization layer. That patent uses a polymer film to cover a plurality of integrated circuit chips adjacent to one another on an underlying substrate. The present invention is similar to US patent number 4783 695 in that a polymer layer containing interconnection paths is bonded to the semiconductor die. However, the present invention is different to US patent number 4 783 695 in that the polymer layer which provides the interconnection also fimotions as the substrate. There is no additional substrate in this invention.
European patent application EP 465 195 discloses a method of interconnecting integrated circuits using multiple laminated dielectric layers. Again, EP 465 195 assumes that the polymer layer serves as an interconnecting path; whereas, in the present invention the polymer serves as both interconnecting path and substrate. The present invention, though similar to both EP 465 195 and US 4783 695, differs in that one component in these inventions has been omitted entirely, namely the substrate, because the present invention performs an entirely different function to the inventions previously referred to.
One advantage of the present invention is that once the polymer has semiconductor die bonded to it then the assembled unit may be folded because the polymer is flexible. Thus the flexible circuit can be manipulated to occupy less surface area than previously and then mounted onto a circuit board or other device.
Another advantage of the present invention is that semiconductor die are bonded directly to a substrate (the polymer) and so the overall circuit is thinner than if packaged integrated circuits were used.
Yet another advantage of the present invention is that a greater density of integrated circuits can be located on the polymer than if packaged integrated circuits were used.
It is an object of the present invention to provide a direct interconnection between integrated circuit die by means of a single, flexible insulating substrate containing a network of conducting paths.
It is another object of the present invention to provide interconnections between integrated circuits with minimum wasted space due to fanning out of connections.
It is another object of the present invention to provide a polymer film which acts as both an interconnecting layer and a substrate to hold integrated circuits.
The substance of this invention is an insulating polymer which functions as a substrate and contains conducting paths providing connections between bond pads of semiconductor die connected to the substrate.
Thus the present invention is an interconnecting structure formed by a multiple bonding process which involves: making perforations in a thin insulating substance; aligning one or more of the bond pads on one or more of the semiconductor die to said thin, perforated insulating substance; attaching said die to said substance; forming one or more electrically conducting paths in said substance; and forming electrical connections between at least one bond pad on said die and one of said conducting paths.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality, to the accompanying drawings forming Figure 1 and Figure 2, in which:
Figure 1A is a side elevation view showing the polyimide clad with a layer of metal on each side and perforations in the metal and polyimide. The polyimide material is held in ajig.
Figure 1B is a side elevation view showing the structure of Figure 1A with the two metal layers patterned to form interconnection between the perforations.
Figure 1C is a plan view of Figure 1B showing an interconnection pattern etched on the top layer of metal deposited on the polyimide.
Figure 1D is a side elevation view showing the structure of Figure 1B with die aligned.
Figure 1E is a side elevation showing the structure of Figure 1D with the die bonded.
Figure 1F is a side showing the structure of Figure 1E with an insulating coating on one of the metal layers.
Figure 1G is a side elevation showing the complete structure of the assembly fabricated using the process described, and
Figure 2 shows a pictorial representation of an alignment station for mounting semiconductor die.
The invention will be described in terms of a number of processing steps. The application of these processing steps results in an assembly composed of silicon die connected to a wiring layer on a flexible circuit board. The steps listed below represent the preferred method of manufacturing the assembly and are given by way of example. However, the processing steps do not have to be performed in the order stated.
In this embodiment of the present invention the semiconductor die are silicon die containing interconnection pads for connecting to other die, components or even other parts of the same die.
Figure 1G shows two die 1 which have bond pads 2 on one surface, the remainder of said surface is covered with a protective layer 3, usually glass. The die are attached to a thin, insulating polymer 4 which has two layers of patterned conducting tracks on it. The side of the polymer 4 next to the die 1 has a layer of conducting material 5 between the die 1 and the polymer 4. The side of the polymer 4 which is not connected to the die 1 also has a layer of conducting material 6 patterned onto it. The polymer 4 contains via openings (perforations) 7 which are filled with a conducting substance 8. An optional insulating coating 9 is shown on the opposite side of the polymer 4 to the die 1. The polymer 4 is held at each end by ajig 10. The substrate of the die 1 is grounded by a wire 11 which connects the substrate of the die 1 to the top conducting layer 5.
Figure 1G shows two semiconductor die with two bond pads on each die, but only for ease of viewing. Obviously, more or less than two semiconductor die could be used, and each die could have more or less than two bond pads. It is not necessary to have the same number of bond pads on each die.
Suitable materials for the thin, insulating polymer film 4 include polyimides, polyamides, polyaralimide, and PolyTetraFluoroEthelyne (PTFE), as determined by the needs of the eventual application. Preferably the polymer material 4 is chosen to match the thermal characteristics of the die 1 so as to minimise the difference between the thermal expansion coefficients of the material 4 and the die 1. In this embodiment, polyimide is the polymer which is used.
Figure 1A shows a perforated polyimide film. A perforation 7 is made at each location at which a bond to the silicon die 1 is to be made. Additional perforations to connect layers of conducting paths within the polyimide material may also be made. The perforations could be made by a number of techniques including: liquid chemical etching, plasma etching, ion beam etching, laser ablation, ultra-fine mechanical drilling or a combination of these techniques. The perforations are located in such a way that at least one perforation corresponds to one of the interconnection pads on the silicon die 1. It may be desirable to use a thin (30clam) polymer (such as polyimide) layer.
Locating the perforations could be done using standard lithography techniques to pattern the polyimide 4 surface leaving areas exposed corresponding to desired locations for perforations, and areas covered with resist corresponding to areas which are not to be etched. Radiation-sensitive resist would be applied to the polymer (by spinning or spraying, whichever is more convenient) and exposed by the appropriate type of radiation for that resist. The lithography mask could be glass, chrome, or any other suitable, convenient material. The lithography mask contains transparent and opaque areas. For positive resist processes, the transparent areas correspond to the areas of the silicon die 1 containing bond pads which are to be bonded and any other interconnecting vias. For negative resist processes, the opaque areas correspond to the areas of the silicon die 1 which contain bond pads which are to be bonded and any other interconnecting vias. The resist mask could be used as an etch mask during plasma etching or if it was not robust enough to withstand the etching stage then a lift-off processing step could be performed. A. suitable material for the lift-off process is a mixture of Strontium Fluoride and Aluminium Fluoride (92% SrF2 and 8% Al2F3), which is easily removed after etching in a weak solution of hydrochloric acid.
The next stage in the manufacturing process is to make a network of conducting paths on the polyimide 4, usually on the side of the polyimide 4 opposite to the die, but in some cases conducting tracks may be patterned on both sides of the polyimide 4. This stage could be performed at the start of the manufacturing process or at any other convenient stage, it is performed at this stage in the example embodiment only because it is convenient to do so.
Figure 1B shows an elevation of the polyimide covered with conducting tracks, and Figure 1C shows a plan view of the same structure. There are two possible ways of delineating conducting tracks. One of these ways uses a polyimide 4 film which is coated on one or both sides with a conducting material, for example KAPTONN polyimide coated with a thin (25m) layer of copper. The conducting material is then selectively etched to leave the desired interconnect paths. The other way uses a layer of polyimide 4 which has no conducting material on it initially, but onto which is evaporated or sputtered a layer of conducting material. The polyimide 4 may be masked during the evaporation or sputtering process to produce the correct interconnection paths, or the conducting material may be selectively etched to produce the correct network of conducting paths.
The silicon die 1 must be aligned to the perforations 7 in the polyimide film 4, as shown in
Figure 1D. This could be done in a number of ways, either manually or electronically with the aid of a microscope or camera and a moveable stage. Preferably, the die 1 are aligned in their final position by the use of the apparatus shown in Figure 2.
Figure 2 shows a fixture 12 containing an optical assembly to allow the die 1 to be accessed from above for positioning purposes, whilst their alignment is checked from below. One possible optical assembly comprises a magnifying lens 13 with a deep field and an electronic video camera 14. The video camera 14 is connected to suitable automation equipment (such as a vacuum pick-up probe) 15, via a microcontroller 16 and control lines 17.
Where manual alignment is to be used, a video monitor would be included in the apparatus and movement of the stage would be done by an operative.
There are two ways of aligning the die 1 with the polyimide 4. The first is to fix the die 1 and move the polyimide 4. The second is to fix the polyimide 4 and move the die 1.
If the polyimide 4 is to be moved to effect alignment, then during this stage of processing it might be advantageous to fix the die 1 to a plinth temporarily to ease alignment and minimise movement of the die 1. The die l would be fixed by some easily removable adhesive such as BOSTIKTM, which can be dissolved in acetone.
If the die 1 are to be moved to effect alignment, then this may be accomplished by use of a vacuum pickup probe, such as is used to grasp die or surface mount components. A stencil could be used to aid placement and alignment of the die. The polyimide 4 would be held motionless to allow the die to be dropped through holes in the stencil into predetermined positions. Suitable stencil materials include thin nickel or brass. If a stencil is used to align the die then it may be removed once the die have been fixed to the polyimide 4.
At any of the ensuing steps of the process, it may be advantageous to clamp or seal the assembly (comprising the polymer and die) into a housing such that the surface on which the die are mounted is sealed to prevent chemical activity or moisture ingress.
If the substrate is flexible, which is the case with polyimides, then an additional clamping frame 10 may be used to ensure that during the subsequent deposition stage a flat surface is presented. The important consideration is that the jig 10 must not stretch the polyimide film 4 as this might cause misalignment of the perforations in the film with the bond pads 2 of the silicon die 1, and thus ruin alignment.
Once the silicon die 1 and polyimide film 4 are aligned they must be stuck together. This could be done using adhesive on the polyimide 4, the die 1 or both. Suitable means for applying the adhesive include silk screen printing, syringe dispensers and sprays using stencils. The adhesive can be cured by the appropriate method (for example using ultraviolet radiation, thermal profile or chemical accelerator) once alignment has been achieved.
However, there is a major disadvantage associated with using adhesive. Any adhesive layer has a finite (and often relatively large) thickness that has the effect of introducing a gap between the die 1 and the polyimide layer 4. The reason that this gap is so undesirable is that it makes it much more difficult to connect the conducting tracks 5 and 6 on the polyimide with the bond pads 2 on the silicon die 1. Since the bond pads 2 on the silicon die 1 are not flush with the top of the die 1 but are submerged, any increase in the distance between the polyimide layer 4 and the bond pads 2 on the die 1 greatly increases the difficulty in forming a conducting path 8 between the two. An alternative method of joining the polyimide layer and the silicon die is to use a heat/vacuum/pressure/cure approach, similar to the one described in US patent number 4 933 042. There are a number of variations to this approach, any one of which would be suitable for the purposes of the present invention. One such approach involves the use of a vacuum bag into which is placed the polyimide and the die. The bag is evacuated and placed in an oven where the polyimide fuses to the die. Another approach is the standard press lamination. In this technique, two heated platens force the polyimide and die together. The most suitable methods of joining the polyimide layer 4 and the silicon die 1 are based on the heat and pressure approach to provide a close fit with no appreciable gap between the die 1 and the polyimide layer 4
One advantage of using a polyimide layer 4 next to the die 1 is that the polyimide 4 will expand or contract as the silicon die 1 heats up and cools down, thus the difference in thermal coefficient of expansion between the die 1 and the polyimide 4 can be compensated by the flexibility of the polyimide 4.
Connections 8 between the conducting paths 5 and 6 on the polyimide 4 and the corresponding bond pads 2 on the silicon die 1 can be formed by a number of different methods. Figure 1E shows the result of such a connection process. One of these methods is to evaporate a conducting solid onto the polyimide and die unit. Another method is to sputter a conducting solid onto the polyimide and die unit. One disadvantage of these approaches is the need to evaporate a large quantity of solid to make the connection, especially if the polyimide 4 is quite thick. Another disadvantage is the possibility of a shadowing effect occurring during evaporation/sputtering which might lead to a poor connection between the conducting layer on the polyimide 4 and the bond pad 2. A further disadvantage is the need to mask the polyimide 4 carefully during evaporation/sputtering to avoid the evaporated/sputtered substance from covering the polyimide 4. If the polyimide 4 was not masked during evaporation/sputtering then an etching step would be needed to recover the network of conducting paths.
Another method of producing conducting paths is a chemical means, such as electroless copper deposition.
A preferred approach, which can only be successfully used if there is a good seal between the polyimide 4 film and the silicon die 1, is to silk-screen print a conducting paste and then cure it by the appropriate method, for example using heat, ultra-violet radiation, or a chemical accelerator. Adequate material must be deposited onto the pads in a directional fashion so that any space between the pad and the substrate is occupied by conductive material.
Further plating of the conducting connections between the bond pads 2 of the die 1 and the polyimide 4 may be performed to provide stronger electrical or mechanical connections.
Where the conductive material deposited is prone to electrolytic action with the aluminium on the pads of the die, multiple deposition stages may be required. For example, the aluminium pad electrodes may be palladium activated, followed by Ni-P electroless plating, then by Sn/Pb. Other suitable processes include but are not limited to those finishing in gold, silver or copper electroless plating.
Where the deposition of a conductive layer does not involve an inherent lithography, such as in silk-screen printing via a mesh or stencil, excess deposited material may be removed by selective etching. An example of how this could be done is by applying photoresist, exposing to UV (ultra-violet) radiation, developing the resist, etching what is not masked by the resist, and cleaning the assembly.
The assembly is now a polyimide 4 substrate onto which has been mounted silicon die 1, connected via micro perforations 7 to a wiring layer 5 on the same side of the polyimide 4 as the die 1. Where the polyimide 4 includes internal wiring layers, or wiring layers on the side of the polyimide 4 opposite to the die 1, the deposition of conductive material onto the pads will also make contact where required with these wiring layers.
The conducting layer on the assembly may be coated with an insulating material, as shown in Figure 1F.
Connections to the crystalline rear face of the silicon die 1, where required, may be carried out either before or after deposition or silk-screen printing of conducting paste. These connections could be formed using any conventional bonding technique or any other convenient technology. Suitable connection methods include: evaporation of conductive material, conductive adhesives and paints; soldering; brazing and mechanical contact methods. On some silicon semiconductor processes, connection to the bulk of the die may be made by a special mask pattern to allow the die bulk connection to be made in the same manner and simultaneously with all other bonds to the die. Another possible technique mirrors COB technology. A wire is connected from the back face of the die 1 to the polyimide 4.
The assembly may now have a conformal coating applied using an insulating material. This coating is to prevent degradation of the bonds through the perforations 7 in the polyimide 4.
Suitable coating methods include dry-film or wet solder resist methods, such as those common in the manufacture of printed circuit boards.
It will be appreciated that various modifications may be made to the above embodiment within the scope of the present invention.
Claims (12)
1 An interconnection structure comprising: a first plurality of integrated circuit chips, each having a second plurality of interconnection pads disposed thereon; a polymer film overlying said integrated circuits; said polymer film having a third plurality of via openings therein; some of said third plurality of via openings being aligned with at least some of said second plurality of interconnection pads; a pattern of interconnection conductors disposed on one side of said polymer film so as to connect at least some of said third plurality of via openings; and a conducting substance to connect at least some of said interconnection conductors to at least some of said interconnection pads; the structure being characterised in that said polymer film serves as both an interconnection layer and a substrate to hold said integrated circuits.
2 An interconnection structure according to claim 1, where a pattern of interconnection conductors is also disposed on a second side of said polymer film.
3 An interconnection structure according to any preceding claim where the polymer film is flexible.
4 An interconnection structure according to any preceding claim where the pattern of interconnection conductors disposed oh the polymer film is separated from said polymer film by a spacer layer.
5 An interconnection structure according to any preceding claim where a conformal coating is applied to the assembly.
6 An interconnection structure according to any preceding claim where the polymer film is less than approximately 3011m thick.
7 An interconnection structure according to any preceding claim where a second surface of one or more of said integrated circuits is electrically connected to one or more of said interconnection conductors disposed on said polymer film.
8 An interconnection structure according to claim 7 where said second surface is opposite the surface on which interconnection pads are disposed.
9 An interconnection structure according to any preceding claim where said conducting substance is a conducting paste.
10 An interconnection structure according to any one of claims 1 to 8 where said conducting substance is a conducting adhesive.
11 An interconnection structure according to any one of claims 1 to 8 where said conducting substance is a conducting paint.
12 An interconnection structure substantially as hereinbefore described with reference to
Figures 1 and 2 of the accompanying drawing.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB939318573A GB9318573D0 (en) | 1993-09-08 | 1993-09-08 | Bonding process for producing multiple simultaneous connections between silicon di and a substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9417926D0 GB9417926D0 (en) | 1994-10-26 |
GB2281814A true GB2281814A (en) | 1995-03-15 |
Family
ID=10741667
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB939318573A Pending GB9318573D0 (en) | 1993-09-08 | 1993-09-08 | Bonding process for producing multiple simultaneous connections between silicon di and a substrate |
GB9417926A Withdrawn GB2281814A (en) | 1993-09-08 | 1994-09-06 | Film carrier with interconnections for I.C. chips |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB939318573A Pending GB9318573D0 (en) | 1993-09-08 | 1993-09-08 | Bonding process for producing multiple simultaneous connections between silicon di and a substrate |
Country Status (1)
Country | Link |
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GB (2) | GB9318573D0 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0707340A3 (en) * | 1994-10-11 | 1997-06-04 | Martin Marietta Corp | Fabrication and structures of circuit modules with flexible interconnect layers |
EP3038145A3 (en) * | 2014-12-23 | 2016-07-06 | General Electric Company | Electronic packages with pre-defined via patterns and methods of making and using the same |
Citations (5)
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GB2137805A (en) * | 1982-11-19 | 1984-10-10 | Stanley Bracey | Chip Carrier |
EP0343400A2 (en) * | 1988-05-26 | 1989-11-29 | International Business Machines Corporation | Electronic package assembly with flexible carrier and method of making it |
EP0368262A2 (en) * | 1988-11-09 | 1990-05-16 | Nitto Denko Corporation | Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device |
EP0482940A1 (en) * | 1990-10-24 | 1992-04-29 | Nec Corporation | Method of forming an electrical connection for an integrated circuit |
EP0527044A1 (en) * | 1991-08-05 | 1993-02-10 | International Business Machines Corporation | Memory package |
-
1993
- 1993-09-08 GB GB939318573A patent/GB9318573D0/en active Pending
-
1994
- 1994-09-06 GB GB9417926A patent/GB2281814A/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2137805A (en) * | 1982-11-19 | 1984-10-10 | Stanley Bracey | Chip Carrier |
EP0343400A2 (en) * | 1988-05-26 | 1989-11-29 | International Business Machines Corporation | Electronic package assembly with flexible carrier and method of making it |
EP0368262A2 (en) * | 1988-11-09 | 1990-05-16 | Nitto Denko Corporation | Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device |
EP0482940A1 (en) * | 1990-10-24 | 1992-04-29 | Nec Corporation | Method of forming an electrical connection for an integrated circuit |
EP0527044A1 (en) * | 1991-08-05 | 1993-02-10 | International Business Machines Corporation | Memory package |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0707340A3 (en) * | 1994-10-11 | 1997-06-04 | Martin Marietta Corp | Fabrication and structures of circuit modules with flexible interconnect layers |
EP3038145A3 (en) * | 2014-12-23 | 2016-07-06 | General Electric Company | Electronic packages with pre-defined via patterns and methods of making and using the same |
CN105789171A (en) * | 2014-12-23 | 2016-07-20 | 通用电气公司 | Electronic packages with pre-defined via patterns and method of making and using the same |
US10141251B2 (en) | 2014-12-23 | 2018-11-27 | General Electric Company | Electronic packages with pre-defined via patterns and methods of making and using the same |
CN105789171B (en) * | 2014-12-23 | 2020-02-21 | 通用电气公司 | Electronic packages with predefined via patterns and methods of making and using the same |
Also Published As
Publication number | Publication date |
---|---|
GB9318573D0 (en) | 1993-10-27 |
GB9417926D0 (en) | 1994-10-26 |
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