GB2276491A - Multilayered connections for intergrated circuits - Google Patents
Multilayered connections for intergrated circuits Download PDFInfo
- Publication number
- GB2276491A GB2276491A GB9306392A GB9306392A GB2276491A GB 2276491 A GB2276491 A GB 2276491A GB 9306392 A GB9306392 A GB 9306392A GB 9306392 A GB9306392 A GB 9306392A GB 2276491 A GB2276491 A GB 2276491A
- Authority
- GB
- United Kingdom
- Prior art keywords
- conductor
- conductor layer
- layer
- pad regions
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/467—Adding a circuit layer by thin film methods
Abstract
A hybrid integrated circuit device comprises a substrate 10, a first conductor layer 20 formed over a surface of the substrate and comprising a plurality of relatively narrow conductor tracks having enlarged pad regions, an insulating layer 30 having openings 32 corresponding to the pad regions, and a second conductor layer 40 comprises a plurality of relatively wide conductor tracks 42 connecting with the pad regions of the conductor layer 20 through the openings in the insulating layer 30. The first and second layers may be of aluminium applied respectively by thin and thick film techniques e.g. spattering. <IMAGE>
Description
Hybrid Integrated Circuit Device
This invention relates to a hybrid integrated circuit device.
Various forms of multi-layer substrates are known, providing conductive interconnections between electronic circuits. For example, thin film processes are used to produce substrates having high densities of conductor tracks, each track being typically 30m or less in width: however after the first conductor layer has been formed, each subsequent layer requires very accurate alignment with the preceding layer to ensure correct positioning of the interconnections between layers; optical alignment techniques are used, but these require expensive equipment and are time consuming to perform.
Thick film processes may instead be used to produce multi-layer substrates: in these, the conductor tracks are much wider (typically 250ism) and of correspondingly lower track densities; however, alignment between layers is much easier to achieve because of the wider conductor tracks, and simple mechanical alignment techniques are sufficiently accurate.
Thin film hybrids find applications where very complex interconnections are required, for example in aerospace and computer industries. In less demanding technologies, thick film hybrids are more suitable because of the lower costs of manufacturing.
However, a problem is developing with thick film hybrids, in that the number of layers required is increasing as the circuits become more complex.
In accordance with this invention, there is provided a hybrid integrated circuit device comprising a substrate, a first conductor layer formed over a surface of the substrate and comprising a plurality of relatively narrow conductor tracks having enlarged pad regions, an insulating layer formed over said first conductor layer and having openings therein corresponding to said pad regions, and a second conductor layer formed over said insulating layer and comprising a plurality of relatively wide conductor tracks connecting with said pad regions through said openings.
The device preferably comprises one or more further conductor layers each comprising a plurality of relatively wide conductor tracks which interconnect with the conductor tracks of the preceding conductor layer through openings in an intervening insulating layer.
The first conductor layer may be formed by conventional thin film techniques: because it is the first layer, it does not require any accurate alignment upon the substrate surface.
The conductors of this thin film layer may be of slightly lower density than in normal thin film conductor layers, to accommodate the enlarged pad regions. The second (and any subsequent) conductor layers may be formed by conventional thick film techniques: each such layer can be aligned, relative to the tracks of the preceding conductor layer, by simple and inexpensive mechanical techniques known in the art, because of the relatively large size of the elements being aligned.
It will be appreciated that a typical device in accordance with this invention will have a relatively high density of conductive tracks in the first (thin film) conductor layer and a higher power carrying capability in the second (thick film) conductor layer: because of the large number of conductor tracks in the first conductor layer, the device can include a greater number of tracks than an equivalent two-layer thick film device, but can be produced at similar relatively low cost.
Also in accordance with this invention, there is provided a method of manufacturing a hybrid integrated circuit device, comprising forming a first conductor layer over a surface of a substrate, the first conductor layer comprising a plurality of relatively narrow conductor tracks having enlarged pad regions, forming an insulating layer over said first conductor layer, said insulating layer being formed with openings therein corresponding to said pad regions, and forming a second conductor layer over said insulating layer, said second conductor layer comprising a plurality of relatively wide conductor tracks connecting with said pad regions through said openings.
An embodiment of this invention will now be described by way of example only and with reference to the accompanying drawings, in which:
FIGURE 1 is an enlarged, diagrammatic cross-section through a hybrid device in accordance with this invention;
FIGURE 2 is a partial plan view of a first conductor layer formed on the substrate of the device of Figure 1;
FIGURE 3 is a partial plan view of an insulating layer formed over the first conductor layer of Figure 2; and
FIGURE 4 is a partial plan view of a second conductor layer formed over the insulating layer of Figure 3.
Referring to Figure 1 of the drawings, there is shown a hybrid integrated circuit device in accordance with this invention, comprising a silicon wafer or substrate 10, a first conductor layer 20 formed over a surface of the substrate, then an insulating layer 30, a second conductor layer 40 and finally a passivation layer 50 (which may be omitted for certain applications).
As shown in Figure 2, the first conductor layer 20 comprises a plurality of relatively high density conductor tracks and having enlarged pad regions 24: typically these conductor tracks may be 5 to 504m wide and spaced apart by a similar amount; the enlarged pad regions may be 170 to 250m across and may be square or circular, for example. The first conductor layer 20 is formed on the substrate 10 by conventional thin film techniques.
As shown in Figure 3, the insulating layer 30 is formed with openings or vias 32 corresponding in size and shape to the enlarged pad regions 24 of the first conductor layer. As shown in Figure 4, the second conductor layer 40 comprises a plurality of relatively wide conductor tracks 42 which connect with the pad regions 24 through the openings or vias 32 in the insulating layer. Typically the tracks 42 of the second conductor layer are 170 to 250cm wide: the tracks may include enlarged pad regions corresponding in shape and size to the pad regions 24 of the first conductor layer. The second conductor layer is formed by conventional thick film techniques.
However, it will be appreciated that only relatively simple and inexpensive techniques are needed to align the necessary masks for forming the vias in the insulating layer 30 and the tracks of the second conductor layer. Further, the passivation layer is also formed with openings, for wirebonds to components to be mounted on the device: these openings correspond in shape and size to pad regions of the tracks of the second conductor layer: again, simple techniques are sufficient to align the mask for these openings.
A typical sequence of steps for the manufacture of the hybrid device is set out below, by way of example only.
1) Clean silicon wafer or substrate 10.
2) Grow thermal oxide on the substrate surface.
3) Deposit aluminium film, typically to a thickness
of 3pm, by sputtering.
4) Spin on photo-resist.
5) Mask to define the narrow, high density tracks
(with pad regions) of the first conductor
layer, and expose.
6) Develop the exposed photo-resist.
7) Wet etch the aluminium, then remove the
remaining photo-resist.
8) Deposit an inorganic dielectric, typically SiO2
deposited by PECVD.
9) Spin on photo-resist.
10) Mask to define the vias (approximate alignment
being sufficient), and expose.
11) Develop the exposed photo-resist.
12) Etch the dielectric to form the vias (typically
dry reactive ion etching), then remove
remaining photo-resist.
13) Deposit aluminium film, typically by sputtering.
14) Spin on photo-resist.
15) Mask to define the wider, low density tracks of
the second conductor layer (approximate
alignment being sufficient), and expose.
16) Develop the exposed photo-resist.
17) Wet etch the aluminium, then remove the
remaining photo-resist.
18) Deposit inorganic dielectric to form the
passivation layer.
19) Spin on photo-resist.
20) Mask (approximate alignment being sufficient)
to define openings in the passivation layer for
wirebonds to components etc., then expose.
21) Develop exposed photo-resist.
22) Etch passivation layer dielectric and then
remove remaining photo-resist.
Claims (5)
1) A hybrid integrated circuit device comprising a substrate, a first conductor layer formed over a surface of the substrate and comprising a plurality of relatively narrow conductor tracks having enlarged pad regions, an insulating layer formed over said first conductor layer and having openings therein corresponding to said pad regions, and a second conductor layer formed over said insulating layer and comprising a plurality of relatively wide conductor tracks connecting with said pad regions through said openings.
2) A hybrid integrated circuit device as claimed in claim 1, comprising one or more further conductor layers each comprising a plurality of relatively wide conductor tracks which interconnect with the conductor tracks of the preceding conductor layer through opening in an intervening insulating layer.
3) A hybrid integrated circuit device substantially as herein described with reference to the accompanying drawings.
4) A method of manufacturing a method of manufacturing a hybrid integrated circuit device, comprising forming a first conductor layer over a surface of a substrate, the first conductor layer comprising a plurality of relatively narrow conductor tracks having enlarged pad regions, forming an insulating layer over said first conductor layer, said insulating layer being formed with openings therein corresponding to said pad regions, and forming a second conductor layer over said insulating layer, said second conductor layer comprising a plurality of relatively wide conductor tracks connecting with said pad regions through said openings.
5) A method of manufacturing a hybrid integrated circuit, the method being substantially as herein described with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9306392A GB2276491A (en) | 1993-03-26 | 1993-03-26 | Multilayered connections for intergrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9306392A GB2276491A (en) | 1993-03-26 | 1993-03-26 | Multilayered connections for intergrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9306392D0 GB9306392D0 (en) | 1993-05-19 |
| GB2276491A true GB2276491A (en) | 1994-09-28 |
Family
ID=10732854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9306392A Withdrawn GB2276491A (en) | 1993-03-26 | 1993-03-26 | Multilayered connections for intergrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2276491A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0096455A2 (en) * | 1982-06-04 | 1983-12-21 | Kabushiki Kaisha Toshiba | Multilayer interconnection structure for semiconductor device |
| EP0347792A2 (en) * | 1988-06-23 | 1989-12-27 | Fujitsu Limited | Multi-layer wirings on a semiconductor device and fabrication method |
-
1993
- 1993-03-26 GB GB9306392A patent/GB2276491A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0096455A2 (en) * | 1982-06-04 | 1983-12-21 | Kabushiki Kaisha Toshiba | Multilayer interconnection structure for semiconductor device |
| EP0347792A2 (en) * | 1988-06-23 | 1989-12-27 | Fujitsu Limited | Multi-layer wirings on a semiconductor device and fabrication method |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9306392D0 (en) | 1993-05-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |