CN117594550A - Wiring substrate and manufacturing method thereof - Google Patents
Wiring substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN117594550A CN117594550A CN202311629184.3A CN202311629184A CN117594550A CN 117594550 A CN117594550 A CN 117594550A CN 202311629184 A CN202311629184 A CN 202311629184A CN 117594550 A CN117594550 A CN 117594550A
- Authority
- CN
- China
- Prior art keywords
- glass
- glass substrate
- substrate
- layer
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 296
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000011521 glass Substances 0.000 claims abstract description 285
- 239000010410 layer Substances 0.000 claims abstract description 141
- 239000012790 adhesive layer Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 11
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000004519 grease Substances 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000004891 communication Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000003746 surface roughness Effects 0.000 claims description 2
- 230000008054 signal transmission Effects 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000006089 photosensitive glass Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Abstract
The embodiment of the application provides a wiring substrate and a manufacturing method thereof, wherein the wiring substrate comprises a plurality of layers of glass substrates and bonding adhesive layers, and the glass substrates are provided with through hole wiring and conducting layers. Adjacent glass substrates are bonded through the bonding adhesive layer, so that gaps do not exist between the adjacent glass substrates, RDL high-density interconnection with more compact structure and stable performance can be realized, staggered stacking is not needed between the adjacent glass substrates, the area of the openable holes can be increased, and glass through holes can be formed in the glass substrates according to different actual requirements. In addition, through hole wires in the adjacent glass substrates are communicated through the conductive layers on the adjacent glass substrates to form conductive wires, and the conductive wires are used for transmitting electric signals from one side of the wire substrates to the other side of the wire substrates, so that signal transmission paths can be effectively reduced, delay and loss of signal transmission are reduced, and high-frequency performance of the wire substrates is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a wiring substrate and a method for manufacturing the wiring substrate.
Background
With the continued development of semiconductor manufacturing processes, glass punch (Through Glass Via, TGV) technology is widely used in integrated circuits and microsystem packaging. TGV technology achieves high density interconnection in packages by making tiny vias in a glass substrate, where the vias can be used to pull out signals, power and ground to connect the chip to external circuitry.
However, in the prior art, when fine wiring is performed by using glass through holes, glass substrates are often required to be stacked in a staggered manner, bonding wires or bumps are adopted between the glass through holes, so that the arrangement is performed, due to the fact that the contact area between adjacent glass substrates is limited, the number of openable holes is limited, gaps appear between the adjacent glass substrates, in the actual chip packaging process, insulating materials need to be additionally filled in the gaps in order to ensure the stability of the structure, the integral integration level of the substrates is not high, and the structure is easy to warp.
Disclosure of Invention
In order to at least overcome the above-mentioned drawbacks in the prior art, an object of the present application is to provide a wiring substrate and a method for manufacturing the wiring substrate.
In a first aspect, an embodiment of the present application provides a trace substrate, where the trace substrate includes: and each layer of glass substrate is provided with a conductive layer protruding relative to the surface of the glass substrate and glass through holes penetrating through two opposite sides of the glass substrate, through hole wiring is arranged in each glass through hole, and the through hole wiring is electrically connected with the conductive layer.
And the bonding adhesive layer is positioned on one side of the glass substrate, on which the conductive layer is arranged, and the projection of the bonding adhesive layer on the glass substrate is not overlapped with the projection of the conductive layer on the glass substrate.
The adjacent glass substrates are bonded through the bonding adhesive layer, through hole wires in the adjacent glass substrates are communicated through the conductive layers on the adjacent glass substrates to form conductive wires, and the conductive wires are used for transmitting electric signals from one side of the wire substrates to the other side of the wire substrates.
In one possible implementation, the glass substrate comprises an ultra-thin glass substrate having a thickness of no more than 100 um.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a routing substrate, where the method includes:
providing a plurality of glass substrates;
glass through holes penetrating through two opposite sides of each glass substrate are formed in each glass substrate, through hole wiring is formed in each glass through hole, and a conductive layer electrically connected with the through hole wiring is formed on the surface of each glass substrate;
manufacturing a bonding adhesive layer on one side of the glass substrate, on which the conductive layer is manufactured, wherein the projection of the bonding adhesive layer on the glass substrate is not overlapped with the projection of the conductive layer on the glass substrate;
and stacking a plurality of glass substrates in sequence, bonding adjacent glass substrates through the bonding adhesive layer, and communicating conductive layers in the adjacent glass substrates to form conductive wiring to obtain the wiring substrate.
In one possible implementation manner, the steps of forming a glass through hole penetrating through two opposite sides of the glass substrate on each glass substrate, forming a through hole trace in the glass through hole, and forming a conductive layer electrically connected with the through hole trace on the surface of the glass substrate include:
providing a carrier plate;
manufacturing an adhesive layer on the surface of the carrier plate;
placing the glass substrate on one side of the bonding layer far away from the carrier plate, and manufacturing at least one glass through hole on the glass substrate;
and manufacturing a through hole wiring in the glass through hole and a conductive layer electrically connected with the through hole wiring on the glass substrate, wherein the conductive layer is positioned on one side of the glass substrate away from the carrier plate.
In one possible implementation manner, the step of fabricating, on the glass substrate, a via trace located in the glass via and a conductive layer electrically connected to the via trace includes:
performing physical vapor deposition on the glass substrate after the glass through hole is manufactured, and forming a metal film on the inner wall of the glass through hole and the surface of one side of the glass substrate away from the carrier plate;
manufacturing a mask protection layer on the metal film positioned on the surface of one side of the glass substrate, which is far away from the carrier plate, wherein the mask protection layer is used for defining the shape and the position of the conductive layer, and at least exposing the glass through hole;
electroplating the glass substrate after the mask protection layer is manufactured, depositing metal in the glass through hole and at the position of the glass substrate, which is far away from the carrier plate, and where the mask protection layer is not arranged, so as to obtain a through hole wiring and a metal layer positioned on the side of the glass substrate, which is far away from the carrier plate;
and removing the mask protection layer and the metal film positioned below the mask protection layer to obtain the conductive layer.
In one possible implementation manner, the step of placing the glass substrate on a side of the bonding layer away from the carrier plate and making at least one glass through hole on the glass substrate includes:
manufacturing a photoresist layer on one side of the glass substrate far away from the carrier plate, and patterning the photoresist layer;
and removing the areas, which are not protected by the photoresist layers, of the glass substrate to obtain glass through holes penetrating through two opposite sides of the glass substrate.
In one possible implementation manner, after the step of forming the bonding adhesive layer on the side of the glass substrate where the conductive layer is formed, the method further includes:
and (3) manufacturing the bonding adhesive layer and one side of the conductive layer on the glass substrate, and carrying out mechanical grinding and chemical polishing to remove the non-uniform positions of the bonding adhesive layer and the conductive layer surface so as to obtain the bonding adhesive layer and the conductive layer with flat surfaces.
In one possible implementation manner, the step of stacking a plurality of glass substrates sequentially, and forming conductive traces by connecting conductive layers in adjacent glass substrates to obtain the trace substrate includes:
stacking and bonding the glass substrates which are positioned on the carrier plate and are provided with the conducting layers and the bonding adhesive layers, and connecting the conducting layers of the adjacent glass substrates to form conducting wires;
and removing the bonding layer, and stripping the carrier plate from the stacked glass substrates to obtain the wiring substrate.
In one possible implementation manner, the step of forming a through hole trace through the glass through holes on two opposite sides of each glass substrate, and placing a conductive layer electrically connected to the through hole trace on the surface of the glass substrate, further includes:
cleaning the surface of the glass substrate to remove impurities, grease and an oxide layer on the surface of the glass substrate;
and coarsening the cleaned glass substrate to increase the surface roughness of the glass substrate.
In a third aspect, embodiments of the present application further provide an electronic component, including the trace substrate in the first aspect or the trace substrate manufactured according to any one of the methods in the second aspect.
Based on any one of the above aspects, the wiring substrate and the manufacturing method thereof provided in the embodiments of the present application include a multi-layer glass substrate and a bonding adhesive layer, wherein the glass substrate is provided with a through hole wiring and a conductive layer. Adjacent glass substrates are bonded through the bonding adhesive layer, so that gaps do not exist between the adjacent glass substrates, RDL (re-wiring layer) high-density interconnection with more compact structure and stable performance can be realized, staggered stacking is not needed between the adjacent glass substrates, the area of the openable holes can be increased, and glass through holes can be formed in the glass substrates according to different actual requirements. In addition, through hole wires in the adjacent glass substrates are communicated through the conductive layers on the adjacent glass substrates to form conductive wires, and the conductive wires are used for transmitting electric signals from one side of the wire substrates to the other side of the wire substrates, so that signal transmission paths can be effectively reduced, delay and loss of signal transmission are reduced, and high-frequency performance of the wire substrates is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly explain the drawings required for the embodiments, it being understood that the following drawings illustrate only some embodiments of the present application and are therefore not to be considered limiting of the scope, and that other related drawings may be obtained according to these drawings without the inventive effort of a person skilled in the art.
FIG. 1 is a schematic diagram of one possible structure of a trace substrate provided in the present application;
FIG. 2 is a schematic flow chart of a method for fabricating a trace substrate according to the present disclosure;
FIG. 3 is a process flow diagram corresponding to FIG. 2;
FIG. 4 is a flow chart illustrating the substep of step S12 in FIG. 2;
FIG. 5 is a process flow diagram corresponding to FIG. 4;
FIG. 6 is a flow chart illustrating the substep of step S124 in FIG. 4;
FIG. 7 is a process flow diagram corresponding to FIG. 6;
FIG. 8 is a possible process diagram of step S14 of FIG. 2.
Icon:
10-wiring substrate; 110-a glass substrate; 120-bonding adhesive layer; 130-conductive layer (via trace); 140-carrier plates; 150-an adhesive layer; 111-glass through holes; 160-mask protection layer; 131-a metal film; 132-metal layer.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that, the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that is commonly put when the product of the application is used, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
It should be noted that, in the case of no conflict, different features in the embodiments of the present application may be combined with each other.
The following detailed description of specific embodiments of the present application refers to the accompanying drawings.
Referring to fig. 1, fig. 1 illustrates a schematic structure of a trace substrate 10 according to an embodiment of the present application, where the trace substrate 10 includes a multi-layer glass substrate 110 and a bonding adhesive layer 120.
Specifically, each glass substrate 110 is provided with a conductive layer 130 protruding relative to the surface of the glass substrate 110 and at least one glass through hole penetrating through two opposite sides of the glass substrate 110, a through hole wiring 130 is disposed in the glass through hole, and the through hole wiring 130 is electrically connected with the conductive layer 130, wherein the through hole wiring 130 disposed in the glass through hole can reduce crosstalk generated by adjacent signal lines, and improve performance of the whole circuit. The bonding adhesive layer 120 is located on one side of the glass substrate 110 where the conductive layer 130 is located, and the projection of the bonding adhesive layer 120 on the glass substrate 110 is not overlapped with the projection of the conductive layer 130 on the glass substrate 110.
The adjacent glass substrates 110 are bonded by the bonding adhesive layer 120, and the through hole traces 130 in the adjacent glass substrates 110 are communicated by the conductive layer 130 on the adjacent glass substrates 110 to form conductive traces for transmitting electrical signals from one side of the trace substrate 10 to the other side of the trace substrate 10. By the arrangement, gaps do not exist between the adjacent glass substrates 110, RDL (re-wiring layer) high-density interconnection with more compact structure and stable performance is realized, staggered stacking is not needed, the area of the openable holes can be increased, and glass through holes can be formed in the glass substrates 110 according to different actual requirements. In addition, the conductive layers 130 on the adjacent glass substrates 110 are communicated to form conductive traces, and by means of the conductive traces, the electric signals are transferred from one side of the trace substrate 10 to the other side of the trace substrate 10, so that signal transmission paths can be effectively reduced, delay and loss of signal transmission are reduced, and high-frequency performance of the trace substrate 10 is improved.
In this embodiment, the adjacent glass substrates 110 are bonded through the bonding adhesive layer 120, so that no gap exists between the adjacent glass substrates 110, high-density interconnection of the rewiring layers with more compact structure and more stable performance can be realized, staggered stacking is not required between the adjacent glass substrates 110, the area of the openable holes can be increased, and glass through holes can be formed in the glass substrates 110 according to different actual requirements. In addition, the through hole traces 130 in the adjacent glass substrates 110 are communicated through the conductive layers 130 on the adjacent glass substrates 110 to form conductive traces, and the conductive traces are used for transmitting electrical signals from one side of the trace substrates 10 to the other side of the trace substrates 10, so that signal transmission paths can be effectively reduced, delay and loss of signal transmission can be reduced, and high-frequency performance of the trace substrates 10 can be improved.
Further, in the wiring substrate 10 provided in the embodiment of the present application, the thicknesses of different glass substrates 110 in the same wiring substrate 10 may be the same or different, the thickness of each glass substrate 110 in the wiring substrate 10 may be adjusted according to different application scenarios, and the specific thickness of the glass substrate 110 is not limited. For example, in the context of improving the integration of devices, it may be preferable to stack ultra-thin glass having a thickness of not more than 100 μm for achieving high-density interconnection.
Based on the same inventive concept, the present application further provides a method for manufacturing the wiring substrate 10, and the method for manufacturing the wiring substrate 10 provided in the embodiment of the present application is described in detail below with reference to fig. 2 and 3, where fig. 2 illustrates specific manufacturing steps of the method for manufacturing the wiring substrate 10 provided in the embodiment of the present application, and fig. 3 illustrates a corresponding process manufacturing diagram.
Step S11: a plurality of glass substrates 110 are provided.
In this step, in order to improve the integration of the device so that the wiring substrate 10 can realize multi-layered wiring in a limited space, the thickness of the glass substrate 110 is generally not more than 100 μm.
Step S12: glass through holes penetrating opposite sides of the glass substrate 110 are formed on each glass substrate 110, through hole traces 130 are formed in the glass through holes, and conductive layers 130 electrically connected to the through hole traces 130 are formed on the surface of the glass substrate 110.
In this step, before the glass through hole is formed, the surface of the glass substrate 110 may be cleaned with clean water to remove impurities, grease and other contaminants on the surface of the glass substrate 110, then the glass substrate 110 is pickled to remove oxide layers and other adhering impurities on the surface of the glass substrate 110, and finally the glass substrate 110 is roughened to increase the roughness of the surface of the glass substrate 110. The vertical glass via structure is fabricated on the glass substrate 110, which not only can realize highly integrated interconnection, but also can reduce crosstalk of adjacent signal lines to the via traces 130, and improve performance of the overall circuit.
Step S13: the bonding adhesive layer 120 is formed on the side of the glass substrate 110 on which the conductive layer 130 is formed, and the projection of the bonding adhesive layer 120 on the glass substrate 110 does not overlap with the projection of the conductive layer 130 on the glass substrate 110.
In this step, before the bonding adhesive layer 120 is fabricated, the surface of the glass substrate 110 may be pretreated to improve the adhesion of the bonding adhesive layer 120, and then the bonding adhesive layer 120 is formed by coating bonding adhesive on the glass substrate 110 where the conductive layer 130 is not fabricated.
Step S14: a plurality of glass substrates 110 are stacked in sequence, adjacent glass substrates 110 are bonded through the bonding adhesive layer 120, and conductive traces are formed by the connection of the conductive layers 130 in the adjacent glass substrates 110, so as to obtain the trace substrate 10.
In this step, the adjacent glass substrates 110 are bonded by the bonding adhesive layer 120, so that no gap exists between the adjacent glass substrates 110, and high-density interconnection of the rewiring layers with more compact structure and more stable performance can be realized. The through hole traces 130 in the adjacent glass substrates 110 are communicated through the conductive layers 130 on the adjacent glass substrates 110 to form conductive traces, and the conductive traces are used for transmitting electrical signals from one side of the trace substrates 10 to the other side of the trace substrates 10, so that signal transmission paths can be effectively reduced, delay and loss of signal transmission can be reduced, and high-frequency performance of the trace substrates 10 can be improved.
In this embodiment, the adjacent glass substrates 110 are bonded through the bonding adhesive layer 120, so that no gap exists between the adjacent glass substrates 110, high-density interconnection of the rewiring layers with more compact structure and more stable performance can be realized, staggered stacking is not required between the adjacent glass substrates 110, the area of the openable holes can be increased, and glass through holes can be formed in the glass substrates 110 according to different actual requirements. In addition, the through hole traces 130 in the adjacent glass substrates 110 are communicated through the conductive layers 130 on the adjacent glass substrates 110 to form conductive traces, and the conductive traces are used for transmitting electrical signals from one side of the trace substrates 10 to the other side of the trace substrates 10, so that signal transmission paths can be effectively reduced, delay and loss of signal transmission can be reduced, and high-frequency performance of the trace substrates 10 can be improved.
As a possible implementation manner of the embodiment of the present application, please refer to fig. 4 and 5, step S12 may also be implemented by the following method.
Step S121: a carrier 140 is provided.
In this step, the carrier 140 may be, but is not limited to, a glass carrier, a metal carrier, a resin carrier, or the like.
Step S122: an adhesive layer 150 is formed on the surface of the carrier 140.
Step S123: the glass substrate 110 is placed on the side of the adhesive layer 150 away from the carrier plate, and at least one glass through hole 111 is made in the glass substrate 110.
Step S124: a through hole trace 130 located in the glass through hole 111 and a conductive layer 130 electrically connected to the through hole trace 130 are fabricated on the glass substrate 110, and the conductive layer 130 is located on a side of the glass substrate 110 away from the carrier 140.
In this embodiment, the adhesive layer 150 may be made of a thermal release material and/or a laser release material, so as to achieve temporary bonding between the glass substrate 110 and the carrier plate, thereby solving the problem of ultra-thin glass transfer. In addition, the vertical glass via 111 structure may be fabricated by plasma etching, photosensitive glass and/or laser induced etching, to achieve highly integrated interconnection while reducing crosstalk of adjacent signal lines to via traces 130, and to improve overall circuit performance.
Further, referring to fig. 6 and 7, step S124 may be implemented by the following method.
Step S1241: the glass substrate 110 after the glass through hole 111 is formed is subjected to physical vapor deposition, and a metal film 131 is formed on the inner wall of the glass through hole 111 and the surface of the glass substrate 110 on the side away from the carrier plate.
In this step, the glass substrate 110 after the glass via 111 is formed may be subjected to Physical Vapor Deposition (PVD) to obtain a metal film, and the metal film may be, for example, copper, chromium, aluminum, or the like, so that the metal film may not only improve the conductivity of the glass via 111, but also improve the adhesion of the conductive layer 130 and the via trace 130 to the glass substrate 110.
Step S1242: a mask protecting layer 160 is formed on the metal film 131 on the surface of the glass substrate 110 on the side away from the carrier.
In this step, the mask protection layer 160 is used to define the shape and position of the conductive layer 130, and the mask protection layer 160 at least exposes the glass via 111, so that the mask protection layer 160 can be formed at a position where the conductive layer 130 does not need to be formed. Specifically, a photoresist layer may be first fabricated on the metal film 131 on the surface of the glass substrate 110, which is far away from the carrier plate, then the photoresist layer is subjected to operations such as exposure and development, and finally the undeveloped photoresist layer is removed.
Step S1243: and electroplating the glass substrate 110 after the mask protection layer is manufactured, and depositing metal in the glass through hole 111 and at the position of the glass substrate 110, which is far away from the carrier plate, and is not provided with the mask protection layer 160, so as to obtain a through hole wiring 130 and a metal layer 132 positioned on the side of the glass substrate 110, which is far away from the carrier plate.
In this step, a metal conductive layer having a certain thickness may be formed by electrochemically depositing a metal on the glass substrate 110, thereby ensuring the conductivity of the via trace 130 and the conductive layer 130.
Step S1244: the mask protection layer 160 and the metal film 131 under the mask protection layer 160 are removed to obtain the conductive layer 130.
In this step, the metal film 131 overlapped with the mask protective layer 160 may be removed by etching after the mask protective layer 160 is removed, to obtain the conductive layer 130.
In the present embodiment, by the physical vapor deposition and electroplating matching method, the uniform and firm via trace 130 and the conductive layer 130 can be formed in the glass via 111 and on the side of the glass substrate 110 away from the carrier 140.
Still further, step S123 may be implemented by the following method.
First, a photoresist layer is formed on a side of the glass substrate 110 away from the carrier, and the photoresist layer is patterned. Then, the regions of the glass substrate 110 not protected by the photoresist layer are removed, resulting in glass through holes 111 penetrating opposite sides of the glass substrate 110.
In this step, the vertical glass via 111 structure may be fabricated by plasma etching, photosensitive glass, and/or laser-induced etching, to achieve highly integrated interconnection while reducing crosstalk of adjacent signal lines to the via traces 130, and improving performance of the overall circuit.
As a possible implementation manner of the embodiment of the present application, the following method may be further included after step S13.
And mechanically grinding and chemically polishing one side of the glass substrate 110, which is provided with the bonding adhesive layer 120 and the conductive layer 130, and removing uneven surfaces of the bonding adhesive layer 120 and the conductive layer 130 to obtain the bonding adhesive layer 120 and the conductive layer 130 with flat surfaces, so as to improve the bonding effect between the adjacent glass substrates 110, ensure that no gap exists between the adjacent glass substrates 110, and realize high-density interconnection of the rewiring layers with more compact structure and stable performance.
Further, step S14 may be implemented by the following method.
The glass substrates 110 which are positioned on the carrier plate 140 and are provided with the conductive layers 130 and the bonding adhesive layers 120 are stacked and bonded, the conductive layers 130 of the adjacent glass substrates 110 are communicated to form conductive traces, the adhesive layers are removed, and the carrier plate and the stacked glass substrates 110 are peeled off to obtain the trace substrate 10.
Specifically, referring to fig. 8, after temporary bonding of the carrier plate 140 and the glass substrate 110 is adopted, the problem that the glass substrate 110 can be transferred is solved, after bonding of the adjacent glass substrates 110 is completed, part of the adhesive layer 150/all of the adhesive layer 150 can be removed by thermal stripping and/or laser stripping, when part of the carrier plate 140 is stripped from the stacked glass substrates 110, the steps described above can be repeated to continue stacking the multi-layer glass substrates 110, so as to realize more complex wiring design, until wiring is completed to strip all of the carrier plates 140 from the stacked glass substrates 110, and the wiring substrate 10 is obtained.
The embodiment of the application also provides an electronic component, which comprises the wiring substrate 10 manufactured by any one of the methods.
In summary, the embodiment of the application provides a wiring substrate and a manufacturing method thereof, wherein the wiring substrate includes a plurality of layers of glass substrates and bonding adhesive layers, and the glass substrates are provided with through hole wiring and conductive layers. Adjacent glass substrates are bonded through the bonding adhesive layer, so that gaps do not exist between the adjacent glass substrates, high-density interconnection of the rewiring layers with more compact structures and stable performances can be realized, staggered stacking is not needed between the adjacent glass substrates, the area of the openable holes can be increased, and glass through holes can be formed in the glass substrates according to different actual requirements. In addition, through hole wires in the adjacent glass substrates are communicated through the conductive layers on the adjacent glass substrates to form conductive wires, and the conductive wires are used for transmitting electric signals from one side of the wire substrates to the other side of the wire substrates, so that signal transmission paths can be effectively reduced, delay and loss of signal transmission are reduced, and high-frequency performance of the wire substrates is improved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (10)
1. A trace substrate, the trace substrate comprising:
each layer of glass substrate is provided with a conductive layer protruding relative to the surface of the glass substrate and glass through holes penetrating through two opposite sides of the glass substrate, through hole wiring is arranged in each glass through hole, and each through hole wiring is electrically connected with the conductive layer;
the bonding adhesive layer is positioned on one side of the glass substrate, on which the conductive layer is arranged, and the projection of the bonding adhesive layer on the glass substrate is not overlapped with the projection of the conductive layer on the glass substrate;
the adjacent glass substrates are bonded through the bonding adhesive layer, through hole wires in the adjacent glass substrates are communicated through the conductive layers on the adjacent glass substrates to form conductive wires, and the conductive wires are used for transmitting electric signals from one side of the wire substrates to the other side of the wire substrates.
2. The trace substrate according to claim 1, wherein the glass substrate comprises an ultra-thin glass substrate having a thickness of no more than 100 um.
3. The manufacturing method of the wiring substrate is characterized by comprising the following steps:
providing a plurality of glass substrates;
glass through holes penetrating through two opposite sides of each glass substrate are formed in each glass substrate, through hole wiring is formed in each glass through hole, and a conductive layer electrically connected with the through hole wiring is formed on the surface of each glass substrate;
manufacturing a bonding adhesive layer on one side of the glass substrate, on which the conductive layer is manufactured, wherein the projection of the bonding adhesive layer on the glass substrate is not overlapped with the projection of the conductive layer on the glass substrate;
and stacking a plurality of glass substrates in sequence, bonding adjacent glass substrates through the bonding adhesive layer, and communicating conductive layers in the adjacent glass substrates to form conductive wiring to obtain the wiring substrate.
4. The method of manufacturing a trace substrate according to claim 3, wherein the steps of forming glass through holes penetrating opposite sides of the glass substrate on each glass substrate, forming a through hole trace in the glass through holes, and forming a conductive layer electrically connected to the through hole trace on a surface of the glass substrate, comprise:
providing a carrier plate;
manufacturing an adhesive layer on the surface of the carrier plate;
placing the glass substrate on one side of the bonding layer far away from the carrier plate, and manufacturing at least one glass through hole on the glass substrate;
and manufacturing a through hole wiring in the glass through hole and a conductive layer electrically connected with the through hole wiring on the glass substrate, wherein the conductive layer is positioned on one side of the glass substrate away from the carrier plate.
5. The method of manufacturing a trace substrate according to claim 4, wherein the step of manufacturing via traces within the glass via and a conductive layer electrically connected to the via traces on the glass substrate comprises:
performing physical vapor deposition on the glass substrate after the glass through hole is manufactured, and forming a metal film on the inner wall of the glass through hole and the surface of one side of the glass substrate away from the carrier plate;
manufacturing a mask protection layer on the metal film positioned on the surface of one side of the glass substrate, which is far away from the carrier plate, wherein the mask protection layer is used for defining the shape and the position of the conductive layer, and at least exposing the glass through hole;
electroplating the glass substrate after the mask protection layer is manufactured, depositing metal in the glass through hole and at the position of the glass substrate, which is far away from the carrier plate, and where the mask protection layer is not arranged, so as to obtain a through hole wiring and a metal layer positioned on the side of the glass substrate, which is far away from the carrier plate;
and removing the mask protection layer and the metal film positioned below the mask protection layer to obtain the conductive layer.
6. The method of manufacturing a trace substrate according to claim 4, wherein the step of placing the glass substrate on a side of the adhesive layer away from the carrier and manufacturing at least one glass via hole in the glass substrate comprises:
manufacturing a photoresist layer on one side of the glass substrate far away from the carrier plate, and patterning the photoresist layer;
and removing the areas, which are not protected by the photoresist layers, of the glass substrate to obtain glass through holes penetrating through two opposite sides of the glass substrate.
7. The method for manufacturing a trace substrate according to claim 3, wherein after the step of manufacturing the bonding adhesive layer on the side of the glass substrate on which the conductive layer is formed, the method further comprises:
and (3) manufacturing the bonding adhesive layer and one side of the conductive layer on the glass substrate, and carrying out mechanical grinding and chemical polishing to remove the non-uniform positions of the bonding adhesive layer and the conductive layer surface so as to obtain the bonding adhesive layer and the conductive layer with flat surfaces.
8. The method for manufacturing a trace substrate according to claim 4, wherein the step of stacking a plurality of glass substrates in order, and connecting conductive layers in adjacent glass substrates to form conductive traces, comprises:
stacking and bonding the glass substrates which are positioned on the carrier plate and are provided with the conducting layers and the bonding adhesive layers, and connecting the conducting layers of the adjacent glass substrates to form conducting wires;
and removing the bonding layer, and stripping the carrier plate from the stacked glass substrates to obtain the wiring substrate.
9. The method of manufacturing a trace substrate according to claim 3, wherein each glass substrate has glass vias extending through opposite sides of the glass substrate, wherein the step of forming a via trace through the glass vias and disposing a conductive layer on a surface of the glass substrate in electrical communication with the via trace further comprises:
cleaning the surface of the glass substrate to remove impurities, grease and an oxide layer on the surface of the glass substrate;
and coarsening the cleaned glass substrate to increase the surface roughness of the glass substrate.
10. An electronic component comprising a trace substrate according to any one of claims 1-2 or a trace substrate made according to the method of any one of claims 3-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311629184.3A CN117594550A (en) | 2023-11-30 | 2023-11-30 | Wiring substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311629184.3A CN117594550A (en) | 2023-11-30 | 2023-11-30 | Wiring substrate and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117594550A true CN117594550A (en) | 2024-02-23 |
Family
ID=89921711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311629184.3A Pending CN117594550A (en) | 2023-11-30 | 2023-11-30 | Wiring substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117594550A (en) |
-
2023
- 2023-11-30 CN CN202311629184.3A patent/CN117594550A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6242279B1 (en) | High density wire bond BGA | |
| US7514636B2 (en) | Circuit component module, electronic circuit device, and method for manufacturing the circuit component module | |
| US5373627A (en) | Method of forming multi-chip module with high density interconnections | |
| JP4250154B2 (en) | Semiconductor chip and manufacturing method thereof | |
| KR100836653B1 (en) | Circuit board and method for manufacturing thereof | |
| US9159693B2 (en) | Hybrid substrate with high density and low density substrate areas, and method of manufacturing the same | |
| US7935891B2 (en) | Wiring board manufacturing method | |
| KR101025520B1 (en) | manufacturing method for multi-layer PCB | |
| TWI578417B (en) | Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices | |
| US20020117753A1 (en) | Three dimensional packaging | |
| JP2000512083A (en) | Multilayer circuit having via matrix interlayer connection and method of manufacturing the same | |
| TW201134329A (en) | Multilayered wiring substrate | |
| KR102069659B1 (en) | Method for manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same | |
| US8186043B2 (en) | Method of manufacturing a circuit board | |
| CN105122449A (en) | Low cost interposer comprising an oxidation layer | |
| KR20010088866A (en) | Deposited thin build-up layer dimensions as a method of relieving stress in high density interconnect printed wiring board substrates | |
| KR101039774B1 (en) | Method of fabricating a metal bump for printed circuit board | |
| WO2008133369A1 (en) | The manufacturing method of the thin film ceramic multi layer substrate | |
| CN117594550A (en) | Wiring substrate and manufacturing method thereof | |
| CN115226301A (en) | Circuit board and manufacturing method thereof | |
| JP2004103911A (en) | Method for forming wiring | |
| EP0836228A2 (en) | Improvements in or relating to carrier tapes | |
| KR100301107B1 (en) | Multichip module substrate and method of manufacturing the same | |
| US20110220403A1 (en) | Side packaged type printed circuit board | |
| CN112151496A (en) | TSV structure with embedded inductor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |