GB2271697A - Automatic data interfacing - Google Patents

Abstract

An interfacing controller (20) is disclosed for use in a host computer system (Fig 1, not shown). A buffer memory circuit (22) is used for storage of all incoming data blocks received at ports (21). A foreground monitor circuit (23) attempts to decode data blocks to identify addressee nodes which have the greatest likelihood of receiving a message, at regular intervals determined by a clock circuit (29). This is carried out with reference to a stored file containing the addresses of "likely" addressee nodes. A background monitor circuit (30) attempts to decode identified by the foreground monitor circuit (23). This data blocks which have not been successfully is carried out with reference to a "comprehensive" addressee file (32). An indication is provided if neither circuit identifies an addressee node for the received data. Both circuits are constructed to transmit the data block to an identified addressee node (35, 27) in parallel with transmission to an updating record (36, 28). <IMAGE>

Description

"Automatic data interfacinv" The invention relates to automatic data interfacing, with particular emphasis on the capture of data in a host computer system and re-transmission to the destination or addressee nodes.

In a host computer system which carries out real time transaction processing and in which incoming data must be captured and directed to the relevant processing node, it is very important that these interfacing operations be carried out efficiently. This is particularly important where the host computer system carries out processing operations for transactions such as air freight transactions. In such a situation there is a huge volume of data being communicated with various computer systems throughout the world (such as those of airlines) and it is essential that data which is received is captured correctly, irrespective of which interfacing port it is received at on the host computer. It is also important that signals are transmitted to remote systems in a manner which does not delay or change processing operations.

British Patent Specification No. GB 2154832B (Plessey) discloses a data capture system for automatic charging of tolls to vehicle users of roads. This system also operates in real-time so that data may be generated immediately for the charging of tolls. However, this specification does not disclose a manner of data capture where data arrives from many different locations, whether or not it is in response to an outgoing query.

The invention is directed towards providing an interfacing controller which provides for automatic data communications and distribution within a host computer system for immediate updating of records in an efficient manner.

According to the invention, there is provided an interfacing controller incorporated in a host computer connected to a data switch for communication with a plurality of data reception devices, the interfacing controller comprising: a buffer memory circuit connected to a plurality of input ports, which are in turn connected to the data switch; a foreground monitor circuit connected to the buffer memory circuit and comprising:: a permanently stored addressee file containing addresses and relevant data for the most likely potential addressee nodes for data blocks received at the ports and inputted to the buffer memory circuit; a decode circuit comprising means for reading a data block in the buffer memory circuit and for decoding the addressee node with reference to the addressee file; means for transmitting the data block to the addressee node if this is identified; a clock circuit for determining the intervals at which data blocks in the buffer memory circuit are to be read and decoded; and a background monitor circuit comprising: a stored comprehensive addressee file storing addresses and relevant data for a comprehensive list of potential addressee nodes for data blocks received and stored in the buffer memory circuit 22; a decode circuit connected to the comprehensive addressee file and comprising means for identifying addressee nodes for data blocks with reference to said file; an interface circuit comprising means for interfacing with a communications system to generate an interrupt and instructions for a message to a pre-set terminal if the addressee node is not identified; means for transmitting the data block to an identified addressee node; and a clock circuit for determining the intervals at which the background monitor circuit operates on a data block received in the buffer memory circuit.

In one embodiment, the background and foreground monitor circuits include means for transmitting the data to an updating record in the host computer in parallel with transmission of the data block to an identified addressee node.

The invention will be more clearly understood from the following description of some preferred embodiments thereof, given by way of example only with reference to the accompanying drawings in which: Fig. 1 is a diagrammatic representation of a host computer system incorporating an interfacing controller of the invention; and Fig. 2 is a partial flow diagram and partial apparatus diagram showing construction of an interfacing controller of the invention.

Referring to the drawings, and initially to Fig. 1 there is illustrated a host computer system 1. The system 1 is for the carrying out of processing operations for air freight cargo handling transactions. There is a host computer 2 which is a super-minicomputer operating on a 32-bit bus and which has ten disk drives 3 of 8 GByte capacity for data storage. The host computer 2 communicates via individual ports and cables 4 and a multi-protocol data switch 5 with various other communications nodes. In particular, for communications on a leased line 6, there is a remote V11 communications circuit 7 for 9600 baud communication. This is connected to an interface circuit 8 having V11 protocol on one side and V24 protocol on the other side. The V24 side is connected to a switch multiplexer (SMUX) 10 and also to a back-up modem 9 for use in the event of a fault.The data switch 5 is also connected to a multiplexer 11 and to a microcomputer 12. In addition, the host computer 2 is connected to a modem 13 for "leased line" communication with a remote data switch. There is also a communication microcomputer 14 connected to an X25 pad for wide area network communication. The X25 pad is also connected to the data switch 5.

In more detail, the data switch 5 allows connection to terminals or microcomputers at communications speeds of 2400 to 19,200 baud over a non-limited distance. It incorporates an IBM 3270 protocol converter to allow communication with IBM protocol machines. Thus, it will be appreciated that the data switch 5 allows communications with a wide variety of different communications nodes and thus data received via the lines 4 may be from many different sources.

While this versatility in data communications is extremely important for the host system 1, it is equally important that data which is received is captured in the correct manner and is allocated to the correct node either within the host computer 2 or externally of it. This is important to ensure that transaction records are updated as quickly as possible using data which is received.

The addressee nodes of data received at the host computer 2 include an electronic mail circuit, tracking records, transaction records, the microcomputer 12, any remote computer system, or indeed any intelligent terminal connected to the data switch 5.

Referring now to Fig. 2, operation of an interfacing controller within the host computer 2 is shown. The controller is connected to a buffer memory circuit within the host computer 2 and is connected to both input and output ports communicating with the data switch 5 and locally to the microcomputer 14. These ports are hard-wired by the cables 4 to the data switch 5, and are each identified by a unique name. In Fig. 2 the ports are represented by the numeral 21 and the buffer memory circuit is represented by the numeral 22. The lines in the drawing of the circuit in Fig. 2 represent blocks of data which have been received via the ports 21. These are, of course, dynamic as data is continually being received and is being transmitted from the buffer memory 22 to the relevant addressee node.

The interfacing controller within the host computer 2 includes two monitor circuits, namely, a foreground monitor circuit 23 and a background monitor circuit 30. The foreground monitor circuit 23 operates by reading the buffer memory 22 at regular intervals as determined by a clock circuit 29. In more detail, in step 24 it reads a data block within the buffer memory 22 and decodes this by reference to an addressee file 25. The addressee file contains indexed lists of addresses for the addressee nodes which are most likely to be those for the particular data block. These include addresses of notes which have transmitted messages within a next previous time period of 60 secs, and for which replies are expected. As indicated by the decision step 26, if the data block is not successfully decoded, the process is repeated at the next time interval, as determined by the clock circuit 29.If, however, the reception device or addressee node of the data block is located, the data block is transmitted to the addressee node in step 27 and in parallel is transmitted to updating records 28. Thereafter, steps 24 to 28 are repeated at the next clock interval. In this embodiment, the clock interval is one second. Thus, the foreground monitor circuit 23 operates continuously at very frequent intervals and immediately identifies the addressees for approximately 90% of the received data blocks and directs these data blocks to the correct addressee node. This is important for reception of data from, say, an airline, in air freight traction processing.

However, some blocks of data which are received may not be so easily directed to the correct node such as when they relate to "pre-alert" air freight messages which are not in response to outgoing messages. The background monitor circuit 30 is constructed to overcome this problem. In step 31, the background monitor circuit 30 decodes a data block in the buffer memory 22 with reference to a comprehensive addressee file 32 which includes data relating to a large number of potential addressee nodes. The file 32 is more comprehensive than the addressee file 25 as it includes, for example, addresses of nodes which have transmitted messages for which a reply was expected more than 60 secs beforehand and accordingly the decoding step 31 takes longer than the decoding step 24.If the addressee is not identified, as determined by step 33, the background monitor circuit 30 generates in step 34 an alert message 2 for transmission to a supervisor. This message contains the data block and highlights the fact that an addressee node has not been found.

In many cases, the supervisor will be aware of the block of data from some other means of communication such as fax or telex and he or she may then input instructions to clear the data block from the buffer memory 22. In most cases, however, the addressee node will be identified and in steps 35 and 36 the data block is transmitted to the addressee node and is used to update the records in parallel. When these operations have been completed, steps 31 to 36 are repeated at the next time interval, which is determined by the clock circuit 37.

In this embodiment the time interval is 10 minutes. Because the circuit operates on a particular data block only every 10 minutes it does not require considerable processing power and efficiently and effectively deals with data blocks for which addressee nodes may not be easily determined.

The steps 27 and 35 of transmitting the data block to the relevant addressee node will often involve communications via the data switch 5. The fact that the data switch 5 includes intelligent processors for protocol conversion and for fast switching ensures that the data block arrives at the correct addressee node in a prompt manner.

It has been found that by use of the interfacing controller of the invention, data which is received either in response to an outgoing enquiry, or is independently received, may be efficiently dealt with. There is no need for separate ports for reception of data in response to enquiries or independent data, thus considerably improving utilisation of available ports and communications circuits.

Thus, the invention has been found to be particularly advantageous for situations such as air freight communication where time is of the essence and prompt and accurate communications are required. Further, in such situations, transactions may be quite complex, for example, routing of air freight cargo to a destination. This results in a large number of data blocks being communicated, and it is thus essential that they are captured correctly.

The invention is not limited to the embodiments hereinbefore described, but may be varied in construction and detail.

Claims (3)

1. An interfacing controller incorporated in a host computer connected to a data switch for communication with a plurality of data reception devices, the interfacing controller comprising: a buffer memory circuit connected to a plurality of input ports, which are in turn connected to the data switch; a foreground monitor circuit connected to the buffer memory circuit and comprising:: a permanently stored addressee file containing addresses and relevant data for the most likely potential addressee nodes for data blocks received at the ports and inputted to the buffer memory circuit; a decode circuit comprising means for reading a data block in the buffer memory circuit and for decoding the addressee node with reference to the addressee file; means for transmitting the data block to the addressee node if this is identified; a clock circuit for determining the intervals at which data blocks in the buffer memory circuit are to be read and decoded; and a background monitor circuit comprising: a stored comprehensive addressee file storing addresses and relevant data for a comprehensive list of potential addressee nodes for data blocks received and stored in the buffer memory circuit; a decode circuit connected to the comprehensive addressee file and comprising means for identifying addressee nodes for data blocks with reference to said file; an interface circuit comprising means for interfacing with a communications system to generate an interrupt and instructions for a message to a pre-set terminal if the addressee node is not identified; means for transmitting the data block to an identified addressee node; and a clock circuit for determining the intervals at which the background monitor circuit operates on a data block received in the buffer memory circuit.

2. A data communications controller as claimed in claim 1, wherein both the background and foreground monitor circuits include means for transmitting the data to an updating record in the host computer in parallel with transmission of the data block to an identified addressee node.

3. A data communications controller substantially as hereinbefore described with reference to, and as illustrated in the accompanying drawings.