GB2271467A - Manufacturing method of a semiconductor device - Google Patents
Manufacturing method of a semiconductor device Download PDFInfo
- Publication number
- GB2271467A GB2271467A GB9319730A GB9319730A GB2271467A GB 2271467 A GB2271467 A GB 2271467A GB 9319730 A GB9319730 A GB 9319730A GB 9319730 A GB9319730 A GB 9319730A GB 2271467 A GB2271467 A GB 2271467A
- Authority
- GB
- United Kingdom
- Prior art keywords
- silicide
- semiconductor device
- forming
- reactor
- polycide structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 52
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000001301 oxygen Substances 0.000 claims abstract description 14
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 14
- 239000007789 gas Substances 0.000 claims abstract description 13
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims abstract description 12
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 18
- 230000007847 structural defect Effects 0.000 abstract description 3
- 239000003870 refractory metal Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 241000894007 species Species 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010549 co-Evaporation Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Abstract
A method for manufacturing an MOS semiconductor device, wherein the oxidation process of a silicide is included, comprises the steps of: forming a polycide structure on a semiconductor substrate (21) by forming a gate insulating layer (22), a conductive layer containing silicon (23), and a silicide layer (24) in order; and forming a silicon oxide (25) on the whole surface of the resultant structure by the dry oxidation in an oxygen and hydrogen chloride gas atmosphere. A gate line or interconnection layer of a polycide structure is obtained without the occurrence of structural defects, thereby improving the reliability of a semiconductor device. <IMAGE>
Description
1 p 2271467 ALkWFACTURING METHOD OF A SEM[ICONDUCTOR DEVICE This invention
relates to a manufacturing method of a semiconductor device, and more particularly, to a method for oxidizing a silicide which is formed to reduce the resistivity of an interconnection in a semiconductor device.
As the features of VLSI are realized by the development of integration technology of semiconductor devices, and particularly, as design rules continue to shrink (to 11im and less), the necessity of decreasing the resistance and capacitance in association with interconnection paths becomes ever more pressing. This is particularly true for MOS (metal oxide semiconductor) devices, in which the RC delay due to the interconnection paths can exceed the delay due to the gate switching during circuit operation. The higher the value of the interconnect R X C (resistance X capacitance) product, the more likely the circuit operating speed will be limited by this delay. Accordingly, low-resistivity of interconnection paths is critical in order to fabricate a dense, high performance device.
Recently, there are several approaches to reduce the resistivity of the interconnection to less than the 15 - 30Q/ 0 exhibited by polysilicon. Among 2 -7 these is a method in which the interconnection material is replaced by aluminum which has a low resistivity. However, due to the low melting and eutectic temperature of aluminum, all subsequent processes have to be held to less than 500"C. Since several processes (e.g. source-drain implant annealing, oxidation, and glass flow/reflow) must be carried out at temperatures above 500"C, aluminum is unsuitable as the interconnection material.
In another method for reducing the resistivity of an interconnection, the polysilicon is replaced by a refractory metal (e.g., W, Ta, Ti or Mo) or a refractory metal silicide composed of silicon and a refractory metal (e. g., WSi, TiSi,, MoSi, or TaSi2) and used as the interconnect material directly.
Also, a polycide structure is used as the interconnection in order to reduce resistivity, and is a multilayer structure consisting of a low resistance material (e.g., refractory metal silicide) on top of a doped polysilicon layer.
Generally, the refractory metals have high melting temperatures, but their oxides are typically of poor quality, and in some cases are volatile (for example, Mo and W oxides). In addition, consistent threshold voltages may be difficult to obtain in MOS transistors which use the refractory metal as a gate electrode, due to impurities in their sources. The use of refractory metal silicides alone as the gate/interconnection layer, suffers similar problems as experienced in connection with the use of a refractory metal alone. The polycide structure has therefore become the predominant interconnection film for replacing polysilicon because it does not give rise to such problems.
7 3 There are several methods for forming the silicide on silicon, each of which involve a deposition followed by a thermal step: 1) deposition of a pure metal on silicon; 2) simultaneous evaporation of the silicon and the refractory metal from two sources; and 3) sputter-depositing the silicide, either from a composite target or by co-sputtering.
In the meantime, often during VLSI processing, an insulating layer must be formed on the top surface of the polycide structure to isolate it from subsequently deposited polysilicon or metal layers. Vapour-deposited silicon oxide (SiO) and silicon nitride (Si3N,) can be used for this application, but thermally grown silicon oxide generally possesses better material properties, and therefore the thermally grown silicon oxide is mainly used as an insulating layer for isolation.
By heating all of the metal silicide films on the polysilicon or singlecrystal in an oxidizing atmosphere, silicon oxide is formed on the surface of the silicide. Therefore,, an insulating layer having good electrical and physical properties can be obtained.
FIG. I of the accompanying drawings represents a conventional thermal oxidizing process for the silicide of a polycide structure.
More particularly, at first, a wafer which contains a polycide structure on its surface is loaded into a reactor whose temperature is low (e.g., 650 I O'C) in a nitrogen gas (N,) atmosphere. Next, the temperature in the reactor is ramped up slowly.
1P 4 After the temperature in the reactor has reached a certain level (e.g., 900 20C) at which the silicide can be oxidized, the wafer is annealed at the same temperature for approximately 30 minutes.
Next, at the same temperature, the silicide is dry -oxidized in a nitrogen and oxygen gas (N2 and 02) atmosphere for 30 minutes more or less (that is, Si +02 _- S'OD - Next, at the same temperature, with the nitrogen gas turned off, the silicide is wet-oxidized in an oxygen and hydrogen gas (02 and H) atmosphere for approximately five minutes (that is, Si + 2HO = SiO2, + 2H, ).
Next, at the same temperature, with th e oxygen and hydrogen gas turned off, the wafer is annealed in a nitrogen gas atmosphere for a certain period of time, and with the temperature being ramped down, the wafer is unloaded from the reactor.
In the above-described polycide structure (see Silicon Processingfor the VLSI Era by S. Wolf and R.N. Tauber, Vol. 1, 1986, pp 395-396), the oxidation process for silicide is presumed to consist of the following four distinct steps:
1) Diffusion of oxidizing species through SiO,; 2) Reaction at the silicide/oxide interface; 3) Transport of silicon atoms relative to metal atoms in the silicide; and 4) Reaction at the polysilicon/silicide interface, which releases silicon v frorn the polysilicon substrate.
As above, the silicide is oxidized by reacting oxidizing species being in the reactor and silicon atoms in the silicide, and therefore the silicon oxide is formed on the surface of the silicide layer. Here, the silicon atoms wasted in the silicide during the oxidation are replaced by silicon atoms released from the polysilicon. As the oxidation reaction continues, the silicon oxide formed on the silicide continues to thicken.
Meanwhile, the oxidation reaction occurs at the silicide/silicon oxide interface all the time in accordance with diffusion of oxidizing species through silicon oxide.
FIG. 2 of the accompanying drawings is a sectional view showing a semiconductor device including a polycide structure fabricated by conventional technology.
Referring to FIG.2, a polycide structure consisting of polysilicon layer 13 and silicide layer 14 is formed on a gate oxide 12 which is formed on a semiconductor substrate 11. Then, silicon oxide layer 15 is formed on the whole surface of Polycide and semiconductor substrate 11, by an oxidation process of silicide according to the conventional technology shown in FIGA.
However, by the conventional process chained with the dry oxidation and wet oxidation, hydrogen gas during the wet oxidation accelerates the oxidation of silicide continuously. As a result, as shown in FIG.2, silicon of the polysilicon layer 13 is over-consumed partially, and therefore a structural -p defect occurs in the polysilicon and silicide. In view of this defect, the value of the threshold voltage of a MOS transistor cannot to be maintained constantly. Therefore, this structural defect deteriorates the reliability and productivity of a semiconductor device.
An object of a first aspect of this invention, to solve the problems of the conventional technology, is to provide a method of manufacturing the semiconductor device formed by oxidizing the silicide without the occurrence of structural defects.
An object of a second aspect of this invention is to provide a method of oxidizing the silicide in a polycide structure.
According to the first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps offorming a polycide structure on a semiconductor substrate by forming a gate insulating layer, a first conductive layer containing silicon, and a silicide layer in order; and forming a silicon oxide on the whole surface of the resultant structure by dry oxidation in an oxygen and hydrogen chloride gas atmosphere.
According to a second aspect of the present invention, there is provided a method of oxidizing a silicide of the polycide structure, comprising the steps of: loading a wafer which has a polycide structure formed by forming a gate -v 7 insulating layer, a first conductive layer containing silicon, and a silicide layer in order, in a reactor at a first temperature state; first annealing in a nitrogen gas atmosphere after ramping the temperature of reactor up to a second temperature state; dry oxidizing the silicide layer in an oxygen and hydrogen chloride gas atmosphere, second annealing in a nitrogen gas atmosphere after turning off the oxygen and hydrogen chloride gas; and unloading the resultant structure from the reactor after ramping the temperature of reactor down to a third temperature state.
According to this invention, during the silicide oxidation process, the oxygen and hydrogen chloride gas oxidizes the silicide stably, thereby to maintain a uniform amount of consumed silicon. Therefore, the structure defect which tends to be formed on the surface of the first conductive layer is prevented.
Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram showing an oxidation process of silicide according to conventional technology; FIG. 2 is a cross-sectional view of a semiconductor device fabricated by conventional technology; FIG. 3 is a scheinatic diagram showing an oxidation process of silicide .P 8 according to an embodiment of the present invention; and FIG. 4 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Referring to FIG.4 showing a semiconductor device fabricated according to an embodiment of the present invention, a polycide structure is formed over a semiconductor substrate 21 as a gate electrode or interconnection layer. The polycide structure is constructed by forming a gate oxide 22, the first conductive layer 23 containing silicon, and a silicide layer 24 in order. Then, a silicon oxide layer 25 is formed on the whole surface of the resultant structure. As the first conductive layer 23, polysilicon or single crystal silicon can be used.
A method of manufacturing a semiconductor device and oxidizing a silicide according to an embodiment of the present invention will be described as follows with reference to FIGS. 3 and 4.
As shown in FIG.4, at first, a gate oxide 22 and the first conductive layer 23 containing a polysilicon or single crystal silicon are stacked on a semiconductor substrate 21 in order. Next, a silicide layer 24 is formed on first conductive layer 23 according to a conventional method, such as, for example, direct metallurgical reaction, co-evaporation, sputter deposition (co- 9 sputtering and sputtering from composite targets, chemical vapour deposition 1 of silicides), and then patterned, thereby to form a gate electrode or an interconnection layer as a polycide structure.
Next, a wafer on which the polycide structure is formed is loaded in a reactor.
Referring to FIG.3, the reactor is in a nitrogen gas atmosphere between a certain temperature range, for example 650 10 11 C. At first, the temperature of the reactor is slowly ramped up to a certain high temperature (for example, 900 20"C) in a nitrogen gas atmosphere for approximately 25 minutes. Next, the wafer is annealed firstly in the same temperature and gas atmosphere condition for a certain time (for example, 30 minutes).
Then, the wafer is oxidized in a dry oxygen and hydrogen chloride gas atmosphere at the same temperature for a certain time (for example, 62 minutes), and thereby a silicon oxide layer 25 is formed on the silicide layer 24. Here,the nitrogen gas is turned off. At this time, the oxygen and hydrogen chloride gas as oxidizing species oxidize the silicide stably, thereby to maintain the amount of consumed silicon to be uniform. Of course, during the oxidation process the silicon oxide 25 is formed on a sidewall of the polycide and a exposed surface of the semiconductor substrate 21.
Next, the wafer is annealed secondarily in the same temperature for certain time (for example 15 minutes) in a nitrogen gas atmosphere with oxygen and hydrogen chloride gas turned off. Next, the wafer is unloaded is from the reactor after ramping down the temperature in the reactor slowly (for example, to the temperature range 650 10"C for approximately 90 minutes).
According to the present invention as shown in the above-described embodiment, during the silicide oxidation, the oxygen and hydrogen chloride gas (as oxidizing species) oxidizes the silicide stably, to thereby maintain a uniform amount of consumed silicon. Therefore, the structure defect which tends to be formed on the surface of the first conductive layer, and as occurs in the conventional technology, is prevented.
Therefore, the threshold voltage of a MOS transistor and the resistivity of the interconnection can be maintained constantly. Therefore, the reliability and productivity of a semiconductor device are improved.
While the present invention has been particularly shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be effected therein without departing from the scope of the invention.
.P 11
Claims (7)
1. A method for manufacturing a semiconductor device comprising the steps of:
forming a polycide structure on a semiconductor substrate by forming a gate insulating layer, a conductive layer containing silicon, and a silicide layer in order; and forming a silicon oxide on the whole surface of the resultant structure by dry oxidation in an oxygen and hydrogen chloride gas atmosphere.
2. A method for manufacturing a semiconductor device as defined in claim 1, wherein said conductive layer comprises a polysilicon.
3. A method for oxidizing a silicide of the polycide structure comprising the steps of.
loading a wafer which has a polycide structure formed by forming a gate insulating layer, a conductive layer containing silicon, and a silicide layer in order, in a reactor at a first temperature state; first annealing in a nitrogen gas atmosphere after ramping the temperature of reactor up to a second temperature state; dry oxidizing the silicide layer in an oxygen and hydrogen chloride gas atmosphere; second annealing in a nitrogen gas atmosphere after turning off the oxygen and hydrogen chloride gas; and unloading the resultant structure from the reactor after ramping the 12 temperature of reactor down to a third temperature state.
4. A method for oxidizing a silicide of the polycide structure as defined in claim 3, wherein the range of said first temperature state is 650 10 C.
5. A method for oxidizing a silicide of the polycide structure as defined in claim 3 or 4, wherein the range of said second temperature state is 900 20C
6. A method for manufacturing a semiconductor device substantially as hereinbefore described with reference to Figures 3 and 4 of the accompanying drawings.
7. A semiconductor device manufactured according to the method of any preceding claim.
1
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR920017608 | 1992-09-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9319730D0 GB9319730D0 (en) | 1993-11-10 |
| GB2271467A true GB2271467A (en) | 1994-04-13 |
Family
ID=19340175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9319730A Withdrawn GB2271467A (en) | 1992-09-26 | 1993-09-24 | Manufacturing method of a semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH06209049A (en) |
| CN (1) | CN1087446A (en) |
| DE (1) | DE4332605A1 (en) |
| GB (1) | GB2271467A (en) |
| IT (1) | IT1272674B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004172259A (en) | 2002-11-19 | 2004-06-17 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor element |
| KR100650858B1 (en) * | 2005-12-23 | 2006-11-28 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| JP5029257B2 (en) * | 2007-01-17 | 2012-09-19 | 東京エレクトロン株式会社 | Mounting table structure and processing device |
| CN104810263B (en) * | 2014-01-24 | 2018-11-20 | 北大方正集团有限公司 | The manufacturing method of gate oxide |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4139658A (en) * | 1976-06-23 | 1979-02-13 | Rca Corp. | Process for manufacturing a radiation hardened oxide |
| EP0087581A1 (en) * | 1982-02-22 | 1983-09-07 | Siemens Aktiengesellschaft | Method of making silicon oxide layers |
-
1993
- 1993-09-24 JP JP5237814A patent/JPH06209049A/en active Pending
- 1993-09-24 DE DE4332605A patent/DE4332605A1/en not_active Withdrawn
- 1993-09-24 IT ITMI932044A patent/IT1272674B/en active IP Right Grant
- 1993-09-24 GB GB9319730A patent/GB2271467A/en not_active Withdrawn
- 1993-09-25 CN CN93118158.5A patent/CN1087446A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4139658A (en) * | 1976-06-23 | 1979-02-13 | Rca Corp. | Process for manufacturing a radiation hardened oxide |
| EP0087581A1 (en) * | 1982-02-22 | 1983-09-07 | Siemens Aktiengesellschaft | Method of making silicon oxide layers |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4332605A1 (en) | 1994-03-31 |
| ITMI932044A0 (en) | 1993-09-24 |
| JPH06209049A (en) | 1994-07-26 |
| IT1272674B (en) | 1997-06-26 |
| GB9319730D0 (en) | 1993-11-10 |
| CN1087446A (en) | 1994-06-01 |
| ITMI932044A1 (en) | 1995-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5970370A (en) | Manufacturing capping layer for the fabrication of cobalt salicide structures | |
| US5766379A (en) | Passivated copper conductive layers for microelectronic applications and methods of manufacturing same | |
| US6091152A (en) | Semiconductor device and method for fabricating the same | |
| US20050130380A1 (en) | Semiconductor device structures including metal silicide interconnects and dielectric layers at substantially the same fabrication level | |
| JP2002314067A (en) | Semiconductor device and manufacturing method of mis- type field effect transistor | |
| US6100188A (en) | Stable and low resistance metal/barrier/silicon stack structure and related process for manufacturing | |
| US6156644A (en) | Method for forming interconnects for semiconductor devices using reaction control layers, and interconnects formed thereby | |
| JPH04259242A (en) | Manufacture of semiconductor device | |
| KR100755121B1 (en) | Method for forming electrode structure and method for fabricating semiconductor device | |
| US7867918B1 (en) | Semiconductor topography including a thin oxide-nitride stack and method for making the same | |
| JP2005510882A (en) | Metal gate electrode for pFET suitable for high-temperature process and method for manufacturing the same | |
| GB2271467A (en) | Manufacturing method of a semiconductor device | |
| US6635938B1 (en) | Semiconductor device and manufacturing method thereof | |
| US5731226A (en) | Low temperature method of manufacturing epitaxial titanium silicide | |
| US8026143B2 (en) | Semiconductor element and manufacturing method thereof | |
| JPH11289087A (en) | Semiconductor device and its manufacture | |
| KR100349625B1 (en) | Method for fabrication of epitaxial cobalt-disilicide layer at low temperatures | |
| US6117755A (en) | Method for planarizing the interface of polysilicon and silicide in a polycide structure | |
| US6432803B1 (en) | Semiconductor device and method of fabricating the same | |
| Wong et al. | Direct tungsten on silicon dioxide formed by RF plasma-enhanced chemical vapor deposition | |
| JP2001274391A (en) | Method for forming electrode structure and method for manufacturing semiconductor device | |
| US10957644B2 (en) | Integrated structures with conductive regions having at least one element from group 2 of the periodic table | |
| JP2739593B2 (en) | Semiconductor device manufacturing method | |
| KR100400288B1 (en) | Method for manufacturing transistor of semiconductor device | |
| US5908321A (en) | Semiconductor structure with stable pre-reacted particle and method for making |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |