GB2270590A

GB2270590A - Semiconductor devices including field effect transistors

Info

Publication number: GB2270590A
Application number: GB9312825A
Authority: GB
Inventors: Jeremy Henley Burroughes; Paul Michael Owen; Donald Dominic Arnone
Original assignee: Toshiba Cambridge Research Centre Ltd
Current assignee: Toshiba Europe Ltd
Priority date: 1992-09-11
Filing date: 1993-06-22
Publication date: 1994-03-16
Anticipated expiration: 2013-06-22
Also published as: JPH07307462A; GB2270590B; GB9312825D0

Abstract

The transistor such as a HEMT comprises a superlattice 37 including a plurality of layers of different conductivity types on a substrate 33. The superlattice is patterned to have an angled facet 41, preferably oblique to the plane of the substrate. A barrier layer 45 and active layer are formed by regrowth on the angled facet. Quantum wires 65 (or 1 DEG) are produced in directions along the planes of the superlattice layers acting as a gate under a first gate electrode 57. An ohmic contact 59 on another facet 43 connects the superlattice 37 and a second gate 61 isolated by a silicon nitride layer 63. The device may be constructed to operate as a microwave or infrared detector. <IMAGE>

Description

SEMICONDUCTOR DEVICE AND METHOD FOR ITS MANUFACTURE The present invention relates to a novel kind of semiconductor device which may be fabricated, in several different forms. One set of variants of this novel device takes the form of field effect transistors for example a high speed field effect transistors of the kind known as a high electron mobility transistor (HEMT) or a velocity modulation transistor (VMT). Another set of variants function as detectors of electromagnetic radiation, for example sensitive in the infra-red range.

It is known that heterostructures such as GaAs/AlGaAs provide a so-called two dimensional electron gas (2DEG), in which the wavefunction perpendicular to the layers is quantised in energy and electrons are confined in the GaAs layer near the GaAs/AlGaAs hetero-interface but can move freely in a plane close and parallel to the interface.

By separating donor impurities from the electron conducting channel, i.e., by doping the AlGaAs layer, the 2DEG exhibits a very high mobility (of the order of 106 cm2/Vs). This is utilized in HEMTs which are otherwise sometimes termed MODFETs (Modulation Doped Field Effect Transistors). The HEMT finds application in such areas as microwave amplifiers and high speed integrated circuits.

Recently, considerable effort has been devoted towards development of a device in which the electron gas has only one degree of freedom, ie. so that it exists as a one-dimensional electron gas (1DEG) or 'quantum wire'.

Since quantum wire devices should enable very high mobilities to be obtained, they are potentially of great interest in the development of extremely fast transistors with ultra-high levels of integration.

Up to now, efforts to produce quantum wires have been unsuccessful and/or restricted to etching grooves in the heterostructure to deplete-out regions of a 2DEG or using electrostatic "pinching" of a 2DEG. Such devices are of rather limited practical application because the number of effective carriers is relatively low, and the wire widths large.

Figure 1 of the accompanying drawings shows a schematic of a proposal by H.L. Stormer et al in "Cleaved Edge Overgrowth: A route to Atomically Precise Lower Diversional Structures", Academic Press 1992; ISBN 0-12-409660-3. According to this proposal, an HEMT structure 1 is regrown on a cleaved (110) facet 3 of a GaAs/AlGaAs superlattice 5 grown on a (100) substrate.

Appropriate biasing of the respective layers of the superlattice should form a one-dimensional electron gas 7 at the regrowth surface.

The device of Stormer et al suffers from several practical disadvantages. For example, because the production process entails cleavage across the superlattice layers, it cannot be mass-produced by whole wafer processing.

Moreover since the active electronic interface is the regrowth surface, the device is highly sensitive to contamination during manufacture.

U.S. Patent 4 835 578 describes a device which is said to be operable as a laser, light emitting diode or transistor. Here, a first superlattice is partly etched along a vertical side wall exposing individual layer edges and a second superlattice is grown over the etched face. The structure is annealed at 5500 to 680 0C and Zn impurities from the first superlattice diffuse into the second to form a disordered region where it is said that a quantum wire can be formed. Not only is this device difficult to manufacture, diffusion of impurities out of the superlattice makes it very difficult to control the resultant composition in the regrowth structure.

As far as known detectors are concerned, B. F. Levine et al have reported in Appl. Phys. Lett. Vol. 56, 1990, pp 851-853, a 50-period multi-quantum well superlattice infra-red detector. This comprises 6-n doped quantum well layers alternated between Al GaAs barrier layers with n contact layers either side of the entire superlattice structure.

The detector of Levine et al has a number of disadvantages. For example the orientation of the quantum wells in the 6- doped layers is orthogonal to the polarisation of incident radiation. This means that a grating or prism is required for coupling. Moreover, the device is not tunable.

We have now devised a new kind of device which in whatever form, overcomes the drawbacks of the relevant conventional devices. Thus, one aspect of the present invention provides a semiconductor device comprising an active layer and a barrier layer regrown on a patterned wafer in the form of a superlattice wherein the active layer is adjacent to or in contact with the barrier layer and the barrier layer is adjacent to or in contact with the superlattice so that respective biasing of the superlattice layers induces at least one narrow elongate conduction channel in or adjacent to the active layer and capable of conduction in a direction parallel to the superlattice edges which are in contact with the barrier layer.

A second aspect of the present invention provides a semiconductor device comprising a superlattice on a substrate, the superlattice comprising a plurality of layers, the superlattice having an angled facet, a barrier layer being provided on or adjacent to said angled facet and an active layer on or adjacent to said barrier layer.

Preferably, at least some of the layers of the superlattice are 6 doped.

In the context of the present invention, the term "superlattice" means any system having layers of different characteristics (eg. different conductivity types or band gaps) varying on a regular periodic basis. A superlattice must have at least three layers.

The term "6 doping" refers to the selective introduction of impurities into at least some layers to produce a superlattice.

The term "patterned wafer" or "patterned substrate" means a chip, wafer, substrate etc having a varying depth profile in at least one relevant area of its surface. Such patterning can result from any suitable technique such as wet or dry etching or area selective growth.

The present invention can take the form of a device which produces one or more quantum wires in the form of a true one dimensional quantum well with only a few propagating transverse modes. However, for the avoidance of doubt, in the context of the present invention 'quantum wire' also includes a constricted 2DEG such as produced by some of the previously known devices mentioned above.

The barrier layer is grown on or adjacent to the superlattice and the active layer on or adjacent to the barrier layer to define a confinement region in the active layer which may be "pinched" into the quantum wires under the influence of applied potentials as described in more detail hereinbelow. Thus, it is possible in some circumstances to provide one or more spacer layers between active layers. As also described further hereinbelow, in many embodiments, a second barrier layer lies the other side of the active layer, remote from the superlattice. The barrier layer or layers is/are made of semiconductor materials having a wider band gap than the material of the active layer.

Devices according to the present invention can be mass produced by whole wafer processing, using selective etching to produce the patterning necessary to produce the angled facet. Regrowth on the angled facet allows the barrier layer to be in contact with the respective layers of the superlattice which are thereby exposed.

Since the contact surface is not the active electronic interface, as will be explained in more detail hereinbelow, low contamination levels are less critical. Therefore, devices according to the present invention provide significant advantages over the form of construction of Stormer et al.

Thus, a third aspect of the present invention provides a method of manufacturing a semiconductor device, the method comprising the steps of: growing a superlattice structure on a substrate, the superlattice comprising a plurality of layers at least some of which are 6 doped; selectively etching said superlattice structure to form an angled facet; forming a barrier layer by regrowth on or adjacent to or said angled facet; and forming an active layer on or adjacent to or said barrier layer.

In nearly all cases, using regular etching techniques, the angled facet will be oblique to the plane of the substrate although using dry etching, it is possible for the angled facet to be substantially perpendicular to the substrate.

As mentioned above, a minimum of three layers is required in the superlattice to induce a single quantum wire. However, this technology permits many layers to be formed, so that up to 20 or even up to 100 or more quantum wires may be induced. This is an advantage because connecting several quantum wires in parallel not only allows larger currents to be handled but quantum fluctuations within individual wires are averaged-out.

The basic construction employed by the present invention lends itself to a number of different specific forms of device. These include transistors and detectors of electromagnetic radiation. Of the transistors, one is a novel form of velocity modulation transistor (VMT).

The mode of operation of VMTs may be understood by first considering the conventional HEMT structure. Figure 2 of the accompany drawings shows the energy band diagram of an HEMT near the hetero-interface, Electrons are transferred to the interface from n-type doped AlGaAs layer and form a channel adjacent to the interface.

Electrons are quantised due to a triangular-like potential profile and occupy sub-bands. Figure 2 shows the lowest two sub-bands El and E2. The energy difference E21 = E2 - E1 is typically about 20 meV.

Therefore, when the carrier density is smaller than 11 2 about 6xl01l/cm /cm only the ground-state sub-band is occupied. The carrier density is changed by the Schottky barrier formed at the surface.

The theoretical limits of operating speeds of conventional HEMTs have been analysed by H.Sakaki in (Japanese Journal of Applied Physics Vo. 21, No. 6, June 1982 p.L381). To improve on the speed of the conventional devices, this reference proposes a concept of velocity (or mobility) modulation. In ordinary field effect transistors, conductivity modulation aG is effected through the change of carrier density aN within a channel. This sets a speed limit of about 1 picosecond using high-velocity electrons (~ 2x107 cm/s) travelling over a channel distance of 0.2 m.

In reality, for conventional FETs capacitance often limits the practical speed of operation but using velocity modulation overcomes this drawback.

According to the velocity modulation concept, the channel conductivity G is modulated by the gate voltage mainly through a change of carrier mobility ap, the carrier density being maintained at a constant value.

This may be understood by considering the expression, aG=FN+Np. The ordinary HEMT utilizes the first term on the right hand side, whilst the VMT utilises the second term. From this expression it is seen that in the VMT it is important to keep the large value of N and to realize a large value of A#.

The VMT concept has been embodied as a dual-channel structure, as disclosed in the specification of Japanese patent TOKKAI-SHO 58-178572. This structure is also referred to as a back gated HEMT structure.

Figure 3 shows the layer structure and Figure 4 the operating principle of a back gated HEMT 11. Two channels 13, 15 are respectively controlled by two back-to-back HEMT arrangements having respective front and back gate electrodes 17, 19. A source 21 and a drain 23 are respectively arranged at either end of the two channels.

In each channel, the wavefunction perpendicular to the 2DEG plane is quantised and a single sub-band is occupied. All the carriers can be localised in the 2DEG of either channel 13 or channel 15 by positively biasing the front gate 17 and negatively biasing gate 19 (or vice versa). The first situation is shown in diagram (c) and the latter in (d). Diagram (a) shows the position with zero bias on both gates and (b), the impurity distribution.

By the appropriate biasing of gates A and B, the carrier density can be constant between the state where all the carriers are in channel A and that where all the carriers are in channel B. The mobility of the carriers in each channel is different due to the impurity doping in the GaAs layer adjacent to channel B and to the difference in surface roughness.

Therefore the mobility modulation can be achieved without changing the total carrier density in the GaAs well, by transferring the carriers between the two channels in response to the, switching potentials applied to the gate electrodes.

One transistor in accordance with the present invention does not have the same two channel and back-gate structure, although two gates are utilised. For the purposes of this discussion, the gate overlying the regrowth structure is called the first gate, or gate 1 (G1) and the gate (or gates) formed by the superlattice, the second gate, or gate 2 (G2). In the case where the superlattice comprises layers alternately doped to be of opposite conductivity types, there will be two second gates designated G2n and G2p respectively contacting the n-type layers and the p-type layers.

As will become apparent from a specific embodiment of a transistor according to the present invention which is described in detail hereinbelow, source and drain contacts from the surface to the 1DEG (quantum wire) is made via a 2DEG. As a result, shallow ohmic contacts or contact isolation by ion implantation is rendered inessential, greatly simplifying manufacture.

The materials of the respective superlattice layers should be chosen to allow application of the appropriate bias to G2 to induce one or more quantum wires in a desired plane of the regrowth structure.

As explained hereinbefore, an advantage of the present invention is to be able to induce quantum wires away from the primary regrowth surface. In the case where the superlattice comprises n-type and p-type layers this requires application of sufficient differential bias potential across the layers of opposite conductivity type. The higher the differential potential, the further away can the 1DEG be induced. The differential potential induced by the superlattice reduces with increasing distance from the regrowth interface.

Thus, there is a general requirement to be able to apply high bias voltages not only to induce quantum wires at the required distance from the interface but to keep the quantum wires as narrow as possible and to widen the gap between permitted states.

Depending on the choice of materials, it is possible to use a heterostructure for the superlattice in which one set of layers are undoped and, alternate layers are 6 doped (in a preferred embodiment, they are GaAs/n-GaAs). However, it is especially preferred to use alternate layers 6 doped to be of opposite conductivity type, ie. alternately p type/n type.

A transistor according to the present invention in the form of a VMT works by application of differential bias between alternate superlattice layers. The use of p/n 6 doping enables larger differential modulation to be applied, making it easier to ensure that the potential difference between adjacent superlattice layers at the regrowth interface (Vpn) is in the order of 1. 5eV or more. By varying the potential between the p and n planes, it is possible to modulate the quantum wire width so that the device operates as a VMT.

Increasing the reverse bias on the superlattice p layer causes quantum well narrowing, with consequent increase of sub-band spacing. If the voltage applied to the G2 layers is the same, ie. VG2n=VG2p, or if VG2n G2p (provided that VG2n-VG2p V -v is less G2n G2p than the forward bias turn-on voltage of the p-n junctions), then the quantum well is in the wider state (a) where the energy difference between lower (1) and a upper (2) sub-bands can be termed zEla2. When

well is in the narrowed state (b) Velocity modulation occurs if in state (a) AE12-KT and in state (b) 12 (b) AE12 KT because with the well narrow and the sub-bands widely spaced, the probability of thermal scattering into other states, which would reduce mobility, is greatly reduced.However, in this situation the population density of the sub-bands also changes which would limit modulation speed. Therefore, it is highly desirable to change the average bias to equilibrate the density.

This gives rise to the possibility of a negative differential resistance device. In such a device at a given applied voltage, excitation of hot carriers reduces the total number of carriers flowing, giving an apparent negative resistance in this region. Varying the source drain voltage can be used to vary the separation of energy levels and so 'tune' the critical voltage for onset of the negative resistance effect.

The basic velocity modulation effect may be further enhanced by putting a spacer layer of higher bandgap material between respective 6 doped n and p layers.

For example, if the 6 doped layers are p-GaAs and n-GaAs, Al GaAs spacer layers could be used to act as a barrier. Thus, higher differential bias may be applied across gates G2n and G2p.

If the 6 doped layers are p-AlGaAs and n-AlGaAs then aVpn can be increased with VG2n=VG2p. This enables the wires to be induced still further from the regrowth surface, eg. at the remote interface of the active layer, whilst utilizing lower bias potentials.

This may also be achieved by using modified bias conditions. This permits higher mobility electron gases, at least using conventional growth techniques.

Thus in summary, two basic forms of transistor can be realised, one with a single first gate (G1) overlying the active layer and a single second gate G2 formed by the superlattice. This functions as a regular FET. In operation, G2 is held at a fixed potential and G1 is varied to pinch off the 1DEG (or not), thus varying the number of carriers flowing.

In the second form there is a single first gate (G1) and two second gates (G2n and G2p) formed by the superlattice. This device can be operated as a regular FET or as a VMT.

As a regular FET, G2n and G2p may be at the same external potential or a different potential but in any case, the potential of both is fixed. G1 is then varied as with the transistor of the aforementioned first basic form.

Alternatively, to operate the transistor at the second form as a VMT, G2n and G2p are at all times at the same differential bias relative to each other but their average is varied relative to G1 which is held at fixed bias. However, it is possible to envisage a hybrid device in which the differential bias between G2n and G2p is varied but the average does not vary relative to G1.

The second basic form of transistor may also be operated as a negative differential resistance device, in which G2n and G2p are used to tune the quantum wire energy spacing and therefore to tune the source-drain voltage at which negative differential resistance occurs.

One preferred construction for devices according to the present invention, whether VMTs or regular FETs, forms the active layer as part of a conventional HEMT structure. However, this could be dispensed with. For example, instead the HEMT structure could be replaced by a simplified inverted HEMT structure such as a GaAs semi-insulating layer on top of which is grown a GaAs layer with an impurity concentration of 1x1017 cm on top of an AlGaAs semi-insulating barrier layer. The doped layer thickness will be dependent on the surface depletion layer. An AlGaAs layer grown on the superlattice may be covered with a further pair of thin Al GaAs layers, the lower of which is doped as above.

This allows depletion mode operation instead of enhancement mode.

This simplified device is especially easy to fabricate source/drain contacts can be made by. conventional GaAs shallow ohmic contact technology, eg. using Ge/Pd, or the like.

Whether a transistor device according to the present invention is fabricated as a regular FET, or as a VMT, the superlattice effectively functions as a gate of the device. Ohmic contact to the superlattice layers is conveniently effected by selective etching of a second angled facet during the patterning process.

Turning now to devices according to the present invention which are detectors of electromagnetic radiation, these may be adapted to be sensitive to a wide range of wavelengths, although depending on the mode of operation as described hereinbelow, they may be tuned to be sensitive only to a narrow band width within this wide range.

A fourth aspect of the present invention provides a detector of electromagnetic radiation, the detector comprising a superlattice, a barrier layer in contact with or adjacent to edges of a plurality of layers of the superlattice and an active layer in contact with or adjacent to the barrier layer, a front gate overlying the barrier layer and an electrical connection to a set of layers of the superlattice so that said set of layers can function as a back gate structure, said front gate and back gate structure being provided for varying the frequency response of said detector which is encapsulated in such a way as to be able to receive electromagnetic radiation.

Where the detector has alternately 6 doped n and p layers (as mentioned hereinbefore in respect of a VMT) to have separate back gates which are designated G2n and G2pi then the potential applied between the front gate (G1) and G2p can be used to determined the resonant frequency of the device and the potential between G1 and G 2n can be used to control sensitivity and bandwidth.

The variation of frequency response which may be effected may involve tuning of a (peak) frequency response and/or bandwidth variation (variation of upper frequency cut-off) depending on the construction and, therefore, mode of operation of the device as explained in more detail hereinbelow. The sensitivity of the device may also be varied.

The detectors may be adapted to operate at (say) microwave or infra-red (IR) wavelengths. However, devices of specific embodiments described hereinbelow are fabricated to operate as IR detectors. Such IR detectors may operate at from 0. 8 to 1000#, preferably from 5 to 500p but especially in the range of from 7 to 15#.

These detectors have three possible modes of operation and the electrical contacts necessary for each mode differ. It is, however, possible to provide sufficient appropriate contacts to allow the device to operate in two, or even all three modes.

Since the three modes of operation depend on conduction in different directions relative to the quantum wires, it is convenient to refer to them in terms of cartesian co-ordinates and so herein they are termed, respectively, x, y and z modes.

In x mode, the device operates such that the incident radiation excites carriers from the highest occupied level to the lowest unoccupied level such that a current flows along the quantum wires between a source and drain, parallel to the edges of the superlattice which contact the regrowth structure. Detection is indicated by a change in source to drain current. The energy difference aEx between the ground state and the next quantum energy level within the one dimensional quantum well determines the frequency at which detector is responsive according to Apex= hv.

Thus, in x mode the device has a narrow frequency response due to the peaked nature of the one dimensional density of states for each quantum level. Moreover, the response frequency is tunable by changing the potential applied between the G2n and G back gates and thus 2p changing the confinement in the one dimensional quantum well.

For x mode operation, the source and drain regions may be made by shallow ohmic contact to the buried active layer.

For y mode operation, the source and drain are arranged in orthogonal positions relative to those for x mode operation. Provided it is of sufficient energy, incident radiation excites carriers out of the 1D-wells so that they can move transverse to the quantum wires and the edges of the superlattice layers in contact with the regrowth structure. Given a DC bias applied between source and drain, the requirement for an increase in current flowing between source and drain is AE = y hv where AE is the minimum energy difference y between the ground state and the quasi continuum, i.e.

the tops of the 1D-wells.

This means that the detector responds to radiation having a frequency above a threshold value. However, this threshold value can itself be tuned in the same manner as for x mode operation.

For y mode operation, source and drain contacts are of the ohmic type.

Z mode operation actually has two possible sub-modes, depending on whether AE z < AE y or AEz > Ey.

In z mode operation, there is one electrical contact to a surface or contact layer of the regrowth structure (i.e. G1) and another to at least the back of relevant layers of the superlattice (i.e. G2n and Gawp~ probably G2n), i. e. to the surface remote from the regrowth surface. Contact is to those layers of the superlattice opposite the induced quantum wires. It will be appreciated that these contacts are the same as the "tuning" contacts for x and y mode operation.

For coupling with y mode operation, the source/drain contacts for x or y mode operation may or may not be present. However, for normal z mode operation (i.e.

without coupling) AEz > any If there are no ohmic source and drain contacts then the front "gate" (G1) must form an ohmic contact with the surface. If ohmic contacts are made to the source and drain then the contact to G1 should be Schottky type and the source and drain should preferably be in the orientation for x mode to provide for efficient current injection.

Provided that the energy of incident radiation is above a minimum threshold, carrier conduction can occur from the electron to the superlattice layers (i.e. G2n).

However, for z mode operation some kind of coupling (e. g. grating or prism) has to be provided to match the polarisation of the radiation to the quantum wire orientation.

The other z sub-mode can occur in the case where AE z < aE . In this mode, excitation occurs between y energy levels defined by the confinement potential provided by the G 2n and G2p gates. However, the conduction is via continuum levels in the z direction.

This form of z mode conduction does not require any external coupler to match polarization.

A wide range of different regrowth structures may be used, whether for a transistor or for a detector. The only requirement is the capability in inducing the quantum wires. Normally, the wires will be induced in an active layer sandwiched between a pair of barrier layers. Optionally, at least one of the barrier layers may comprise a spacer layer in direct contact with the active layer. If a contact is to be made to the top of the regrowth structure (for a detector), a contact layer will usually be the penultimate layer so that the upper barrier layer does not present an abrupt barrier to conduction between front and back gate electrodes. In the case of z mode operation in a device without source drain contacts, a graded contact layer is preferably used to "bridge" the bandgap between the cap layer and upper barrier layer in a progressive manner.This may be effected by stepped variation of Al during deposition of an AlGaAs layer. Otherwise, just a cap layer such as n -GaAs may be provided (in the case of a transistor).

Preferably, the active layer is GaAs and the barrier layer(s) will be AlGaAs or n-AlGaAs.

Other heterostructures may be used such as InP/InGaAs.

For InP/InGaAs/AlInAs structures, carriers will be confined in the InGaAs regions with InP or AlInAs serving as the barrier layers. The normal binary or quaternary analogues of these may be used.

GaSb/AlSb/InAs systems and their ternary equivalents may also be used, e.g. with AlSb barrier layers and InAs forming the active layer in which carriers are confined within the wells. Si/Ge is also possible, in which case the majority carriers are holes. In such a device Ge would constitute the active layer and Si would be used for the barrier layers. In place of Si in the latter system, oxygen implanted silicon may be used, sometimes known as "Simox". The barrier layers could also be made from other less usual wide band-gap materials such as GaN.

The present invention will now be explained in more detail by the following description of preferred embodiments and with reference to the accompanying drawings in which: Figure 1 shows a known semiconductor device; Figure 2 shows an energy band diagram for a conventional HEMT structure; Figure 3 shows an sectional view of a conventional back gated HEMT VMT structure; Figure 4 shows the operating principle of the conventional VMT shown in Figure 3; Figure 5A shows a sectional view of a VMT device according to a first embodiment of the present invention and Figure 5B shows an enlarged view of Figure 5A showing detail in the region of the HEMT/superlattice interface; Figure 6 shows a plan view of the device shown in Figures 5A and 5B;; Figure 7A shows a sectional view of an FET of a second embodiment of the present invention and Figure 7B shows an enlarged view of Figure 7A showing detail in the region of the HEMT/superlattice interface; Figure 8 shows a plan view of the device shown in Figure 7A and 7B; Figures 9A and 9B show band diagrams for the device shown at the second embodiment of the invention, illustrating the band structure parallel to the (311) direction through the regrowth region into the first growth region; Figure 10A shows a sectional view of a third embodiment of the present invention using an inverted HEMT regrowth structure and Figure lOB shows an enlarged view of Figure 10A showing detail of the regrowth interface; Figure 11 shows an alternative regrowth structure to that shown in Figures 10A and 10B;; Figure 12 shows a cross section through a preferred embodiment of an an infra-red detector according to the present invention; Figure 13A shows a plan view of the detector shown in Figure 12 with contacts for x mode operation; Figure 13B shows an energy band diagram for x mode operation; Figure 14A shows a plan view of the detector shown in Figure 12 with contacts for y mode operation; Figure 14B shows an energy band diagram for y mode operation; Figure 15A shows a cross sectional view corresponding to that of Figure 12 for explaining normal z mode operation; Figure 15B shows an energy band diagram for normal z mode operation; Figure 16 shows a cyclotron resonance plot showing tuning of the infra-red detector of Figure 17; and Figure 17 shows the structure of the infra-red detector used to obtain the plot shown in Figure 16.

Referring now to Figures 5A and 5B of the accompanying drawings, there is shown a VMT 31 according to a first embodiment of the present invention.

A first growth is performed on a (100) GaAs wafer 33 and consists of a p-GaAs buffer layer 35 (lem) followed by a 6 doped n-GaAs/p-GaAs superlattice 37 with a minimum superlattice period approximately twice the thickness of the first AlGaAs barrier layer to be formed during the regrowth. Finally a lym p-GaAs cap layer 39 is grown.

The wafer is then patterned, using standard photolithographic techniques and etched to expose angled facet 41, 43. The preferred crystal plane is the (311) as this gives the greatest device flexibility as the amphoteric doping behaviour of Si on (311) facets allows the regrowth of both p- or n-GaAs/AlGaAs layers depending on whether the regrowth occurs on the A or B plane. The (311) facets are exposed using a suitable etch.

Following the required surface preparation, an AlGaAs barrier layer 45 (eg > 100 A) is formed by regrowth on the angled facet 41. This is followed by a standard modulation doped HEMT structure 47. The HEMT structure comprises a GaAs active layer 49 (ca > 20 A) followed by a second AlGaAs layer 51 (ca. 200-400 A) then an n-doped AlGaAs layer 153 (ca 400 A), and finally a GaAs cap layer 55 (ca 100 A). The HEMT structure is overlayered with a first gate electrode 57.

Regrowth may be performed using standard MBE or MOCVD growth techniques. However for improved device performance, these layers are preferably grown by migration enhanced epitaxy (MEE) or atomic layer epitaxy (ALE). MEE growth is carried out by cycling the growth species one at a time, resulting in monolayer growth.

For this technique to work the substrate temperature must be low enough so that a complete bonded monolayer may be deposited without the need for an arsenic over-pressure. The time between each cycle is determined by the surface diffusion time of the deposited species. The low temperature results in less diffusion of contaminates with the growth plane. Also the interfaces tend to be much smoother resulting in less disorder and alloy scattering. ALE is the monolayer growth analogue of MOCVD.

An ohmic contact region 59 is diffused in the other angled facet 43 to make contact between a second gate electrode 61 and the 6 doped n-GaAs layers of the superlattice. To enable VMT operation a further gate electrode (not shown in Fig. 5) is provided to contact the p-GaAs layers of the superlattice. The second gate electrode may be isolated by means of an Si3N4 or other dielectric insulating layer 63.

In use, a 1DEG 65 is induced at the first GaAs/AlGaAs interface 67 by biasing the second gate 61 positive.

The standard modulation doped HEMT structure 47 induces a 2DEG at the second GaAs/AlGaAs interface 69, adjacent to the 1DEG. This is close enough to allow coupling between the two electron gases. The primary purpose of the 2DEG is to allow efficient contact to the 1DEG. In the region of interest, a negative bias is applied to the first gate 57, which depletes out the 2DEG.

By biasing the G2p gates sufficiently negative, the 2DEG at the second interface may be depleted out above the G2p gates. Thus a 1-D wire may be induced at the second interface above the G2n gates. This mode of operation requires that the source/drain contacts are shallow.

Figure 6 shows the same device in plan view. The first gate electrode 57 overlies the HEMT structure and has a mid portion 71 directly above the region where the quantum wires 65 are induced which constitutes a channel region. The source 73 and drain 75 electrodes are located at opposite ends of the channel region. A further second gate 62 provides separate ohmic contacts for p-doped layers of the superlattice. Thus, there are two second gates G2n(61) for the n-type 5 doped layers and G2p(62) for the p-type.

For VMT operation, the first gate 57 (G1) is held at a fixed potential and the potential applied to G2n and G2 p are varied as hereinbefore described. For operation as a normal FET, G2n and G 2p are held at a fixed potential and the voltage applied to G1 is varied.

Figures 7A and 7B show a second embodiment of the invention. This is analogous to that shown in Figures 5A and 5B but it is a regular FET, not a VMT. Instead of using alternate p- and n- 5 doped GaAs layers interspersed with undoped layers, alternate undoped and n-type 6 doped layers are used in the superlattice.

The first growth is again performed on a (100) GaAs wafer 133 but consists of a p-GaAs buffer layer 135 (lem) followed by a 6 doped n-GaAs superlattice 137 with a superlattice spacing according to the rule of thumb given above for the first embodiment. AlFm p-GaAs layer 139 is grown as the cap layer.

The wafer is then patterned as before and etched to expose angled facets 141, 143. The (311) facets are exposed using a hydrofluoric acid based etch.

Again, an AlGaAs barrier layer 145 ( > 100A) is formed by regrowth on the angled facet 141, followed by a standard modulation doped HEMT structure 147, comprising GaAs active layer 149 (ca > 20 A), second AlGaAs layer 151 (ca. 200-400 A), n-doped AlGaAs layer 153, (ca 400 A) and GaAs cap layer 155 (ca 100 A). The HEMT structure is overlayered with a first gate electrode 157.

In this case, the ohmic contact region 159 is diffused in the other angled facet 143 to make contact between a single second gate electrode 161 and the doped n-GaAs layers of the superlattice. The second gate electrode may be isolated by Si3N4 or other dielectric insulating layer 163.

Figure 8 shows the device of the second embodiment in plan view. There is no further second gate contacting the undoped layer of the superlattice. The first gate pinches off the 2DEG 177 in the central part of the channel region.

The advantages of forming the HEMT structures on the patterned surface will now be apparent. However, unlike the situation which would occur if regrowth were performed on a cleaved surface, the second growth direction is not necessarily perpendicular to the first growth direction. This results in less confinement of the 1DEG.

For the device according to the second embodiment of the present invention, Figure 9A and 9B shows schematic band-structure diagrams parallel to the second growth direction (311), bisecting a 5 doped (Figure 8A) and an undoped (Figure 8B) region of the first growth. The 1 dimensional confinement is produced by the non-homogeneous electric field within the (311) plane induced by the 6 doped layers. The extent of the confinement may be controlled by the 6 doping layer width and the distance between the regrowth interface and the first GaAs/AlGaAs interface.

It can be noted that Figure 9A shows the band-structure bisecting a 6 doped n-GaAs layer. The induced 1DEG at the first GaAs/AlGaAs interface is apparent. Away from the 6 doped regions the GaAs conduction band minimum (Figure 9B), no longer crosses the Fermi level, thus there is no induced mobile charge. Note that in these diagrams, the 2DEG is pinched off.

The confinement may be further increased by separating the 6 doped n-GaAs regions by 6 doped p-GaAs regions. This increases the variation in the electric field parallel to the (311) plane. The main advantage of this structure is that the electron gas is removed from the regrowth interface and thus is less likely to be scattered or depleted by charged contaminates at the interface, provided that there is insignificant contamination riding with the growth interface.

The steps in production of devices of the first and second embodiments will now be described in more detail.

In order to expose the (311) facets on (100) wafers, a reliable etch is required. The etch should be able to expose as many different planes as possible.

A suitable wafer preparation technique must be used in order to prepare the wafer for regrowth.

Regrowth on pattered substrates requires the ability to etch the (100) GaAs wafer (or any other GaAs wafer such as (111)) to expose predetermined facets such as the (311). There are a number of GaAs etches, which all give different sidewall profiles. The etch should result in a linear sidewall ramp with a given angle to the (100) plane which is not dependent on whether the mask stripe direction is aligned parallel or perpendicular to the (110) direction.

Figures 10A and 10B show a third embodiment of the present invention. This is generally analogous to that shown in Figures 5A and SB except that in place of the standard modulation doped HEMT structure, an inverted HEMT structure 181 is formed by regrowth.

Above angled facet 41 of the superlattice 37 is grown on AlGaAs semi-insulating layer 89 ( > 100A), then a GaAs semi-insulating layer 91 (2000 A) and finally, an n-GaAs layer 93 (1000 A) preferably with a doping level just sufficient to be completely depleted by 17 -3 surface Fermi level pinning (eg lox10 cm ). This has the advantage of facilitating the use of GaAs shallow ohmic contacts.

Otherwise in Figures 10A and 10B, the same reference numerals are used to designate the same features shown in Figures 5A and 5B. Similar variants for the regrowth structure are shown in Figure 11.

In this variant, the regrowth consists of AlGaAs (600-800A) layer 95 n-AlGaAs (100A-200A) layer doped with lxl017cm Si impurities 97 and a final AlGaAs (200A) layer 98. This is all covered with a 2000A GaAs layer 99 so that a 1DEG can be induced at the interface with the upper AlGaAs layer. The impurity level in the doped layer is determined by the zero bias charge required and in the case quoted above corresponds 11 -2 to a carried density of ca. 1. 2x10 cm Turning now to Figure 12, there is shown an infra-red detector 101 comprising a superlattice 103 of alternately 8doped p-type layers 105 and n-type layers 107 etched to form a regrowth interface 109.

There is a first electrical connection (not shown) to the n-type layers 107 as G2n (back gate) and another (not shown) to the p-type layers 105 as G 2p (other back gate).

Successively grown on the regrowth interface 109 are a back barrier layer 111 of ca. 150 A GaAs, an active or well layer 113 of 30 A AlGaAs, Si 6 doped at > ca. 1x1011cm#2, a a front barrier layer 115 of 1000A AlGaAs or as an AlAs/GaAs short period superlattice. A Schottky metal contact 119 is evaporated onto the contact layer as a front gate. In operation, quantum wires 121 (into the plane of the paper) are induced in the active layer 113. The top Al GaAs layer would be doped sufficiently to negate the influence of surface pinning on the active well layer 113.

Operation in x mode will now be explained with reference to Figures 13A and 13B.

As shown in Figure 13A, x mode source 123 and drain 125 contacts are arranged to contact the quantum wires towards respective ends thereof. Figure 13B shows the energy bands in cross-section through the 1D-wells. The current transport direction is denoted by arrow 127.

Incident radiation of a frequency corresponding to the energy difference AEx between the lower (Eo) and upper (E1) quantised energy states within the well will cause a change in conduction along the quantum wire. However, increasing the potential difference applied between the two back gates increases the confinement thereby increasing aEx and therefore the response frequency.

Figure 14A shows the arrangement for y mode operation and the corresponding energy diagram is shown in Figure 14B.

As shown in Figure 14A, y mode source 129 and drain 131 electrodes are situated either side of the quantum wires. Under the influence of a source-drain bias, radiation with a frequency of at least to aEy (where AE is the energy difference between the ground y state Eo and the next excited state near the top of the 1D wells) allows conduction from source to drain across the quantum wires (see also Figure 14B). In this case, the direction of current transport is indicated by arrow 133.

Figure 15A is a view corresponding to Figure 12 for explaining normal z-mode operation. Current is arranged to flow from the front gate 199 to the back gate 105 if the frequency of incident radiation is high enough. The current transport direction is shown by arrow 135.

As shown in Figure 15B, if the IR radiation has sufficient energy, electrons from the ground state have sufficient energy to overcome the well lattice energy.

Under the influence of an applied bias, conduction may then occur from the front gate 199 to the back gate 105.

To demonstrate the turnability of an IR detector using the structure shown in Figure 17, cyclotron resonance spectra were plotted for irradiation with a laser at a fixed frequency equivalent to an energy of 10.5meV. As shown in Figure 17, this IR detector 141 has a structure analogous to the VMT as shown in Figure 5A. On a substrate 143 were grown a superlattice 145 comprising 6 doped layers p-GaAs 7500A (147), n-GaAs 1000A (149), p-GaAs 2000A (151), n-GaAs 1000A (153) and p-GaAs 5000A (155). The superlattice is covered with a regrowth structure 157which comprises a 1300A Al GaAs barrier layer 161 on the regrowth interface 163, a 700A GaAs active layer 165 and finally a conventional HEMT structure 167 with 200A spacer layer..

By varying the gate voltage, as shown in Figure 16, it can be seen that the absorption peak for the active layer shifts. This is equivalent to a change in confinement energies oo as follows: Vp=+0.5V xO=0.66meV Vp=+0.4V #0=1.52meV Vp=+0.3V xo=1.58meV Vp=+0.2V xo=2.05meV vp=+0. 1V =2. 12meV Vp=0.0V 6) o=2 55meV In the light of this disclosure, modifications to the described embodiments as well as other embodiments, all within the scope of the present invention as defined by the appended claims will now be apparent to persons skilled in the art.

Claims

1. A semiconductor device comprising an active layer and a barrier layer regrown on a patterned wafer in the form of a superlattice wherein the active layer is adjacent to or in contact with the barrier layer and the barrier layer is adjacent to or in contact with the superlattice so that respective biasing of the superlattice layers induces at least one quantum wire in or adjacent to the active layer and capable of conduction in a direction parallel to the superlattice edges whilst in contact with the barrier layer.

2. A semiconductor device comprising a superlattice on a substrate, the superlattice comprising a plurality of layers, the superlattice having an angled facet, a barrier layer being provided on or adjacent to said angled facet and an active layer on or adjacent to said barrier layer.

3. A semiconduictor device according to claim 2, wherein at least some of the layers of the superlattice are 6 doped.

4. A semiconductor device according to claim 2 or claim 3, wherein there is substantially no dopant diffused from the superlattice into the active layer or the barrier layer.

5. A semiconductor device according to any of claims 2 to 4, wherein the angled facet is oblique to the plane of the substrate.

6. A semiconductor device according to any preceding claim, wherein one set of alternate layers of the superlattice are 6 doped to produce a first predetermined conductivity type.

7. A semiconductor device according to claim 6, wherein the other alternate layers of the superlattice layer are 6 doped to produce a second conductivity type different from said first conductivity type.

8. A semiconductor device according to claim 7, wherein all of the superlattice layers are 6 doped GaAs.

9. A semiconductor device according to claim 7, wherein all of the superlattice layers are 6 doped AlGaAs.

10. A semiconductor device according to claim 7 or claim 8, wherein spacer layers are located between successive 6 doped layers and the spacer layers are formed of a material having a wider bandgap than that of the 8 doped layers.

11. A semiconductor device according to any preceding clam, wherein the active layer forms part of an HEMT structure regrown on the superlattice.

12. A semiconductor device according to any preceeding claim, further comprising at least one front gate electrode overlying the active layer and an electrical contact to a first set of the superlattice layers to function as a first back gate.

13. A semiconductor device according to claim 12, further comprising an electrical contact to a second set of the superlattice layers, alternating with those of the first set, to function as a second back gate.

14. A semiconductor device according to any preceeding claim, further comprising source and drain regions.

15. A semiconductor device according to claim 14, in which device said source and drain regions are provided with respective Schottky barrier electrode contacts.

16. A semiconductor device according to claim 15, in which device, said source and drain regions extend substantially parallel to the edges of the superlattice layers which are adjacent to or in contact with the active layer and are spaced apart with respect to said edges.

17. A semiconductor device according to any of claims 1-14, in which device said source and drain regions are formed by respective ohmic contacts with said active layer.

18. A semiconductor device according to claim 15 or claim 17, in which device said source and drain regions extend substantially perpendicular to those edges of the superlattice layers which are adjacent to or in contact with the active layer and are spaced apart with respect to the length of said edges.

19. A semiconductor device according to any preceeding claim, configured to function as a detector of electromagnetic radiation.

20. A semiconductor device according to any preceeding claim, configured to function as a transistor.

21. A detector of electromagnetic radiation, the detector comprising a superlattice, a barrier layer in contact with or adjacent to edges of a plurality of layers of the superlattice and an active layer in contact with or adjacent to the barrier layer, a front gate overlying the barrier layer and an electrical connection to a set of layers of the superlattice so that said set of layers can function as a back gate structure, said front gate and back gate structure being provided for varying the frequency response of said detector which is encapsulated in such a way as to be able to receive electromagnetic radiation.

22. A detector according to claim 21, wherein the back gate structure comprises two separate back gates constituted by alternate p- and n-doped layers respectively.

23. A detector according to claims 21 or 22, further comprising source and drain regions.

24. A detector according to any of claims 19 or 21-23, adapted to be responsive to infra-red radiation.

25. A method of manufacturing a semiconductor device, the method comprising the steps of: growing a superlattice structure on a substrate, the superlattice comprising a plurality of layers at least some of which are 5 doped; selectively etching said superlattice structure to form an angled facet; forming a barrier layer by regrowth on or adjacent to said angled facet; and forming an active layer on or adjacent to said barrier layer.

26. A method according to claim 25, wherein the angled facet is formed oblique to the plane of said substrate.

27. A method according to claim 25, wherein said step of selective etching forms a second angled facet for making a gate electrode contact to the superlattice.

28. A method of operating a semiconductor device according to claim 6 or claim 12, comprising varying the potential applied to a first gate overlying the active layer and holding a second gate constituted by the superlattice at a fixed potential.

29. A method of operating a semiconductor device according to claim 7 or claim 13, comprising varying the potential applied to a first gate overlying the active layer and holding two gates constituted by the superlattice at fixed potentials which are the same or different.

30. A method of operating a semiconductor device according to claim 7 or claim 13, comprising holding a first gate overlying the active layer at a fixed potential and varying the average potential applied to two gates constituted by the superlattice but with the same magnitude of differential potential applied to said two gates.

31. A method of operating a semiconductor device according to claim 7 or claim 13, comprising applying a voltage or voltages to two gates constituted by the superlattice to determine a source-drain voltage at which negative differential resistance occurs.

32. A method of operating a semiconductor device according to any of claims 7, 12, 21 or 22, comprising applying a potential between a first gate overlying the active layer and a second gate structure constituted by the superlattice, and measuring the current flowing between the first gate and second gate structure to detect the electromagnetic radiation, the potential between gates of the second gate structure being chosen to determine the frequency response of detection.

33. A method of operating a semiconductor device according to claim 13 when dependent on claim 6 or claim 11, or according to claim 21 or claim 22, comprising applying a potential between a first gate overlying the active layer and a second gate structure constituted by the superlattice and measuring the current flowing between the source and drain regions, the potential between gates of the second gate structure being chosen to determine the frequency response of detection.

34. A semiconductor device substantially as hereinbefore described with reference to any of Figures 5-15 or 17 of the accompanying drawings.

35. A transistor substantially as hereinbefore described with reference to any of Figures 5-11 of the accompanying drawings.

36. A detector of electromagnetic radiation, the detector being substantially as hereinbefore described with reference to any of Figures 6-15 or 17 of the accompanying drawings.

37. A method of manufacturing a semiconductor device, the method being substantially as hereinbefore described with reference to any of Figures 5-15 or 17 of the accompanying drawings.

38. A method of operating a semiconductor device, the method being substantially as hereinbefore described with reference to any of Figures 5-17 of the accompanying drawings.