GB2286719A

GB2286719A - Field effect transistors

Info

Publication number: GB2286719A
Application number: GB9402814A
Authority: GB
Inventors: Jeremy Henley Burroughes; David A Ritchie; Mark Levence Leadbeater
Original assignee: Toshiba Cambridge Research Centre Ltd
Current assignee: Toshiba Europe Ltd
Priority date: 1994-02-14
Filing date: 1994-02-14
Publication date: 1995-08-23
Anticipated expiration: 2014-02-14
Also published as: GB2286719B; GB9402814D0

Abstract

The transistor 1 comprises a back gate layer 7 formed in a substrate 3 having a recess intersecting an edge of the back gate layer. The recess extends from an upper surface to a recessed surface 17 of the substrate. A conduction layer 19 including a channel region 29 is formed over at least part of the recess to cover the edge of the back gate layer 7. Source 23 and drain 27 regions are formed in the conduction layer 19 respectively in the vicinity of the recessed and upper surfaces. A front gate electrode 37 overlies the conduction layer between the source and drain regions. Conduction between the source and drain electrodes is controlled by applying a bias potential to the back gate layer 7. <IMAGE>

Description

SEMI CONDUCTOR DEVICE The present invention relates to a novel semiconductor device, and in particular, a field effect transistor.

There have been several proposals for transistors which operate by modifyina the flow of carriers in a so-called two-dimensional electron gas (2DEG), between implanted source and drain regions. These either function in the manner of a conventional field effect transistor by pinching-off the current or by modulating the velocity of the carriers.

The progressive trend in ultra high scale integration means there is a constant demand for new technologies enabling still greater miniaturisation of high speed switching devices. At the same time, the desire to fabricate ever larger numbers of complex devices on a single substrate requires devices which can be manufactured by relatively simple processes, rather than using electron beam/X-ray lithography which is expensive and relatively slow.

A new form of device has now been devised which in the form of a field effect transistor which utilises an electron gas and has gate lengths down to the limits of metal-organic chemical vapour deposition (MOCVD) growth resolution, e. g. 0. 1 Fm or less.

Thus, the present invention provides a semiconductor device comprising a back gate layer formed in a substrate having a recess intersecting an edge of said back gate layer, said recess extending from an upper surface to a recessed surface of said substrate, a conduction layer formed over at least part of said recess to cover said edge of said back gate layer, source and drain regions being formed in said conduction layer respectively in the vicinity of said upper and recessed surfaces, and a front gate electrode overlying said conduction layer between said source and drain regions.

Devices according to the present invention are conveniently fabricated by doping of the substrate, performing selective etching and subjecting the etched substrate to regrowth to form the overlying conduction structure. Thus, the device can be formed without resort to electron beam lithography or other difficult techniques. Any epitaxial growth technique may be used, for example MOVPE.

The conduction layer is provided in a regrowth structure in which a 2DEG can be induced substantially parallel to the edge of the back gate layer by application of a potential bias to the front gate to allow conduction between the source and drain regions.

Application of an appropriate bias potential to the back gate layer can then deplete-out the 2DEG in the vicinity of the edge.

Optionally, a relatively thin shield layer may be provided over the regrowth surface, having a conductivity type opposite to that of the conduction layer, in order to enable operation in depletion mode instead of enhancement mode. This is especially applicable to embodiments where the conduction layer is relatively thin and the degree of depletion would be so great that very large gate potentials would be necessary to turn-off conduction between source and drain.

Preferably, screening layers are provided above and below the back gate layer to shape the depleting potential. No bias is normally applied between the back gate and focusing layers so capacitance effects which may occur in some other doped structures are avoided.

The device may be formed with appropriately doped silicon or germanium layers, especially for operation at room temperature. In fact, semiconductor material may be used for the conduction layer, for example, Si, Ge, GaAs, AlGaAs, InAs, InGaAs or AlSb with appropriate doping. In general, the regrowth structure as a whole may comprise a heterostructure comprising any combination of such materials capable of allowing induction of a 2DEG near the boundary interface.

The present invention will now be explained in more detail by means of the following description of a preferred embodiment and with reference to the accompanying drawing, in which Fig. 1 shows a cross-section through a field effect transistor according to the present invention.

As shown in Figure 1, an FET comprises an Si substrate 3 which is doped to form in order above one another, a first n-doped Si layer 5 of 500A thickness, a p-doped Si back gate layer 7 of 1000A thickness, a second n-doped Si layer 9 of 500A and an undoped Si top layer 11. The latter structure is selectively etched to form an obliquely inclined surface 13 intersecting all of the aforementioned layers, penetrating a predetermined distance below the bottom of the first n-doped layer 5 down to a lower etched surface 17 substantially parallel with the doped layers.

Onto this structure is grown a p Si layer 19 so that the inclined surface 13 forms an interface therewith. The upper surface 21 of that part of the p Si layer 19 which overlies the lower etched surface 17 is implanted with impurities to form an n-doped source region 23. The upper surface 25 of the p Si layer 19 which overlies the undoped top Si layer is similarly implanted to form an undoped drain region 27.

The inclined portion 29 of the p Si layer 19 which is formed on the interface surface 13 and spans the source and drain regions constitutes a channel region. A source electrode 31 is formed in electrical contact with the source region 23 and a drain electrode 33 is formed in electrical contact with the drain region 27. The remainder of the exposed surface of the p Si layer 19 between the source and drain contacts is covered with a silicon oxide insulating layer 35. A front gate electrode 37 is formed over this insulating layer above the inclined channel region 29.

In use, a positive bias is applied to the front gate electrode to form an inversion layer 39 in which a 2DEG is formed allowing conduction between the source and drain electrodes. However, if a bias potential is applied to the back gate layer 7, then the 2DEG in a region 41 immediately opposite the back gate layer is depleted-out, thus interrupting conduction. In this way, the device functions as a miniaturised high-speed switching device wf a pulsed signal is applied to the back gate layer.

In the light of this disclosure, modifications of the described embodiment, as well as other embodiments, all within the scope of the invention as defined by the appended claims, will now become apparent to persons skilled in the art.

Claims

CLAIMS:

1. A semiconductor device comprising a back gate layer formed in a substrate having a recess intersecting an edge of said back gate layer, said recess extending from an upper surface to a recessed surface of said substrate, a conduction layer formed over at least part of said recess to cover said edge of said back gate layer, source and drain regions being formed in said conduction layer respectively in the vicinity of said upper and recessed surfaces, and a front gate electrode overlying said conduction layer between said source and drain regions.

2. A device according to claim 1, wherein said substrate is formed of Si, said back gate is of a first conductivity type, and said conduction layer is also of said first conductivity type but having a lower impurity concentration.

3. A device according to either preceding claim, wherein upper and lower screening layers are provided respectively above and below said back gate layer.

4. A device according to claim 3, when dependent upon claim 2, wherein said screening layers have a second conductivity type opposite to said first conductivity type.

5. A semiconductor device substantially as hereinbefore described with reference to the accompanying drawings.

6. A method of manufacturing a semiconductor device according to any of claims 1 to 4, the method comprising doping said substrate to form the back gate layer, selectively etching the substrate to form said recess to expose said edge of the back gate layer, forming the conduction layer by regrowth over said recess and forming said source and drain regions.

7. A method of manufacturing a semiconductor device, the method being substantially as hereinbefore described with reference to the accompanying drawing.