GB2270221A - Adaptive IC output driver circuit - Google Patents

Abstract

An IC driver circuit has first and second switch circuits 25, 60 for connecting an output terminal 18 to respective supply lines. At least one of the switch circuits 60 is digitally adjustable to vary the current flow and is coupled to a control circuit. The control circuit has a reference signal generator 61 indicating a reference voltage/time variation and threshold circuitry 67 for detecting voltage at the output terminal 18 and generating a feedback signal 68 whose timing is compared with an equivalent signal 63 generated from the reference signal by threshold detector 62. Logic circuitry 72 is coupled to the comparison circuitry and holds a digital setting for the switch circuit 60 in dependence on the comparison between the reference and feedback signals. The setting may be altered subsequent to each downward edge. <IMAGE>

Description

IMPROVEMENTS IN OR RELATING TO IC OUTPUT DRIVERS The invention relates to output drivers for integrated circuit devices and methods of operating output drivers for such devices.

Integrated circuit devices are commonly used to generate output signals which are supplied from an output terminal or pad to a load circuit on a connected printed circuit board.

The high speed transmission of signals from an output pad of an IC chip to a load on a printed circuit board provides problems. Each time a signal is driven off-chip, the external load capacitance must be discharged or charged via the output driver circuitry and the inductance of the voltage supply lines. The inductance may be due to conventional features such as bond wires and lead frame as well as the output pin itself. The capacitance which has to be driven by the driver circuitry may be formed from a mixture of printed circuit board track capacitance, load capacitance of the device on the printed circuit board and other integrated circuit input or output capacitance. When designing an integrated circuit chip it is not possible to tell what load capacitances will have to be handled by the output driver circuitry of the chip.It will be understood that a large load capacitance will require large current flows to cause a fast change in logic level and smaller capacitances require much smaller currents to achieve the same speed of switching. The capacitance variation can easily vary from small capacitance loads such as 10 pF or larger values such as 300 pF. It will be understood that when an integrated circuit device is connected to a load on a printed circuit board the ground and power supply lines on the integrated circuit chip as well as the output pad connected to the load circuit on the printed circuit board will each be connected to circuits including inductance and capacitance such that resonance occurs when transmitting output signals from the output pad.Oscillations in voltage caused in this way may cause temporary-rise and fall in the voltage on the on chip power and ground supply lines (as well as on the power and ground tracks of the printed circuit board) herein referred to as power bounce and ground bounce. Furthermore oscillations on the output pad may result in overshoot or undershoot of the required signal level to which the output pad is being driven. The current needed in the driver circuits to meet a required signal transmission speed will of course depend on the capacitance of the circuitry to which the output pad is connected. However higher currents in the driver circuits will cause larger under or overshoot for the output voltage and possible power bounce and ground bounce in the voltage supply lines both on the chip and on the printed circuit board.The voltage generated in an inductive circuit is dependent on the rate of change of current through the circuit and consequently it is desirable to avoid excessive rates of current change in order to minimise the oscillation effects.

For many applications it is necessary to determine a worst case propagation delay for signals from the output to a load circuit on a printed circuit board. This has to be determined in advance of knowing the capacitance to which the output pad is connected. It also has to apply in a wide variety of environmental conditions such as temperature of operation and with circuit components which have been manufactured under a wide range of processes with inevitable process variation in transistor performance. It will be appreciated that the components must be designed to handle a large load capacitance with an acceptable propagation delay and on the other hand excessive under or overshoot of the output voltage must be avoided when the capacitance of the load is low.

It is an object of the present invention to provide an improved digital driver circuit for an IC output terminal which regulates current flow to an output terminal to achieve a controlled voltage/time variation at the output terminal.

The invention provides a method of controlling a driver circuit for an integrated circuit output terminal in which a switch circuit is used during a signal output cycle for connecting the output terminal to a supply line to change a voltage signal on the terminal to correspond to that of the supply line, which method comprises generating a reference voltage/time variation signal, detecting voltage at the output terminal during said output signal to generate a feedback voltage/time variation signal, effecting a comparison of the feedback signal with said reference signal, modifying a digital setting for said switch circuit in one signal output cycle in dependence on said comparison and using said digital setting after modification for controlling current flow through said switch circuit in a later signal output cycle.

Preferably said switch circuit is arranged to connect said output terminal to a ground line and the reference voltage/time variation signal is arranged to reduce ground bounce on said ground line when said switch circuit is operated.

Said switch circuit may include circuitry for connecting the output terminal to a power supply line and said reference voltage/time variation signal may be arranged to reduce power bounce on said power supply line when the switch circuit connects the output terminal to the power supply line.

Preferably said reference voltage/time variation signal is arranged to control current flow to said output terminal to reduce overshoot or undershoot of the voltage level required on said output terminal.

Said integrated circuit may be connected to a printed circuit board and said reference voltage/time variation signal may be arranged to reduce unwanted voltage and/or current signals supplied from the output terminal to a load on the printed circuit board.

In one embodiment modification of said digital setting is used to alter the switch circuit in the next signal output cycle which changes the voltage signal towards said supply line.

In a further embodiment modification of said digital setting during one signal output cycle is delayed for a predetermined plurality of cycles before altering the switch circuit.

The invention also provides a driver circuit for an integrated circuit output terminal which driver circuit comprises a first switch circuit to connect said terminal to a supply line of first potential to output a first value and a second switch circuit to connect said terminal to a supply line of different potential to output a second different value, at least one of said switch circuits being digitally adjustable to vary the current flow through the switch circuit and being coupled to a control circuit for controlling variation of current flow through the switch circuit, said control circuit having a reference signal generator for providing reference signals indicating a reference voltage/time variation, and comparison circuitry for detecting voltage at the output terminal at varying times when said one of the switches is operated, to generate a feedback voltage/time signal, comparing said feedback signals with said reference signals and providing a control signal, drive strength logic circuitry coupled to both the comparison circuitry and to said one of the switch circuits and arranged to hold a digital setting for said one of the switch circuits in dependence on said control signal thereby to vary the current through the switch circuit to obtain a desired relationship between said reference and feedback signals.

Preferably the switch circuit controlled by the output of the comparison circuitry is arranged to connect said output terminal to a ground line.

In one embodiment said comparison circuitry includes threshold detection circuitry responsive to said reference signal generator for setting upper and lower limits on the rate of change of output signal and said drive strength logic circuitry is operable to change said digital setting only when the feedback signal falls outside said upper and lower limits.

In one embodiment said drive strength logic circuit is coupled to a start up circuit to modify the rate of change of the digital setting during start up.

The invention includes an integrated circuit having a plurality of output terminals together with a printed circuit board having a load device connected to at least one output terminal on said integrated circuit device, the integrated circuit device having a driver circuit for said one output terminal which driver circuit is as aforesaid.

By use of a reference voltage/time variation signal in controlling the voltage/time variation at the output pad, it is possible to avoid excessive peak current and excessive rates of current change with time. In this way undershoot and overshoot as well as power bounce and ground bounce can be minimised. Furthermore by using components in generating the reference voltage/time signals which have a similar environmental variation to the switching circuit controlling current flow to the output pad, it is possible to provide automatic compensation in the reference voltage/time signals used to control current flow to the output pad.

Some embodiments of the invention will now be described by way of example and with reference to the accompanying drawings in which: Figure 1 shows a conventional manner of operating an output pad on an integrated circuit device connected to a load on a printed circuit board, Figure 2 shows schematically a modified integrated circuit device in accordance with the present invention for use with a printed circuit board of the type shown in Figure 1, Figure 3 shows more detail of a different embodiment of the invention.

Figure 1 shows an integrated circuit device 11 of conventional construction incorporating a logic circuit 12 and having a plurality of output pads 13. In this example the circuit comprises CMOS components supplied with power by a power supply line 14 of 5 volts and a ground supply line 15 of 0 volts. Output pads 16 and 17 are used for power supply and ground connection respectively to connected circuitry which in this case comprises a printed circuit board 20. The printed circuit board is of conventional construction having a load circuit 21 which is to receive output signals from an output pad 18 on the integrated circuit chip.The printed circuit board includes other circuitry 22 and both the load 21 and other circuitry 22 are connected to a power supply line 23 and ground line 10 which are connected respectively to the output pads 16 and 17 of the integrated circuit chip. It will be understood that the integrated circuit 11 will have many of its output pads connected to other circuitry in normal use but for simplicity only the operation of the output pad 18 will be described in this example. In order to output a logic signal from the logic circuit 12 a binary value will be output through an inverter 24 to the gates of both transistors 25 and 26. The transistors 25 and 26 are of opposite conductivity type and connected in series between the power supply line 14 and the ground line 15. The output pad 18 is connected to node 27 on the line between transistors 25 and 26.The pad input voltage supplied through the inverter 24 switches on one of the transistors 25 and 26 while switching the other off depending on the binary signal which is input to the inverter 24. If transistor 25 is switched on then the pad 18 is connected to the supply line 14 and disconnected from ground 15. If the binary input to the pad is of the opposite value then transistor 26 is switched on and transistor 25 is switched off so that the pad 18 is connected to the ground line 15 and disconnected from the power supply line 14. In this way pad 18 moves towards the voltage of either line 14 or 15 due to current flow through either transistor 25 or 26.In order to transmit the signal from the logic circuit 12 pad 18 has to develop a voltage value above or below a particular threshold in order to indicate the nature of the binary signal which is being output and that signal must be propagated through bond wires lead frame and PCB track before reaching the load 21 which is to respond to the output signal from the logic circuit 12. The circuitry both on chip and off chip to which the pads 16, 17 and 18 of the integrated circuit chip are connected will inevitably exhibit inductance capacitance and resistance and fast switching of current flows through these circuits in order to output appropriate binary signals by the pad 18 will result in oscillation leading to overshoot or undershoot of the required voltage on the output pad 18 as well as power bounce on the supply line 14 and ground bounce on the line 15.In the example shown in Figure 1 the driver circuit formed by the transistors 25 and 26 is an analog circuit and must be of sufficient current capacity to permit the change of voltage on the output pad 18 to propagate the required output signal to the load 21 within a sufficiently short delay regardless of variation in the load capacitance connected to the output terminal 18 and the environmental operating conditions and process conditions used in forming the circuit components.To cope with the worst case of slow operating components due to processes used in manufacture or operating environmental conditions as well as coping with the maximum capacitance to which the circuitry may be connected, the driver circuit must be sufficiently large in current capacity that when operating with a small capacitance load or with fast operating transistors or fast environmental conditions there is a risk of undershoot or overshoot damaging devices connected to the output pad 18 as well as excessive bounce on the supply and ground lines 14 and 15 which may cause the injection of noise into sensitive analog circuits.

Figure 2 illustrates an embodiment of the present invention in which similar reference numerals have been used for parts corresponding to those already described in Figure 1. In this case the printed circuit board 20 has merely been represented by circuits 30, 31 and 32 each including inductive capacitative and resistive elements connected respectively to the output pads 16, 18 and 17. A digital circuit is used in which transistor 25 of Figure 1 is replaced by a plurality of digital driver switches 59 controlled by a control circuit 33 and transistor 26 is similarly replaced by a plurality of digital driver switches 60 controlled by the output of a control circuit 34. The input signal to the pad is provided through inverter 24 as previously described and is supplied to each of the control circuits 33 and 34.Depending on the binary signal which is input, one or other of the control circuits 33 or 34 will be operated to switch on a controlled number of its associated switches 59 or 60 while the other is switched off. In this way the output pad 18 will be connected to the required one of the lines 14 or 15 but the number of conducting digital switches will be controlled to vary the current flow through the output 18 in dependence on the output signal from the respective control unit 33 or 34.

It will be appreciated that in Figure 2 separate control units 33 and 34 are provided for the respective switches 59 and 60 depending on whether the output pad 18 is to be driven high to the voltage of line 14 or low to the ground level of line 15.

In practice more problems occur in handling negative going edges of output signals where the output pad 18 is to be driven to ground. With positive going edges there is more headroom between Vdd and the output high voltage levels used for TTL threshold levels. Thereby less problems arise with power bounce than with ground bounce. Consequently embodiments may be provided as shown in Figure 3 in which the control on current flow is provided only for connecting the output pad 18 to the ground line 15. In this case the output of the inverter 24 is connected directly to the gate of transistor 25 and operates as previously described with reference to Figure 1 to connect the pad 18 to Vdd on an upward signal edge.It will be understood that in the control unit of Figure 3 it is equally possibly to provide a mirror replica of the control unit 34 shown in Figure 3 for controlling a plurality of switches 59 in place of the transistor 25 where it is desired to provide a reference voltage/time control signal for both upward and downward movement of the voltage on the output pad 18.

In Figure 3 the digital driver switches 60 incorporate a plurality of transistors which can be selectively switched on or off so that the number switched on corresponds with the digital control derived from a reference voltage/time signal.

In this case the output from inverter 24 is fed to a reference slope generator 61. This produces a reference voltage/time curve having a desired gradient to determine acceptable rates of change of voltage on the output pad 18. The voltage signal from that reference slope is fed to a threshold detector 62 which may be used to provide one or more signals indicating time delays necessary for the reference voltage in the signal generator 61 to change to a desired value. In this particular example the threshold detector 62 is arranged to provide two outputs 63 and 64 indicating respectively maximum and minimum times for the voltage to change between particular threshold values. These signals are fed to a timing comparator 65 arranged to receive feedback signals derived from detection of the voltage at the output pad 18.In this case a feedback signal from the pad 18 is supplied on line 66 to a further threshold detector 67 to indicate the time delays for the voltage on feedback line 66 to reach a particular threshold value. The timing comparator 65 then compares the input 68 from the threshold detector 67 with the reference upper and lower levels on lines 63 and 64.

The result of this comparison is used to determine the number of transistors in the driver switches 60 which are operated for the next or later downward going edges in the signal at the pad driver input 42. In this example a logic unit 72 is provided to store the current state of required drive strength and this is connected through output lines 73 to the digital driver switches 60 so as to operate a number of transistors in the switches 60 corresponding to the stored drive strength indicated by the logic unit 72. The timing comparator 65 is arranged to provide two outputs 70 and 71 to the logic unit 72. Signal 71 is actuated by the timing comparator 65 when it is required to alter the state stored in the logic unit 72 and signal 70 indicates whether the change in state is to be an increase or decrease in the drive strength required.The timing comparator 65 will receive signals on lines 63 and 64 which represent respectively fast and slow reference signals indicating the minimum and maximum acceptable times for the voltage level to change from one predetermined value to a set threshold value. If the comparator 65 determines that the signal 68 from the threshold detector 67 cross its threshold before the fast reference signal on line 63 then the outputs 70 and 71 are operated to cause the logic unit 72 to a lower drive strength state. Conversely, if the signal on line 68 does not indicate a crossing of the threshold value which is fast enough to match the slow reference signal on line 64 then the timing comparator 65 operates to change the logic 72 to increase the drive strength state.

It will be appreciated that the change in state of the drive strength logic 72 is not operative to alter the setting of the digital driver switch 60 during the downward going edge which has generated the feedback on line 66 to the threshold detector 67. The change of state is stored in the logic unit 72 and may be used for the next downward going edge on the input 42 or indeed it may be stored for longer and used for later downward going edges in the input signal 42. If the timing comparator 65 determines that the feedback signal on line 68 lies between the slow and fast reference signals on lines 63 and 64 then no adjustment is made to the drive strength set in the logic 72. In that case no output is provided on line 71 and consequently the logic 72 remains unchanged.Normally the change in drive strength due to one edge in the signal at the input 42 will only be a small increment or decrement to the drive strength state indicated by the logic 72. However during an initial start up sequence the increment or decrement size may be larger to allow a faster settling to the required drive strength. This is provided on line 74 which is a separate start up input to the logic 72 and allows more rapid change in the recorded state when a signal is provided on line 74.

The logic unit 72 may include a setting to determine a delay between its change of state and its output on line 73 to vary the number of downward going edges on input 42 before the state of the driver switches 60 is changed in accordance with the revised drive strength state indicated by logic 72. By delaying the change in switches 60 beyond the next downgoing edge after the one which caused the revised state of the logic 72 it is possible to reduce the likelihood of the timing comparator 65 adopting a metastable state with indecision on whether the logic state 72 is to be increased or decreased.

Due to the finite adjustment in the setting of the driver switches 60 which is made in response to the change in state of the logic 72 after any single edge, the circuitry may require the output of several edges of output signal before the digital circuitry establishes the correct delay through variation of the number of switches operated in unit 60. This may be dealt with by allowing the pad driver to set itself up during an initial startup period by ignoring the first few outputs from the output pads or alternatively by designing the pad to start too fast or too slow depending upon the arrangement that the particular application can tolerate best. Then the speed may be increased or decreased as necessary during the next few output cycles. Once the adjustment has been made to obtain a delay at the output pad which falls within the acceptable limits set by the reference system then further adjustment may be made on each output cycle or once every N ns or X clock cycles. If it is required to make adjustments to compensate for ambient or integrated circuit temperature conditions or supply voltage variations then more regular monitoring is necessary.

The invention is not restricted to the details of the foregoing example.

Claims (15)

CLAIMS:

1. A method of controlling a driver circuit for an integrated circuit output terminal in which a switch circuit is used during a signal output cycle for connecting the output terminal to a supply line to change a voltage signal on the terminal to correspond to that of the supply line, which method comprises generating a reference voltage/time variation signal, detecting voltage at the output terminal during said output signal to generate a feedback voltage/time variation signal, effecting a comparison of the feedback signal with said reference signal, modifying a digital setting for said switch circuit in one signal output cycle in dependence on said comparison and using said digital setting after modification for controlling current flow through said switch circuit in a later signal output cycle.

2. A method according to claim 1 in which the switch circuit comprises a plurality of switchable device and the step of comparing the reference signal with the feedback signal comprises a digital comparison to generate a digital signal to control the number of switchable devices which are switched on or off in the switch circuit.

3. A method according to claim 1 or claim 2 in which said switch circuit is arranged to connect said output terminal to a ground line and the reference voltage/time variation signal is arranged to reduce ground bounce on said ground line when said switch circuit is operated.

4. A method according to any one of claims 1 to 3 in which said switch circuit includes circuitry for connecting the output terminal to a power supply line and said reference voltage/time variation signal is arranged to reduce power bounce on said power supply line when the switch circuit connects the output terminal to the power supply line.

5. A method according to any one of the preceding claims in which said reference voltage/time variation signal is arranged to control current flow to said output terminal to reduce overshoot or undershoot of the voltage level required on said output terminal.

6. A method according to any one of the preceding claims in which said integrated circuit is connected to a printed circuit board and said reference voltage/time variation signal is arranged to reduce unwanted voltage and/or current signals supplied from the output terminal to a load on the printed circuit board.

7. A method according to any one of claims 1 to 6 in which modification of said digital setting is used to alter the switch circuit in the next signal output cycle which changes the voltage signal towards said supply line.

8. A method according to any one of claims 1 to 6 in which modification of said digital setting during one signal output cycle is delayed for a predetermined plurality of cycles before altering the switch circuit.

9. A driver circuit for an integrated circuit output terminal which driver circuit comprises a first switch circuit to connect said terminal to a supply line of first potential to output a first value and a second switch circuit to connect said terminal to a supply line of different potential to output a second different value, at least one of said switch circuits being digitally adjustable to vary the current flow through the switch circuit and being coupled to a control circuit for controlling variation of current flow through the switch circuit, said control circuit having a reference signal generator for providing reference signals indicating a reference voltage/time variation, and comparison circuitry for detecting voltage at the output terminal at varying times when said one of the switches is operated, to generate a feedback voltage/time signal, comparing said feedback signals with said reference signals and providing a control signal, drive strength logic circuitry coupled to both the comparison circuitry and to said one of the switch circuits and arranged to hold a digital setting for said one of the switch circuits in dependence on said control signal thereby to vary the current through the switch circuit to obtain a desired relationship between said reference and feedback signals.

10. A driver circuit according to claim 9 in which said comparison circuitry includes a digital comparator for comparing the reference and feedback signals and said switch circuit comprises a plurality of switch devices connected to an output of the comparator to vary the number of switch devices which are switched on or off.

11. A driver circuit according to claim 9 or claim 10 in which the switch circuit controlled by the output of the comparison circuitry is arranged to connect said output terminal to a ground line.

12. A driver circuit according to any one of claims 9 to 11 in which said comparison circuitry includes threshold detection circuitry responsive to said reference signal generator for setting upper and lower limits on the rate of change of output signal and said drive strength logic circuitry is operable to change said digital setting only when the feedback signal falls outside said upper and lower limits.

13. A driver circuit according to any one of claims 9 to 12 in which said drive strength logic circuit is coupled to a start up circuit to modify the rate of change of the digital setting during start up.

14. An integrated circuit having a plurality of output terminals together with a printed circuit board having a load device connected to at least one output terminal on said integrated circuit device, the integrated circuit device having a driver circuit for said one output terminal which driver circuit is as claimed in any one of claims 9 to 13.

15. A driver circuit for an integrated circuit device which driver circuit is substantially as hereinbefore described with reference to any of the accompanying drawings.