GB2267201A - Display Systems for displaying a Series of sequentially occurring Displays - Google Patents

Abstract

The invention finds particular application in radio testing equipment. There is known radio testing equipment wherein the updating by a display system thereof of the displays of a series of sequentially occurring displays provided in testing by the equipment, is undesirably slow. The present invention provides a display system which overcomes this problem. The invention has four aspects. in the first aspect the present invention provides a display system having a dual processor architecture wherein one processor (49, 51) modifies a drawing sequence executed by the other processor (53, 55). In the second aspect the present invention provides a display system which, to display each next display of the series, modifies the contents of memory locations for a previous display by addressing and changing the contents of substantially only those memory locations the contents of which is required to be different for the next display to the previous display. In the third aspect the present invention provides a display system wherein the characterisation of each pixel (65) of a display screen (61) is determined by a number stored in a corresponding memory location of a memory (55), and each number comprises a number of parts each of which corresponds to a respective one of a plurality of distinct features comprising each display. In the fourth aspect the present invention provides a test equipment which, with a view to providing a series of frequency spectrum displays, includes a frequency synthesiser (203, 205 or 301, 303) which steps the frequency generated thereby. The synthesiser (203, 205 or 301, 303) indicates when each frequency is achieved by providing a synchronisation signal to a display system (21, 23, 25) which in response to receipt thereof receives a further signal in the provision of which the frequency was utilised. <IMAGE>

Description

Display Systems for displaying a Series of sequentially occurring Displays This invention relates to display systems for displaying a series of sequentially occurring displays.

The invention finds particular application in radio testing equipment.

There is known radio testing equipment which tests the following two modes of operation of a duplex radio system. The receive mode, wherein the quality of reception by the radio system of audio modulated radio frequency (r.f.) signals is tested, in particular the quality of demodulation by the radio system of a received audio modulated r.f. signal to produce an audio output of the radio system is tested. The transmit mode, wherein the quality of transmission by the radio system of audio modulated r.f. signals is tested, in particular the quality of modulation by the radio system of a received audio signal onto an r.f. carrier to produce an audio modulated r.f. output of the radio system is tested.

A display system of the known equipment provides in the testing of each mode of operation a series of sequentially occurring waveform displays, each of which displays, apart from the first occurring, is the update of the display previously occurring in the series. In testing the receive mode of operation, the updating is in response to the audio output of the radio system. In testing the transmit mode of operation, the updating is in response to the audio modulated r.f. output of the radio system. A user of the known equipment interprets the displays to aid in the determination of the quality of reception/transmission.

A problem with the known equipment is that the updating by the display system thereof of the displays of the series is undesirably slow.

It is an object of the present invention to provide a display system for displaying a series of sequentially occurring displays wherein the above problem is overcome.

According to a first aspect of the present invention there is provided a display system for displaying a series of sequentially occurring displays comprising: means for acquiring data values for each said display; first processor means for modifying for each said display a sequence of drawing instructions for said displays in dependence on the data values acquired for that said display; and second processor means for executing for each said display the sequence of drawing instructions modified for that said display.

According to a second aspect of the present invention there is provided a display system for displaying a series of sequentially occurring displays, each of which comprises a waveform and is displayed on a display screen of the system comprising an array of rows and columns of pixels, whether or not each of which pixels is characterised by the system being determined by the contents of a corresponding memory location of a memory of the system for storing said displays, said system displaying each waveform by characterising all the pixels of each column from and including a first pixel of the column to and including a second pixel of the column, said display system displaying each next display of the series by modifying the contents of the memory locations for a previous display by addressing and changing the contents of substantially only those memory locations the contents of which is required to be different for the next display to said previous display.

According to a third aspect of the present invention there is provided a display system for displaying a series of sequentially occurring displays each of which comprises a plurality of distinct features, said display system comprising: a display screen comprising an array of rows and columns of pixels on which display screen said sequentially occurring displays are displayed; a memory for storing said displays, the characterisation of each pixel of said display screen being determined by a number stored in a corresponding memory location of said memory, which number is one of a series of numbers each of which comprises a number of parts equal to the number of said distinct features each part corresponding to one distinct feature; look-up table means for storing in respect of each number of the series a digital value for a video output of the look-up table means; and processor means for modifying for a subsequent display of said series one or more of said number of parts of the number stored in each memory location of said memory, said processor means thereby modifying for the subsequent display the distinct feature(s) corresponding to the part(s) of each number modified, said modification of the part(s) of each number being made independently of the remaining part(s) of the number.

According to a fourth aspect of the present invention there is provided a test equipment comprising: a display system for displaying a series of sequentially occurring displays each of which comprises a frequency spectrum, the display system including processor means for providing data for said sequentially occurring displays; and frequency synthesiser means for generating a plurality of frequencies which extend over a frequency range, said synthesiser means stepping the frequency generated thereby through said plurality of frequencies the time taken by said synthesiser means to make a frequency step varying over said range, said synthesiser means indicating when each frequency is achieved by providing a synchronisation signal to said processor means, each frequency generated by said synthesiser means being utilised to provide a further signal, said processor means receiving each said further signal in response to receipt of a said synchronisation signal from said synthesiser means indicating that the frequency utilised to provide that further signal has been achieved by said synthesiser means, said processor means processing said further signals to provide said data for said sequentially occurring displays.

A display system for displaying a series of sequentially occurring displays in accordance with the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block schematic diagram of the system; Figures 2 and 3 show first and second oscilloscope waveform displays respectively, displayed by the system; Figure 4 illustrates the drawing/deleting which occurs in the display of oscilloscope waveform displays; Figure 5 is a block schematic diagram of a part of a radio testing equipment, of which equipment the system of Figure 1 is the display system; and Figure 6 is a block schematic diagram of a further part of the radio testing equipment.

The radio testing equipment, of which the system of Figure 1 is the display system, tests the receive and transmit modes of operation of a duplex radio system. The display system of Figure 1 produces three series of sequentially occurring displays, in each of which series each display, apart from the first occurring display, is the update of the display previously occurring in the series.

In testing the receive and transmit modes of operation, the updating is in response to the audio output and the audio modulated r.f.

output respectively of the radio system. A user of the equipment interprets the displays to aid in the determination of the quality of reception/transmission.

The three series of sequentially occurring displays produced by the display system of Figure 1 are as follows. A series of oscilloscope displays, each of which displays comprises a plot of the amplitude versus time of an audio signal derived from the radio system under test, be it demodulated audio derived from the audio modulated r.f. output of the radio system or audio directly received from the audio output of the radio system. A series of fast fourier transform (FFT) analyser displays, each of which displays comprises the frequency spectrum of an audio signal derived from the radio system under test, be it either the aforementioned demodulated or directly received audio. A series of spectrum analyser displays, each of which displays comprises the frequency spectrum of the audio modulated r.f. output of the radio system under test.

Referring to Figure 1, the display system comprises a data acquisition section 21, a central processing section 23, and a video processing section 25.

The data acquisition section 21 comprises an oscilloscope sub-section 27 for acquiring the data for the oscilloscope displays, and an FFT and spectrum analyser sub-section 29 for acquiring the data for the FFT and spectrum analyser displays. The data acquisition section 21 further comprises a connection 31 with the main central processing unit (not shown in Figure 1 but shown in Figure 5, see below) of the radio testing equipment for the receipt of control instructions from the main unit, and the receipt of data from, and the sending of data to, the main unit. The connection 31 communicates with the central processing section 23 of the display system by way of a parallel interface 33.

The oscilloscope sub-section 27 comprises an analogue to digital (A/D) converter 35 and sampling logic circuitry 37. The A/D converter 35 receives an audio signal from the radio system under test and digitizes it thereby to provide a train of data values representative of the audio signal. These data values pass to the circuitry 37 which determines the maximum and minimum data values occurring during each passage of a given time interval. These maximum and minimum data values are passed to the central processing section 23 by way of a first in/first out (FIFO) buffer 39.

The FFT and spectrum analyser sub-section 29 comprises an A/D converter 41, a digital signal processor (DSP) 43, and a memory 45 for the digital signal processor 43. The A/D converter 41 digitizes log-amp signals derived from the radio system under test, and the processor 43 performs calculations on these digitized signals to produce data for the spectrum analyser displays. The A/D converter 41 also digitizes audio signals from the radio system under test, and the processor 43 performs an FFT on these digitized signals to produce data for the FFT analyser displays. A switch 40 is provided to switch either the log-amp signals for the spectrum analyser displays or the audio signals for the FFT analyser displays to A/D converter 41. The memory 45 serves as data and running program memory for processor 43.The data provided by processor 43 passes to the central processing section 23 by way of a parallel interface 47.

The central processing section 23 comprises a 68000 (68K) processor 49 and a memory 51 which serves as data and running program memory for the processor 49. The data provided by the data acquisition section 21 of the display system passes to the memory 51 by way of a 68K data bus 52 between memory 51 and processor 49.

There is also a 68K address bus 54 between the memory 51 and processor 49. The processor 49 acts on commands received, by way of connection 31, from the main central processing unit of the radio testing system, handles data transfer from the data acquisition section 21, and performs calculations and tests on the data from the acquisition section 21 to provide the required drawing information for the video processing section 25. The processor 49 also downloads to the memory 45 running programs for the digital signal processor 43. The drawing information provided by the central processing section 23 for the video processing section 25 passes to the section 25 by way of a buffer 56.

The video processing section 25 comprises a processor 53, a dynamic random access memory (DRAM) 55 for the processor 53, and a palette 57. The processor 53 both executes drawing sequences stored in the DRAM 55, which sequences are determined by the drawing information received by the DRAM 55 from the central processing section 23, and handles the display of the bit maps created in the DRAM 55 by the execution of the drawing sequences. The processor 53 thus performs two distinct operations, the execution of drawing sequences and the display of the bit maps created thereby. Both of these operations require access to a data bus 59 of the video processing section 25 between processor 53 and memory 55. Use of large internal FIFO pre-fetch buffer memories (not shown) in the processor 53 for drawing commands and display data permits the use of fast efficient page mode access to the DRAM 55.Further, the processor 53 is programmed to give the 68K data bus 52 of the central processing section 23 priority access to the data bus 59 of the video processing section 25. The 68K databus 52 does not therefore have to wait very long, when it has drawing information for the DRAM 55, while the drawing and display operations of the section 25 occupy the bus 59. The buffer 56 by way of which drawing information is received by the video processing section 25 from the central processing section 23 is enabled by processor 53 by way of connection 60.

The operation of the display system of Figure 1 will now be described in detail. The operation to provide the series of sequentially occurring oscilloscope displays will first be described.

Referring also to Figures 2 and 3, the display screen 61 of the display system is divided up into a series of vertical ordinates 63, each of which comprises a column of pixels 65. For the oscilloscope displays each ordinate 63 corresponds to the time interval mentioned above in connection with the acquisition of data for the oscilloscope displays. In each oscilloscope display, the pixels 65 of each ordinate 63 characterised by the processor 53 of the video processing section 25 extend from and including a pixel, e.g. pixel 64 in Figure 2, corresponding to the minimum data value occurring during the time interval corresponding to that ordinate 63 to and including a pixel, e.g. pixel 66 in Figure 2, corresponding to the maximum data value occcurring during that time interval (note in Figures 2 and 3 the pixels characterised are those crossed).

The display system thereby displays the signal received by the A/D converter 35 of the oscilloscope sub-section 27. The waveform comprising the oscilloscope display of Figure 2 describes a signal the frequency of which is low compared with the number of ordinates or time intervals per second. The waveform comprising the oscilloscope display of Figure 3 describes a signal the frequency of which is high compared with the number of ordinates per second.

The signal displayed in Figure 3 in fact comprises envelopes of high frequency signal. The frequency of the signal to be displayed is thus too high for resolving on the display and a so called 'solid' trace results.

Consider that the oscilloscope sub-section 27 is acquiring the data for oscilloscope display n of a series of sequentially occurring oscilloscope displays ...., n-3, n-2, n-l, n, n+1, n+2, n+3,...., display n-3 being updated to display n-2, display n-2 being updated to display n-l, etc.

The maximum and minimum data values for display n are read out of FIFO buffer 39 by processor 49. The processor 49 determines for each ordinate 63 of the display screen 61 the difference (if any) between the maximum data value for that ordinate for display n and the maximum data value for that same ordinate for display n-2, the memory 51 having stored therein, from previous operation of the display system for the display of display n-2, the maximum and minimum data values for display n-2. The processor 49 also datermines for each ordinate 63 the difference (if any) between the minimum data value for that ordinate for display n and the minimum data value for that same ordinate for display n-2.

In dependence on the aforesaid differences determined for display n, the processor 49 modifies, by means of address connections 67 and 69, connection 71 to data bus 59, and data bus 59, a first sequence of drawing instructions of first and second sequences of drawing instructions stored in DRAM 55 of the video processing section 25. In this connection, the DRAM 55 as well as storing the first and second sequences of drawing instructions, stores first and second display bit maps created by the execution of the first and second sequences respectively.As will become clear below, the reason why the first drawing sequence is modified in dependence on the aforesaid differences is because the drawing algorithm used by the first (and also the second) drawing sequence only draws to/deletes from those first (second) display bit map memory locations the contents of which are required to be different from a given display (resulting from execution of the first (second) sequence) to the next display (resulting from execution of the first (second) sequence).

Further, as will also become clear below, the reason why the differences for display n are with respect to display n-2 and not display n-l is because of the toggling action of the video processing section 25 between the first and second drawing sequences stored in memory 55, at the time of the modification of the first sequence for the drawing of display n the first sequence having been previously modified for the drawing of display n-2.

At the time of the modification by the processor 49 of the first drawing sequence for the drawing of display n, the processor 53 is executing, by means of address connection 69 and data bus 59, the second drawing sequence to create in the DRAM 55 a second display bit map for display n-l. At the same time processor 53 is displaying, by means of data bus 59 and video connection 73 to palette 57, a previously created first display bit map in DRAM 55 for display n-2.After modification of the first sequence for display n and creation of the second display bit map for display n-l, the display system toggles so as to display the second display bit map for display n-l, to execute the first sequence to create a first display bit map in DRAM 55 for display n, and to modify the second sequence, modified as it is for display n-l, for display n+1.

After modification of the second sequence for display n+1 and creation of the first display bit map for display n, the display system toggles again to display the first display bit map for display n, to execute the second sequence to create a second display bit map for display n+1, and to modify the first drawing sequence, modified as it is for display n, for display n+2. Thus, the drawing/deleting by execution of the drawing sequences is not seen, and the user is presented with a series of stable displays.

The drawing algorithm used by each of the first and second drawing sequences only draws to/deletes from those memory locations of the DRAM 55 the contents of which are required to be different from a given display (resulting from execution of that sequence), display n-2, to the next display (resulting from execution of that sequence), display n. The drawing/deleting which occurs depends on the relationship for each ordinate 63 of the display screen 61, firstly between the maximum data values for that ordinate 63 for the given and next displays, and secondly between the minimum data values for that ordinate 63 for the given and next displays. As mentioned above, these relationships are determined by the processor 49 of the central processing section 23.

Referring to Figure 4, (a) to (f) are the six general cases for the relationships between the maximum and minimum data values for the ordinates 63 of the given and next displays. In each of the six cases (a) to (f) the area labelled G represents those pixels 65 of a given ordinate 63 characterised in the given display, and the area labelled N represents those pixels 65 of the same given ordinate 63 required to be characterised in the next display. In case (a), deletion from those memory locations corresponding to pixels 65 from 107 to 105 and drawing to those memory locations corresponding to pixels 65 from 100 to 101 occurs, the memory locations corresponding to the pixels 65 from 102 to 104 being left as they are (pixel numbers inclusive). In case (b), drawing to 117 to 115 and deletion from 110 to 111 occurs, 112 to 114 being left as it is. In case (c), deletion from 127 to 126 and from 120 to 122 occurs, 123 to 125 being left as it is. In case (d), drawing to 137 to 136 and to 130 to 132 occurs, 133 to 135 being left as it is.

In case (e), deletion from 147 to 144 and drawing to 140 to 142 occurs. In case (f), drawing to 157 to 154 and deletion from 150 to 152 occurs.

The algorithm covering the six general cases (a) to (f) is as follows:if given max pixel > next max pixel (cases (a), (c) and (e)) then:

if next max pixel given min pixel (cases (a) and (c)) then: delete from and including given max pixel to but not including next max pixel else (case (e)): delete from and including given max pixel to and including given min pixel else (cases (b), (d) and (f)):: if given max pixel # next min pixel (cases (b) and (d)) then: draw from and including next max pixel to but not including given max pixel else (case (f)): from draw from and including next max pixel to and including next Ll!.n pixel if given min pixelv next min pixel (cases (b), (c) and (f)) then:: if next min pixelArgiven max pixel (cases (b) and (c)) then: delete from and including given min pixel to but not including next min pixel else (case (f)): delete from and including given min pixel to and including given max pixel else (cases (a), (d) and (e)): if given min pixel # next max pixel (cases (a) and (d)) then:: draw from and including next min pixel to but not including given min pixel else (case (e)): F aw from and including next min pixel to and including next

LLImax pixel.

Thus, each ordinate 63 is updated by two drawing/deleting operations, the first drawing/deleting from the top downwards, the second drawing/deleting from the bottom upwards.

In drawing/deleting only those memory locations of the DRAM 55 the contents of which are required to be different from a display (resulting from execution of a drawing sequence) to the next display (resulting from execution of the same drawing sequence), the algorithm confers advantage in the speed of updating displays, in particular in the speed of updating between solid trace displays (see above). That is, where the difference between the old and new solid trace displays is minor, prior art display systems have completely deleted the old solid trace display and then drawn the new one, a lengthy operation compared with that to achieve the same of the display system of the present invention.

The drawing/deleting algorithm described above is realised by the first and second drawing sequences each comprising a draw sequence and a delete sequence. The draw sequence is as follows: move x, y draw dx, dy move x, y draw dx, dy move x, y draw dx, dy etc where, see Figures 2 and 3, x is the number of the pixel column in the x direction, y is the number of the pixel row in the y direction, and dx and dy are the number of pixels drawn to in the x and y directions respectively starting from the x/y position. The delete sequence is the same as the draw sequence except the draws are replaced by deletes. The draw and delete sequences will each be of variable length depending on the amount of drawing/deleting required.In modifying the first and second drawing sequences from display to display, processor 49 changes the x, y and dy data in the draw and delete sequences, the dx values always being zero.

The operation of the display system to provide the series of sequentially occurring FFT and spectrum analyser displays will now be described.

Similarly to the production of the oscilloscope displays, in producing the FFT and spectrum analyser displays, the processor 49 of the central processing section 23 modifies a drawing sequence stored in the memory 55 of the processor 53 of the video processing section 25. Such modification takes place in dependence on the data received by the section 23 from the FFT and spectrum analyser sub-section 29.

In the case of the FFT analyser displays, as for the oscilloscope displays, there are two drawing sequences stored in memory 55, the processor 49 modifying one whilst the processor 53 executes the other, toggling occurring thereafter. However, in the case of the spectrum analyser displays, only one drawing sequence is stored in memory 55. In this case processor 49 receives data from sub-section 29 in real time during frequency sweeping, and the processor 53 is arranged using conventional drawing methods to update each display one ordinate at a time whilst the display is displayed on the display screen 61, so that such updating one ordinate at a time is seen by the user of the display system to be occurring.

The FFT and spectrum analyser displays are not max/min displays as the oscilloscope displays. In the case of the FFT and spectrum analyser displays, a single data value/pixel is identified for each ordinate 63 of the display screen 61, and by the known technique of point-to-point or polyline drawing a line is drawn between these identified values to produce a point-to-point trace.

The polyline drawing operates from an array of so called 'dx' and 'dy' values stored in memory 55, and in the drawing sequence modification by the processor 49, it is this array which is modified. For the FFT and spectrum analyser displays the memory locations of the DRAM 55 containing the old trace are deleted and the memory locations to contain the new trace drawn to (in the case of the spectrum analyser displays this deletion and drawing takes place one ordinate at a time), since, in the case of point-to-point drawing, this can be done quickly. Each of the two drawing sequences stored in memory 55 for the FFT analyser displays therefore consists of a first part which deletes the previous trace and a second part which draws the new one.The same is true of the single drawing sequence stored in memory 55 for the spectrum analyser displays, except that in this case the sequence deletes and draws in respect of one ordinate at a time, such updating one ordinate at a time being seen by the user on the display screen 61.

Returning to the provision of the oscilloscope displays, a further comment to be made in connection therewith, is that on slower oscilloscope timebases, the time taken to acquire the data for a display is longer than the display update time, and therefore for these timebases a different drawing method is used by processor 53 which updates one ordinate at a time the ordinates of a currently displayed display, cf. the provision of the spectrum analyser displays.

It will be appreciated that the processor 53 of the video processing section 25 is a fully fledged co-processor, and not just a peripheral device, to the processor 49 of the central processing section 23. In this connection it is not necessary for the processor 49 to continually send one drawing instruction at a time to the processor 53 for execution, the processor 53 executes complete drawing instruction sequences from its own memory 55. It is to be noted here that if the processor 53 were reading complete drawing sequences for execution from the memory 51 of the central processing section 23 by employing direct memory accessing (DMA), the processor 53 would still be acting as a fully fledged co-processor to the processor 49.

It will also be appreciated that the display system of Figure 1 derives advantage from the repetitive nature of the display drawing. That is the processor 49 does not repeatedly download a complete drawing sequence to the DRAM 55 for each of the sequentially occurring displays, but downloads a complete drawing sequence only once for the first display. Thereafter for subsequent displays the processor 49 merely modifies the initially downloaded drawing sequence. This has the dual benefit of reducing the work done by the processor 49, and minimising interruption to the work of processor 53, thus reducing the time it takes the processor 53 to draw and display displays.

An oscilloscope/FFT analyser/spectrum analyser trace is not wanted in isolation; usually there must also be a graticule displayed, and sometimes also a second trace and markers. The display system of Figure 1 achieves such displays by making use of what can be considered to be a combination of the principles of two known display techniques.

The first known technique is commonly termed the bit plane display technique. In this technique the red, green and blue video display information is stored separately, i.e. in bit planes; the separate areas are visualised as planes of display data which are displayed simultaneously by the display hardware. The second known technique uses a so called colour palette chip. A certain number of bits per pixel (bpp), e.g. 4 or 8, is assigned by the display system, with each pixel being set to a number, the logical colour; these logical colours are output to the palette chip (a fast RAM coupled to three DACs), sometimes known as a Colour Look-Up Table (CLUT), which looks up the required DAC values for the red, green and blue analogue video outputs, the physical colour for each logical colour.

The display provided by the display system of Figure 1 consists of a 'base screen' for the main display area, which is overlaid with a hardware window for the oscilloscope/FFT analyser/spectrum analyser display. As mentioned above the oscilloscope/FFT analyser/spectrum analyser display includes, in addition to the main trace and, as required, a graticule, second trace and markers. The palette 57 of Figure 1 includes two look-up tables, one which is selected when the base screen is displayed, the other which is selected during the window overlay periods of the video scan. A hardware window status output signal provided by procesor 53 is used for this selection. Display data on the base screen operates according to the second known technique mentioned above, using four bits per pixel to provide 16 logical colours, whose analogue values are programmed into the base screen look-up table.The video output of the base screen look-up table results in 16 shades of green displayed. Display data on the hardware window overlay operates according to a combination of the first and second known techniques as will now be described.

According to the palette technique, four bits are assigned in respect of each pixel of the window, each pixel therefore being set to a four bit number. However, with similarities to the bit plane technique, each bit of each four bit number corresponds to one of the four distinct features of the window display, i.e. the main trace, graticule, second trace and markers. Modification by the processor 53 of each bit of each four bit number therefore results in modification in the display of the corresponding distinct feature. The processor 53 provides bit-masking, allowing it to be programmed to only modify a certain bit or bits in the pixel data being manipulated. Thus the trace drawing software can draw and delete the main trace image using a certain bit mask totally independently of and oblivious to the graticule, marker, and second trace image data.The first, second, third and fourth bits of the four bit numbers can be regarded respectively as main trace, graticule, second trace and marker bit planes.

The combination of the four bits for each pixel is regarded as a logical colour to be translated to the appropriate physical colour by the window look-up table. The look-up table is used to deal with the combinations of the different bit planes in a useful manner as follows: The main trace on its own produces a high intensity green.

The second trace on its own produces a medium intensity green.

The graticule on its own produces a low intensity green.

When the main trace and graticule cross, the colour for the main trace is output, so that the main trace appears to be in front of the graticule.

When the second trace and graticule cross, the colour of the graticule is output, so that the second trace appears to be behind the graticule.

Similar decisions are made for other combinations of main and second traces, graticule, and markers.

The base screen and window look-up tables of palette 57 mentioned above produce a green monochrome output at 91 in Figure 1.

Palette 57 includes an alternative base screen look-up table and an alternative window look-up table, the use of which is precisely the same as the first mentioned base screen and window look-up tables, except that red 93, green 95 and blue 97 outputs are produced by the alternative look-up tables for the purposes of colour display on a colour monitor external to the display system described by way of example. The digital values for the four look-up tables of palette 57 are initially down-loaded by processor 49 to palette 57 via 68K databus 99.

The above described hybrid bit plane/colour palette display method has distinct advantages over other ways of displaying and updating combinations of main trace plus graticule/second trace/markers. For example, the images for these display features could be drawn in separate memory areas and combined using multiple windows, but this is very expensive in terms of hardware processing power required. Alternatively, software could be used to do the combining, reading what else is to be displayed and adding the main trace to it. This is easy for drawing a new trace, but very slow when the trace has to be deleted without disturbing the other information. A software method might have to instead clear the trace display area and redraw the graticule and other trace information each time, which is slow.The bit plane/colour palette display method of the present invention overcomes these problems. High speed drawing is achieved by using a specialised drawing method (bit plane), and expense is saved in terms of hardware processing power required by the bit planes in fact comprising the respective bits of the numbers used to instruct a palette chip. The palette produces a sensible colour output by mapping the combinations of information from the different bit planes to the required physical colours.

Referring to Figure 5, the radio testing equipment, of which the system of Figure 1 is the display system, includes a main central processing unit 201 (referred to above), a microprocessor 203, a fractional-N frequency synthesiser 205, a mixer 207, an input switch and attenuators 204, a bank of switched filters 206, and a logarithmic amplifier 209. Microprocessor 203, synthesiser 205, mixer 207, filters 206, and amplifier 209 are located in a part 208 of the r.f. tray of the test equipment. Connection 31, see the display system of Figure 1, connects main unit 201 to the display system of Figure 1. Microprocessor 203 is connected to digital signal processor 43 of data acquisition section 21 of Figure 1 by connection 211. Amplifier 209 is connected to A/D converter 41 of data acquisition section 21 of Figure 1 by connection 213.

That part of the radio testing equipment shown in Figure 5 operates to provide data for the spectrum analyser displays as follows.

As mentioned above each spectrum analyser display comprises the frequency spectrum of the audio modulated r.f. output of the radio system under test. The frequencies of this spectrum are plotted along the X axis of the display screen 61 of the display system, see Figure 2. Thus, data is required in respect of the band of frequencies covered by each vertical ordinate 63 of display screen 61. To this end fractional-N synthesiser 205 generates in respect of each ordinate 63 one or more frequencies.

Microprocessor 203 steps frequency synthesiser 205 through the frequencies for the ordinates 63, and each frequency is mixed with the above mentioned audio modulated r.f. output to provide data for the spectrum analyser displays. This will now be explained in more detail.

In dependence on the frequency span requested by the user for the spectrum of the display, main unit 201 sets, by way of serial bus 217, parameters for a stepped frequency sweep by microprocessor 203/synthesiser 205. These parameters comprise the start frequency, the frequency step size, the 'time per step' time, and the selection of the filter of the switched band of filters 206.

Microprocessor 203 effects selection of the filter of filters 206 in accordance with the 'selection of the filter' parameter. Main unit 201 also sets, by way of connection 31, the display system of Figure 1 to display spectrum analyser displays. Such setting includes telling digital signal processor 43 how many frequency settings of synthesiser 205 there are per ordinate 63 so that processor 43 can appropriately process the data values from A/D converter 41 to provide display data for ordinates 63. For example, if there are two frequency settings of synthesiser 205 per ordinate 63, processor 43 may select the greater of the two values provided in respect of each ordinate 63 by A/D converter 41, see below.

Mixer 207 mixes each frequency generated by synthesiser 205 with the audio modulated r.f. output of the radio system under test, this output being received by mixer 207 from an r.f. input 219 to the test equipment via input switch and attenuators 204. Each intermediate frequency (IF) output of mixer 207 is filtered by the selected filter of filters 206 and passed to logarithmic amplifier 209. Amplifier 209 provides in response to receipt of each output of filter 206 a DC signal the strength of which is representative of the strength of a frequency component of the audio modulated r.f.

output within the band of frequencies covered by the ordinate 63 in respect of which that output of filter 206 was produced. The signal provided by amplifier 209 is digitised by A/D converter 41, which converter 41 is read by processor 43.

Digital signal processor 43 initiates and ends each stepped sweep of synthesiser 205 by means of connection 211. Considering a frequency step, microprocessor 203 begins the frequency step by instructing synthesiser 205 to step to the next frequency. After such instruction microprocessor 203 allows sufficient time for synthesiser 205 to achieve, i.e. settle to, the next frequency. In order to enable microprocessor 203 to allow sufficient time it has knowledge of those frequency steps which require change to hardware configurations of the test equipment, such steps taking longer to make. When synthesiser 205 makes a frequency step which does not require the aforementioned change to hardware configurations, microprocessor 203 allows only the 'time per step' time (minus the duration of a synchronisation pulse sent at the end of each step, see below) for this frequency step to be achieved.However, when synthesiser 205 makes a frequency step which does require change to hardware configurations, microprocessor 203 allows a longer time for this frequency step to be achieved. After the time allowed has passed microprocessor 203 outputs to processor 43, by means of connection 211, a synchronisation pulse (mentioned above) indicating that the next frequency has been achieved. In response to receipt of the synchronisation pulse processor 43 takes a single reading of A/D converter 41, which single reading is that of the DC level provided by amplifier 209 for the above mentioned next frequency.

After the sending of the synchronisation pulse microprocessor 203 begins the next frequency step by instructing synthesiser 205 to step to the frequency after the above mentioned next frequency.

It is to be appreciated that catering for the frequency steps that take longer by allowing a longer step time for these steps only makes for a faster sweep (and hence display update rate) than, for example, catering for the longer steps by allowing the longest step time for all steps. Consider an equipment wherein the display system ordinate update rate controls the frequency stepping by synthesiser 205 and is chosen to be sufficiently low to cater for the longest frequency step. Such an equipment would have a significantly slower sweep (and hence display update rate) than the equipment described above.

Referring to Figure 6, the equipment described above may be used in the following way to display a further series of sequentially occurring displays, each of which comprises the audio frequency response of the radio system under test. There are similarities between such use and the provision of the spectrum analyser displays.

The equipment further comprises a microprocessor 301 and an audio frequency generator 303. Generator 303 comprises a DSP 305 and a digital to analogue (D/A) converter 307. Microprocessor 301 is connected to main unit 201 (see Figure 5) by serial bus 309 and to DSP 43 (see Figure 1) by connection 311. Each audio frequency generated by generator 303 at output 302 is either supplied directly to the radio system 313 under test or else is used to modulate an r.f. carrier which is supplied to radio system 313. In the case where each audio frequency is supplied directly, the audio modulated r.f. output of radio system 313 is demodulated and supplied to audio frequency input 315 of the test equipment. Input 315 is connected to A/D converter 41 (see Figure 1).In the case where each audio frequency is used to modulate an r.f. carrier, the audio output of radio system 313 is supplied directly to input 315.

The operation of the test equipment to provide the audio frequency response of radio system 313 is similar to the operation to provide the spectrum analyser displays. Main unit 201 sets, by way of serial bus 309, parameters for a stepped frequency sweep by microprocessor 301/generator 303. Main unit 201 also sets, by way of connection 31 (see Figure 5), the display system of Figure 1 to display the frequency response of radio system 313. The time taken for microprocessor 301/generator 303 to make a frequency step (i.e. the time between microprocessor 301 instructing generator 303 to generate a frequency and to generate the next frequency) varies across the range of frequencies generated by generator 303. This variation is in accordance with the frequency step being made. To indicate when each frequency is achieved microprocessor 301 provides via connection 311 a synchronisation pulse to DSP 43. In response to receipt of each synchronisation pulse DSP 43 takes several readings of A/D converter 41 to enable it to calculate the root mean square (rms) level of the audio frequency signal produced by radio system 313 in response to the frequency generated by generator 303 in respect of which that synchronisation pulse was produced.

Claims (29)

1. A display system for displaying a series of sequentially occurring displays comprising: means for acquiring data values for each said display; first processor means for modifying for each said display a sequence of drawing instructions for said displays in dependence on the data values acquired for that said display; and second processor means for executing for each said display the sequence of drawing instructions modified for that said display.

2. A system according to Claim 1 wherein said first and second processor means each has its own dedicated memory and said drawing sequence is stored in the memory of said second processor means.

3. A system according to Claim 2 which is the display system of a radio testing equipment.

4. A system according to Claim 3 wherein: said series of displays comprises a series of oscilloscope displays, each of which represents an audio signal derived from a radio system being tested by said equipment; each oscilloscope display is displayed on a display screen of the system comprising an array of rows and columns of pixels; said data values acquired for each said oscilloscope display comprise a plurality of pairs of data values of the data values provided by an analogue to digital converter of said means for acquiring which receives said audio signal, each pair comprising the maximum and minimum data values occurring during a predetermined time interval, each said time interval corresponding to the width of a respective one of said columns of pixels; and said first processor means determines for each said oscilloscope display firstly the difference between the maximum data value of each pair of the plurality of pairs of data values for that said display and the maximum data value of the corresponding pair of the plurality of pairs of data values for a previous oscilloscope display, and secondly, the difference between the minimum data value of each pair of the plurality of pairs of data values for that said display and the minimum data value of the corresponding pair of the plurality of pairs of data values for said previous display, said first processor means modifying for each said display said drawing sequence in dependence on said differences determined for that said display.

5. A system according to Claim 4 wherein: for each said oscilloscope display said previous display is the next but one preceding display; and the memory of said second processor means simultaneously stores two said sequences of drawing instructions for the oscilloscope displays, one of which is being modified by said first processor means for a said oscilloscope display, whilst the other, which has been previously modified by said first processor means for the preceding oscilloscope display, is being executed by said second processor means, at the time of modification of said one sequence and execution of said other sequence said second processor means displaying the next but one preceding display, after the modification of said one sequence and the execution of said other sequence said second processor means displaying the preceding display and executing said modified one sequence and said first processor means modifying said executed other sequence for the next oscilloscope display.

6. A system according to Claim 3 which displays three said series of sequentially occurring displays, the first of which comprises a series of oscilloscope displays each of which represents an audio signal derived from a radio system being tested by said equipment, the second of which comprises a series of fast fourier transform displays each of which comprises the frequency spectrum of an audio signal derived from said radio system, the third of which comprises a series of spectrum analyser displays each of which comprises the frequency spectrum of an audio modulated radio frequency signal derived from said radio system.

7. A display system of a radio testing equipment, for displaying three series of sequentially occurring displays, the first of which comprises a series of oscilloscope displays each of which represents an audio signal derived from a radio system being tested by said equipment, the second of which comprises a series of fast fourier transform displays each of which comprises the frequency spectrum of an audio signal derived from said radio system, the third of which comprises a series of spectrum analyser displays each of which comprises the frequency spectrum of an audio modulated radio frequency signal derived from said radio system, substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

8. A display system for displaying a series of sequentially occurring displays, each of which comprises a waveform and is displayed on a display screen of the system comprising an array of rows and columns of pixels, whether or not each of which pixels is characterised by the system being determined by the contents of a corresponding memory location of a memory of the system for storing said displays, said system displaying each waveform by characterising all the pixels of each column from and including a first pixel of the column to and including a second pixel of the column, said display system displaying each next display of the series by modifying the contents of the memory locations for a previous display by addressing and changing the contents of substantially only those memory locations the contents of which are required to be different for the next display to said previous display.

9. A system according to Claim 8 which is the display system of a radio testing equipment, said series of displays comprising a series of oscilloscope displays, each of which represents an audio signal derived from a radio system being tested by said equipment.

10. A system according to Claim 9 comprising: means for acquiring for each said display a plurality of pairs of data values, said means for acquiring including an analogue to digital converter which receives said audio signal and provides data values, each pair comprising the maximum and minimum data values occurring during a predetermined time interval, each said time interval corresponding to the width of a respective one of said columns of pixels; first processor means for determining for each said next display firstly, the difference between the maximum data value of each pair of the plurality of pairs of data values for that said display and the maximum data value of the corresponding pair of the plurality of pairs of data values for said previous display, and secondly, the difference between the minimum data value of each pair of the plurality of pairs of data values for that said display and the minimum data value of the corresponding pair of the plurality of pairs of data values for said previous display, said first processor means modifying for each said next display a sequence of drawing instructions for said displays in dependence on said differences determined for that said display; and second processor means for executing for each said next display said sequence of drawing instructions modified for that said display thereby effecting for that said display said modification of the contents of the memory locations for said previous display.

11. A system according to Claim 10 wherein said first and second processor means each has its own dedicated memory and said sequence of drawing instructions is stored in the memory of said second processor means.

12. A system according to Claim 11 wherein: for each said next display said previous display is the next but one preceding display to said next display; and the memory of said second processor means simultaneously stores two said sequences of drawing instructions, one of which is being modified by said first processor means for a said next display, whilst the other, which has been previously modified by said first processor means for the preceding display to said next display, is being executed by said second processor means, at the time of modification of said one sequence and execution of said other sequence said second processor means displaying the next but one preceding display to said next display, after the modification of said one sequence and the execution of said other sequence said second processor means displaying the preceding display and executing said modified one sequence and said first processor means modifying said executed other sequence for the display after said next display.

13. A display system of a radio testing equipment, for displaying a series of sequentially occurring oscilloscope displays, each of which represents an audio signal derived from a radio system being tested by said equipment, substantially as hereinbefore described with reference to Figures 1 to 4 of the accompanying drawings.

14. A display system for displaying a series of sequentially occurring displays each of which comprises a plurality of distinct features, said display system comprising: a display screen comprising an array of rows and columns of pixels on which display screen said sequentially occurring displays are displayed; a memory for storing said displays, the characterisation of each pixel of said display screen being determined by a number stored in a corresponding memory location of said memory, which number is one of a series of numbers each of which comprises a number of parts equal to the number of said distinct features each part corresponding to one distinct feature; look-up table means for storing in respect of each number of the series a digital value for a video output of the look-up table means; and processor means for modifying for a subsequent display of said series one or more of said number of parts of the number stored in each memory location of said memory, said processor means thereby modifying for the subsequent display the distinct feature(s) corresponding to the part(s) of each number modified, said modification of the part(s) of each number being made independently of the remaining part(s) of the number.

15. A system according to Claim 14 wherein said processor employs bit-masking to modify said one or more parts of the number stored in each memory location independently of the remaining part(s) of the number.

16. A system according to Claim 14 or Claim 15 wherein each display comprises four district features, a main trace, a graticule, a further trace and markers, and the number stored in each memory location is a four bit number each bit of which corresponds to a respective one of said four features.

17. A system according to Claim 14 or Claim 15 or Claim 16 wherein said digital values stored in the look-up table means provide for video outputs for pixels whereat there is one or more or none of said distinct features.

18. A system according to any one of Claims 14 to 17 wherein said display screen is a window display area of a larger display screen, said system including in respect of the remaining display area of the larger display screen further look-up table means, said processor means providing an output signal indicative of the window and remaining display area periods of the video scan, which signal is used to select from the first mentioned and further look-up tables.

19. A system according to Claim 14 substantially as hereinbefore described by way of example.

20. A test equipment comprising: a display system for displaying a series of sequentially occurring displays each of which comprises a frequency spectrum, the display system including processor means for providing data for said sequentially occurring displays; and frequency synthesiser means for generating a plurality of frequencies which extend over a frequency range, said synthesiser means stepping the frequency generated thereby through said plurality of frequencies, the time taken by said synthesiser means to make a frequency step varying over said range, said synthesiser means indicating when each frequency is achieved by providing a synchronisation signal to said processor means, each frequency generated by said synthesiser means being utilised to provide a further signal, said processor means receiving each said further signal in response to receipt of a said synchronisation signal from said synthesiser means indicating that the frequency utilised to provide that further signal has been achieved by said synthesiser means, said processor means processing said further signals to provide said data for said sequentially occurring displays.

21. An equipment according to Claim 20 wherein: each said display comprises the frequency spectrum of a signal received by said equipment, which signal has components at different frequencies; and said utilisation of each frequency of said plurality to provide a said further signal is by a means for utilising of said equipment, which means for utilising comprises a mixer which mixes each frequency of said plurality with said signal received by said equipment to provide a said further signal.

22. An equipment according to Claim 21 wherein: said signal received by said equipment comprises an audio modulated r.f. output of a radio system being tested by said equipment; and said means for utilising further comprises filter means connected to the output of said mixer and a logarithmic amplifier connected to the output of said filter means, said amplifier providing said further signals, the strength of each said further signal being representative of the strength of a frequency component of said audio modulated r.f.

output.

23. An equipment according to Claim 22 wherein said synthesiser means comprises a microprocessor and a fractional-N frequency synthesiser, the microprocessor stepping the fractional-N synthesiser through said plurality of frequencies and providing in respect of each frequency a said synchronisation signal to said processor means indicating when that frequency is achieved.

24. An equipment according to any one of Claims 20 to 23 wherein said processor means is a digital signal processor.

25. An equipment according to Claim 20 wherein said utilisation of each frequency of said plurality to provide a said further signal is by a device being tested by said equipment, said frequency spectrum comprising each display being the frequency response of said device to said plurality of frequencies.

26. An equipment according to Claim 25 wherein: said device is a radio system; and each frequency of said plurality is an audio frequency.

27. An equipment according to Claim 26 wherein said synthesiser means comprises a microprocessor and an audio frequency generator, the microprocessor stepping the generator through said plurality of frequencies and providing in respect of each frequency a said synchronisation signal to said processor means indicating when that frequency is achieved.

28. An equipment according to any one of Claims 25 to 27 wherein said processor means is a digital signal processor.

29. A test equipment substantially as hereinbefore described with reference to Figure 5 or Figure 6 of the accompanying drawings.