GB2266607A - Preventing operations which cause overflow in an arithmetic and logic unit - Google Patents

Abstract

An arrangement 10 for detecting an incorrect result produced by division in a computer ALU 12 including apparatus 17 for storing the sign of a dividend, apparatus 18 for storing the sign of a divisor, apparatus for utilizing the sign of the dividend a and the sign of the divisor to indicate an expected sign for a quotient, apparatus 20 for detecting the sign of a quotient produced by the division of the dividend by the divisor, apparatus 27 for comparing the expected sign of the quotient with the actual sign of the quotient, and apparatus for aborting the division operation if the compared signs differ. <IMAGE>

Description

APPARATUS FOR PREVENTING DIVIDE-BY-ZERO AND OTHER OPERATIONS WHICH CAUSE OVERFLOW IN AN ARITHMETIC AND LOGIC UNIT BACKGROUND OF THE INVENTION Field Of The Invention This invention relates to computer systems and, more particularly, to apparatus for preventing register overflow in division operations by an arithmetic and logic unit of a computer processor.

History Of The Prior Art Division conducted by a computer is a relatively slow process compared to other mathematical processes. The basic division process typically requires that the divisor be progressively subtracted, first from the high order bits of the dividend and thereafter from sequential interim dividends until a result is reached. These interim dividends are formed from the partial remainder which results from the last subtraction and the unused lower order bits from the original dividend. At each subtraction, the result of the subtraction is evaluated.If the result is positive, the upper order bits of the interim dividend from which the divisor was subtracted were larger than the divisor, a one is recorded for that place of the quotient in the lowest order position of the interim dividend, a shift of all bits of the interim dividend to the next highest order takes place, and a subtraction occurs. However, if the result is negative, the divisor was larger than the upper order bits of the interim dividend, a zero is recorded for the quotient, and the dividend must be restored to its previous condition by adding back the divisor before the next subtraction takes place. The process of division is typically accomplished utilizing the arithmetic and logic unit of a processor to perform the shifts, additions, and subtractions necessitated by the process.

This entire process is quite time consuming so various methods of acceleration have been devised. One of these methods is called a non-restore process. In this process, a negative partial remainder is allowed during the subtraction process. The non-restore process begins with a shift of the bits of the dividend by one bit to the next highest order to shift out the highest order bit followed by a subtraction of the divisor from the remaining high order bits of the dividend. If the partial remainder is positive, a one is recorded for the quotient bit in the lowest order bit position, the interim dividend is again shifted by one bit, and another subtraction occurs. If the result is negative, a zero is recorded for the quotient bit, a low order bit is appended, a left shift occurs, and the divisor is added back.Thus, the partial remainder varies positively and negatively but the interim dividend is not restored when the intermediate result for a subtraction step is negative.

However, since the shift occurs before the divisor is added back, only half the divisor value previously subtracted is added back so the extra step needed to accomplish a restore does not take place. It will be noted that the shift and add by adding only half the value previously subtracted is equivalent to adding the full divisor, shifting, and the subtracting the divisor since the shift causes the subtracted value to be one-half the added value. The remainder is only explicitly restored when the last step in the division has occurred and the remainder is negative.

Eliminating the restore steps makes this a much more rapid process than that required to implement the restore process to accomplish division.

The conventional process for implementing non-restore division using unsigned integers is described in Cavanaugh, Digital Computer Arithmetic, pp. 236-258. The process described in the Cavanaugh text requires that a non-standard arithmetic and logic unit be used to accomplish the division so that the sign bits and any carryout can be considered in determining whether the next step should be addition or subtraction.

In division by a computer, at least three operations can provide incorrect results. The first of these is division by zero which produces an indeterminate infinite number; this problem is, of course, common to all forms of division.

However, in computer operations such an infinite number is not only indefinite but causes register overflow because the quotient is too large for any register to hold. The second problem is similar but is peculiar to computers or other digital devices which reserve only a finite amount of space for storing the quotient. If the quotient overflows this space, the number produced as a quotient will be incorrect; and some other means must be found for reaching a solution.

Register overflow is caused by a divisor which is too small relative to the dividend and thus produces too large a quotient for the register. The third problem is also peculiar to computers and similar devices and occurs in signed division where the quotient lies outside its signed number range. For example, the highest positive number which can be held by an eight bit register is 0111 1111 while the largest negative number is 1000 0000. If the result is outside this range, an overflow occurs in a circuit using an eight bit register to hold the quotient.

The first two of these problems can be eliminated in unsigned division by subtracting the divisor from the high order bits of the dividend. If a positive or zero result occurs, this indicates that the quotient will require at least one more bit position than the number of positions available for the quotient. Basically, the divisor is too small relative to the dividend so that the quotient takes up more register space than is available. This would be the result for either a normal overflow condition or for division by zero. Even though the prior art has resolved these problems with respect to unsigned values, in signed division, the values dealt with are not necessarily of the correct sign to allow the prior art process to take place correctly.

Moreover, only very complicated arrangements requiring substantial increases in circuitry and slowing the division process to a great degree have been devised to resolve the third problem. No simple arrangement for determining whether the sign bits have caused an overflow in signed division has yet been proposed.

Summary Of The Invention It is, therefore, an object of the present invention to provide circuitry for resolving problems such as division by zero and other problems which cause overflow in arithmetic and logic units of computers.

It is another more specific object of the present invention to provide circuitry for resolving problems causing overflow in arithmetic and logic units of computers during division of signed numbers using a non-restore division process.

These and other objects of the present invention are realized in an arrangement for detecting an incorrect result produced by division in a computer ALU comprising means for storing the sign of a dividend, means for storing the sign of a divisor, means for utilizing the sign of the dividend a and the sign of the divisor to indicate an expected sign for a quotient, means for detecting the sign of a quotient produced by the division of the dividend by the divisor, means for comparing the expected sign of the quotient with the actual sign of the quotient, and means for aborting the division operation if the compared signs differ.

These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.

Brief Description Of The Drawings Figure 1 illustrates a number of binary numbers which may be utilized in a division process practiced using a computer processor.

Figure 2 is a block diagram of a circuit in accordance with the present invention.

Figure 3 is an illustration of an operation carried out using the circuitry of the present invention.

Notation And Nomenclature Some portions of the detailed descriptions which follow are presented in terms of symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.

Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind. The present invention relates to an apparatus for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.

Detailed Description Of The Invention Referring now to Figure 1, there are illustrated a number of binary numbers which may be utilized in a division process utilizing a computer processor. Each of the numbers is illustrated in both its binary and decimal form so that the operation may be more rapidly appreciated. As may be seen, at the left in the figure, three illustrative dividends are given. In the center of the figure, three illustrative divisors are furnished; and at the right, three quotients produced by the division of the dividend by the divisor are shown.

In all of the well known types of division practiced by using an arithmetic and logic unit (ALU) of a computer, the dividend is allotted a first number of bit positions in a register and the divisor is allotted half as many bit positions in a register. Thus, in an ALU in which an eight bit dividend is the largest dividend which can be handled, a divisor has four bits; and the remainder and the quotient are similarly allotted four bits each. At each iteration as the division progresses, each of the bits of the dividend is shifted left to the next highest order position so that the most significant bit is shifted out; the divisor is subtracted or added to the high order bits remaining; and the quotient bit is appended at the least significant bit position left empty by the initial shift.When the appropriate number of steps have occurred (typically equal to the number of bits in the divisor), the highest order bits remaining in the register which originally held the dividend represent the final remainder and the lowest order bits represent the quotient.

Thus, if (as shown in the first line of Figure 1) a dividend of decimal fifty-four (binary 0011 0110) is divided by decimal seven (0111), a quotient of decimal seven with a remainder of five (binary 0101 0111) results. The four bits to the right in the result represent the quotient while the four bits to the left represent the remainder. As may be appreciated, division by zero has not occurred in the example given on the first line of Figure 1 so the number which is the quotient is not infinitely large. Moreover, the divisor is sufficiently large with respect to the dividend that the quotient which results fits within the four lowest order bit positions (i.e., 0111 equals decimal seven) and the remainder is left in the four highest order bit positions (i.e.., 0101 equals decimal five).In addition, the result includes a zero in the most significant bit position indicating correctly that the result is positive.

However, if a dividend of decimal fifty-four (binary 0011 0110) is divided by decimal two (binary 0010) as shown in the second line of Figure 1, a result of twenty-seven (binary 0001 1011) should be produced. As may be seen in the column to the right in Figure 1, five bits are required to represent the quotient. This requires that the highest order bit of the quotient overflow into the position reserved for the remainder in the register which retains the result. Thus, although the divisor is not zero, an overflow occurs and produces an incorrect result because of the small size of the divisor relative to the dividend.

It should be noted that the registers normally. utilized in an actual processor are significantly larger than the eight bits shown for the dividend of the exemplary register so that most numbers are not affected by this problem of register size. In fact, the typical registers are sixteen or thirty-two bits in length; Moreover, if a dividend of decimal fifty-four (binary 0011 0110) is divided by decimal fifteen (binary 1111) a quotient of decimal three with a remainder of nine (1001 0011) should be produced. However, four bit positions are an insufficient number of bit positions to represent both the number and the sign bit of the divisor. Consequently, the divisor appears to be a negative number since it carries a one in its highest order position; and the division process will produce an incorrect result.

The prior art has provided solutions to the problem of overflow caused by a divisor which is too small for the dividend and consequently produces too large a quotient for the size of register available in the case of unsigned numbers. However, where the numbers manipulated are signed and the process used to accomplish the division is a nonrestore process, the prior art solutions do not work.

Moreover, the problem created by divisors and dividends which are out of the range of their respective registers is a problem which has been very difficult for the prior art to resolve without very complicated steps. These steps have often required the addition of significant hardware to the processor and have substantially slowed the division process.

Each of these three registers is, in the preferred embodiment, a thirty-two bit register although for the purpose of this explanation registers of smaller sizes are described so that the process will require fewer steps than would a thirty-two bit division operation. The binary numbers stored in the registers as dividend and divisor are transferred at various steps of the operation to the ALU 12 where various shifts, additions, and subtractions occur under control of the logic circuits.

In the process of non-restore division of signed numbers, the ALU 12 is first used to determine whether each of the dividend and the divisor are negative or positive by testing the value of the bit in the highest order bit position; and values which indicate whether they are negative or positive are stored. A latch 17 is utilized to store a one bit A value which indicates whether the dividend is positive or negative. A second latch 18 is utilized to store a one bit B value which indicates whether the divisor is positive or negative.

Before the division process is begun, a dividend which is negative is complemented. In a similar manner, a divisor if negative is complemented. A logic circuit 19 (which may be combinational logic circuitry constructed in a manner well known to the prior art) is illustrated as controlling the ALU 12 to complement the values of the dividend and the divisor if the values in the A and B latches indicate that this operation is necessary. In the preferred embodiment of the invention, the circuit 19 reviews the values stored in the latches 17 and 18 and, if required, directs the ALU 12 to complement the dividend or the divisor. The operations of the ALU 12 to accomplish complementing may be controlled by microcode stored in read only memory of a microprocessor of which the ALU 12 and its associated circuitry are a part.

The particular microcode is that necessary to accomplish the individual operations of the process of complementing a binary number. For example, each of the bits of the binary number must be inverted and a one value added to the lowest order bit to provide the correct twos complement result.

Each of these steps is a step which may be typically programmed in microcode within a conventional microprocessor to be performed by the ALU.

In addition to this circuitry for preparing the binary numbers for division, once the binary numbers have been complemented, a test in accordance with the present invention is carried out to determine whether division by zero or register overflow will occur because the divisor is too small in relation to the dividend and will, consequently, produce more quotient bits than the registers are capable of handling. This operation utilizes a logic circuit 23 which causes the ALU 12 to subtract the divisor in whatever form it is presently retained in the register 15 from the highest order bits of the dividend, the bits presently held in the DIVA register 13.The logic circuit 23 may also be implemented as combinational logic gates and cooperates with a test circuit 25 which reviews the carryout bit from the result produced by the subtraction and aborts the division operation if the result is positive as indicated by a one valued carryout bit. A positive or zero result indicates that the division will produce a quotient which is too large for the DIVB register into which the resulting quotient is to fit. This result will occur both in the case of an overflow caused by the divisor being too small in relation to the divisor and an overflow caused by division by zero.

All of these steps are taken before the division begins. In addition to the circuits which allow the ALU 12 to prepare the signed numbers to be used in the non-restore division process, the non-restore process described in the abovementioned patent application utilizes circuitry to control each step of the non-restore process. A exclusive NOR (XNOR) circuit 22 determines the value of the individual quotient bits generated by each subtraction or addition and whether the next operation is to be one of addition or subtraction. The circuit 22 may be constructed in a manner well known to the prior art, for example, as combinational logic gates adapted to produce the output of an XNOR truth table in response to a pair of binary input values.

An iteration counter 24 is utilized to count the number of individual addition or subtraction steps in the process.

Each of these steps is described in detail below. A logic circuit 26 controls the process which occurs at each step depending on whether the step is the first forced subtraction step or one of the XNOR-determined iterations which follow. Between each of the steps, the result arrived at by the step is transferred back to the DIVA and DIVB registers prior to the next operation. The logic circuit 26 also tests the value of result produced by the last iteration to determine whether the value of the divisor is to be added back to the final partial remainder to correct the remainder portion thereof. The logic circuit 26 may in the preferred embodiment be combinational logic circuitry constructed in a manner well known to those skilled in the art to utilize microcoded instructions to cause the ALU 12 to carry out the steps of the subtraction, addition, and restore operations.

A logic circuit 20, which may be implemented using combinational logic gates, controls the ALU 12 to cause it to complement the value of the final remainder if the value A is negative and to complement the value of the final quotient determined by the non-restore division process depending on the result of an exclusive OR (XOR) operation using the A and B values. As with the other operations outlined above, the specific operations of the ALU 12 may be implemented using stored microcode.

Although individual logic circuitry is utilized in the preferred embodiment of the invention, it would be possible to implement the entire operation of the circuit 10 to provide non-restore division of the signed values under control of microcode stored in the read only memory of a microprocessor of which the ALU 12 and its associated circuitry are a part. The particular microcode necessary would be that necessary to accomplish the individual operations described below in order to accomplish each of the steps of the non-restore division process with signed binary numbers.

In addition to the circuitry already described, the circuit 10 also includes a comparator circuit 27 which compares the sign of the ultimate result of the division operation with the sign which should be expected from the operation with the values of the original dividend and divisor. If the signs differ, then the result produced by the division process is incorrect because the result is not within the allowed number range (positive or negative) for the given number of bits in the operation so that an incorrect sign is produced by the operation. To accomplish this comparison, the circuit 27 receives an output from the logic circuit 20 which is used to decide the final sign of the quotient.

This output indicates whether the sign should be positive or negative. The output of the logic circuit 20 is compared to the actual sign of the quotient. If they differ, the result is incorrect because of sign overflow. This is a very simple and elegant manner of determining the influence of sign overflow on the result of a non-restore division process. This method may be used in the same manner with division processes other than non-restore division.

Referring now to Figure 3, a diagram is illustrated which outlines the steps of the operation necessary to perform division of signed binary numbers using circuitry provided to accomplish division of unsigned binary numbers.

At the first step of the process, the binary number which is to be the dividend is passed through the ALU 12 in order to determine its sign and is loaded into the DIVA and DIVB registers 13 AND 14. In the example, a binary number equivalent to the decimal number minus forty is used. As may be seen in the example, the binary value one in the highest order bit indicates that the number is negative.

This value one of the sign is stored as the value A in the latch 17. The high order bits of the number are held in the DIVA register 13, and the low order bits of the number are held in the DIVB register 14.

As has been pointed out above, in accomplishing division, a processor moves through a number of loops in which a shift, subtract or add, and a logical step occur. The number of loops of the division process must be counted. Since the number of loops in the division process is equal to the number of bits of the divisor, the iteration counter 24 is loaded with a value equal to the size of the divisor less one bit (because the forced subtraction step is taken before the divide loop controlled by the iteration counter 24 is entered). In the case of the preferred embodiment, this may be equal to seven, fifteen, or thirty-one since divisors of eight, sixteen, and thirty-two bits are encountered.After the first step of the division operation (an automatic forced subtraction step), the value in the iteration counter 24 is reduced by one during each iterative step of the unsigned divide operation. This allows the process to loop through the steps the appropriate number of times for the size of the divisor. As may be seen, seven iterations are provided in the example.

Next, the dividend in the DIVA and DIVB registers is complemented if it is a negative number and the result replaced in the DIVA and DIVB registers. Since the exemplary dividend is negative, the binary number is complemented by the ALU 12 to produce a positive number.

The binary number which is to be the divisor is also processed through the ALU 12 to determine its sign and is placed in the temporary register. In the example, the number is a binary number which is equivalent to the decimal number negative ten. The sign is stored as a value B; in the example, the divisor is negative so the value of B is one. If the divisor is a negative number, it is complemented in the ALU 12; and the result is placed back in the temporary register. Since the exemplary divisor is negative, the binary value is complemented and the complement is placed back in the temporary register 15.

At this point, a check is made to determine if the divisor is less than the highest order bits of the dividend zero in order to prevent division by zero which is a prohibited operation. In accordance with the present invention, the circuit 23 causes the ALU 12 to subtract the value of the divisor presently held in the register 15 from the high order bits of the dividend presently held in the register 13. A complemented value is used for the divisor or for the dividend in this operation if either of them is negative.

If the result of the subtraction is positive, the high order bits of the dividend are divisible by the divisor. This means that the quotient will occupy more bit positions than are available in the DIVB register so that overflow will occur. In any case in which the result of the subtraction is zero or a positive number, the carry value will be one.

Thus, the value of the carry of the result is transferred to the circuit 25 which issues an abort signal to the circuit 19 if there is a one value carry signal indicating that the result is positive. In such a case, some other method of accomplishing the division (software) must be used.

In the present example, the binary value (0000 1010) in the register 15 is the complement of the original divisor. In order to subtract this number from the high order bits of the dividend, it is again complemented to its original value of binary (1111 0110) and added to the value in the DIVA register, binary (0000 0001) which is the complement of the original dividend. The result of the subtraction is the binary number (1111 0111), a negative number which produces no carry. The lack of a carry indicates that the high order bits of the dividend are not divisible by the divisor, so there will be no overflow caused by the quotient being too large to fit the register. Consequently, the operation may proceed.Had the result produced a carry value of one indicating a positive or zero result from the subtraction, the high order bits of the dividend would be divisible by the divisor; and the quotient would overflow the register.

This would require that the operation be aborted at this point. In such a case, the division would probably be carried out by software through some other algorithmic process.

The process then proceeds to the first step of the division operation in which the sixteen bit dividend representing the decimal number four hundred (now positive) is divided by the eight bit divisor representing the number ten (also now positive). In accordance with the invention of the previous patent application, the most significant bit of the dividend is stored apart from the ALU 12 as the first step. In the preferred embodiment, this storage takes place at an input latch in the XNOR circuit 22. Next the dividend is shifted left by one bit, and the divisor is subtracted from the remaining highest order bits of the dividend. The twos complement of the divisor is added to the remaining high order bits of the dividend in order to accomplish the subtraction in the ALU 12.

This subtraction during the first iteration of the division process is a forced subtraction controlled by the logic circuit 26. Thereafter, the circuit 26 allows the operation accomplished to be addition or subtraction depending on the result of the operation in the previous iteration as determined by the XNOR circuit 22. The result of this forced subtraction (the sum of the highest order bits of the dividend which remain after the left shift and the twos complement of the divisor) may produce a carryout value of one or may not produce a carryout value (a zero). It should be noted that the carryout bit produced is inverted in the case of a subtraction which produces a negative number indicating that the divisor is greater than the partial remainder.

An XNOR operation is carried out by the XNOR circuit 22 described in the above-mentioned patent application using the carryout value and the most significant bit of the dividend stored before the subtraction. The result of the XNOR operation determines the first bit of the quotient and the next operation to be performed. If the XNOR operation produces a one value, this indicates that the quotient is to be a one and that the next operation should be a subtraction. If the XNOR operation produces a zero value, this indicates that the quotient is to be a zero and that the next operation should be an addition.

As may be seen, when this operation is performed with the most significant digit of the dividend and the carryout of the first forced subtraction in the example, an XNOR result of zero is obtained. Consequently, the first quotient bit is a zero; and the next operation to be performed is an addition.

The high order bits which resulted from the forced subtraction operation are concatenated by the ALU 12 with the lower order bits of the dividend which were not used in the subtraction to produce the next interim dividend and with the new quotient bit. These values are placed in the DIVA and DIVB registers 13 and 14. The new quotient bit is placed in the empty lowest order bit position of the DIVB register 14.

At this point after the forced subtraction of the first iteration of the division process, a number of additional iterations occur equal to the number stored in the iteration counter 24 to accomplish the division process. In the second iteration, the most significant bit of the interim dividend is again stored in the XNOR circuit 22 apart from the ALU 12; and the interim dividend is shifted left by one bit. Then the addition operation determined by the result of the XNOR operation in the last stage is performed by adding the divisor to the highest order bits remaining of the interim dividend. Again, this operation produces a result which may or may not produce a carryout. In this case, no carryout is produced. The zero value is transferred to the XNOR circuit 22.Another XNOR operation is performed using the new carryout bit value and the most significant bit which was stored before the subtraction.

This produces a XNOR value of zero indicating that the next operation is to be an addition and that the next quotient bit is a zero.

Again, the result of the addition operation is concatenated with the low order bits of the previous interim dividend to produce the next interim dividend; and the new quotient bit is appended in the lowest order bit position. The most significant bit of the new interim dividend is again stored, and the interim dividend is shifted left by one bit. Then the addition operation determined in the last stage is performed by adding the divisor to the highest order bits remaining of the interim dividend. Again, this operation produces a result which may or may not produce a carryout.

In the present case, a carryout bit of one is generated. A XNOR operation is then performed using the new carryout value and the most significant bit stored before the addition. This produces a XNOR value indicating that the next operation is to be a subtraction and that the next quotient bit is a one.

Again, the result of the addition operation is concatenated with the low order bits of the previous interim dividend to produce the next interim dividend; and the new quotient bit is placed in the lowest order bit position. In iteration four, the most significant bit of the new interim dividend is again stored; and the interim dividend is shifted left by one bit. Then, the subtraction operation determined in the last stage is performed by adding the twos complement of the divisor to the highest order bits remaining of the interim dividend. Again, this operation produces a result which may or may not produce a carryout. In this case, a carryout is produced because the result of the subtraction provides a negative number. A XNOR operation is then performed using the new carryout bit value and the most significant bit stored before the subtraction.This produces a XNOR value of zero indicating that the next operation is to be an addition and the next quotient bit is a zero.

This process continues as described above through four additional iterations, the last of which is an addition operation. The result of this final addition is concatenated with the low order bits of the previous interim dividend and the new quotient bit to produce a result.

However, since the last XNOR operation produced a zero indicating that the divisor was still greater than the partial remainder, the divisor must be restored at this point. The divisor is added to the eight highest order bits to produce the final result. The eight bits to the right in the DIVB register 14 then represent the quotient, a value of forty, while the eight high order bits in the DIVA register 13 represent the remainder, a value of zero for the division of four hundred by ten.

Once this result is reached, the values A and B are utilized to determine what are expected to be the correct signs for the result. If the value of A is a one indicating that the dividend is negative, then the remainder is complemented by the ALU 12 to provide a remainder value having the same sign as the original dividend. A value which is the XOR of the values A and B is used to determine the sign of the quotient. If the result of the XOR operation is one, then the quotient reached is complemented. Since the XOR of the values A and B is equal to zero in the present case where both were one, the value of the quotient not complemented by the ALU 12. As may be seen, when these operations are carried out on the results provided by the division operation, the binary number produced is a number equal to the decimal number negative forty. Thus, the correct result is reached.

However, had one of the original dividend or divisor been too large for the register in which it was held so that the number actually overflowed into the sign position of the register, the result obtained may still be incorrect and require the aborting of the division by signalling a controlling circuit such as a central processing unit when the compared signs differ. In order to determine if this has in fact occurred, the sign which such a division should have produced is compared with the sign of the result. If they are the same, the result is correct. If they are different, the result is incorrect; and the division must be aborted and accomplished in a different way. The sign of the correct result is easily obtained from the value provided by the result of the XOR operation. A value of zero indicates that the dividend and divisor were either both positive or both negative. In either case, the result of the operation is positive. Since the present result is positive, the result has not been affected by overflow of the dividend or divisor causing an incorrect sign.

Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.

Claims (10)

1. An arrangement for detecting an incorrect result produced by division in a computer ALU comprising means for storing the sign of a dividend, means for storing the sign of a divisor, means for utilizing the sign of the dividend and the sign of the divisor to indicate an expected sign for a quotient, means for detecting the sign of a quotient produced by the division of the dividend by the divisor, means for comparing the expected sign of the quotient with the actual sign of the quotient, and means for aborting the division operation if the compared signs differ.

2. An arrangement for detecting an incorrect result produced by division in a computer ALU as claimed in Claim 1 further comprising means for subtracting the divisor from the highest order bits of the dividend prior to any steps of a division operation, and means for aborting the division operation if the result of the subtraction is positive.

3. An arrangement for detecting an incorrect result produced by division in a computer ALU as claimed in Claim 1 in which the means for utilizing the sign of the dividend and the sign of the divisor to indicate an expected sign for a quotient comprises means for accomplishing a XOR logic operation with the sign of the dividend and the sign of the divisor as input values, and means for complementing the quotient if a result of the XOR logic operation is one.

4. An arrangement for detecting an incorrect result produced by division in a computer ALU as claimed in Claim 1 in which the means for comparing the expected sign of the quotient with the actual sign of the quotient comprises a comparator.

5. An arrangement for detecting an incorrect result produced by division in a computer ALU as claimed in Claim 1 in which the means for aborting the division operation if the compared signs differ comprises means for signalling a controlling circuit when the compared signs differ.

6. An arrangement for detecting an incorrect result produced by a non-restore division process in a computer ALU comprising means for storing the sign of a dividend, means for storing the sign of a divisor, means for utilizing the sign of the dividend and the sign of the divisor to indicate an expected sign for a quotient, means for detecting the sign of a quotient produced by the division of the dividend by the divisor, means for comparing the expected sign of the quotient with the actual sign of the quotient, and means for aborting the division operation if the compared signs differ.

7. An arrangement for detecting an incorrect result produced by a non-restore division process in a computer ALU as claimed in Claim 6 further comprising means for subtracting the divisor from the highest order bits of the dividend prior to any steps of a division operation, and means for aborting the division operation if the result of the subtraction is positive.

8. An arrangement for detecting an incorrect result produced by a non-restore division process in a computer ALU as claimed in Claim 6 in which the means for utilizing the sign of the dividend and the sign of the divisor to indicate an expected sign for a quotient comprises means for accomplishing a XOR logic operation with the sign of the dividend and the sign of the divisor as input values, and means for complementing the quotient if a result of the XOR logic operation is one.

9. An arrangement for detecting an incorrect result produced by a non-restore division process in a computer ALU as claimed in Claim 6 in which the means for comparing the expected sign of the quotient with the actual sign of the quotient comprises a comparator.

10. An arrangement for detecting an incorrect result produced by a non-restore division process in a computer ALU as claimed in Claim 6 in which the means for aborting the division operation if the compared signs differ comprises means for signalling a controlling circuit when the compared signs differ.