CN111813375A

CN111813375A - Modulo arithmetic processing method and related product

Info

Publication number: CN111813375A
Application number: CN202010820882.1A
Authority: CN
Inventors: 刘君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-08-14
Filing date: 2020-08-14
Publication date: 2020-10-23

Abstract

The embodiment of the application provides a modulus operation processing method and a related product, wherein an operation circuit comprises a controller, a cache, a subtracter module and a shift register module, and the controller compares whether a current dividend is more than or equal to 2 times of an original divisor; under the condition that the current dividend is more than or equal to 2 times of the original divisor, the controller inputs the original divisor into the shift register module, the shift register module shifts the original divisor and outputs a current decrement which is N times of the original divisor and less than the current dividend to the subtractor module; the subtractor module executes a current subtraction operation, and the current subtraction operation is used for calculating the difference value between the current dividend and the current subtraction value; in the case where the difference between the current dividend and the current decrement is smaller than the original divisor, the controller divides the difference between the current dividend and the current decrement by the remainder of the original divisor. The embodiment of the application can shorten the time required by the modular operation.

Description

Modulo arithmetic processing method and related product

Technical Field

The present application relates to the field of image processing technologies, and in particular, to a modulo operation processing method and a related product.

Background

In the fourth generation mobile communication technology (4G) and the fifth generation mobile communication technology (5G), many functional blocks are implemented by hardware in order to speed up signal processing. Modular arithmetic (i.e., the operation of dividing and then taking the remainder) is widely used in transceivers (e.g., the modular arithmetic is needed for channel coding and decoding in the transceiver). Since the division is needed for the modulo operation, and the division circuit is relatively complex, the division is usually avoided as much as possible to directly take the remainder.

Currently, a subtraction circuit is generally used to perform a modulo operation, and the dividend is subtracted by the divisor once at a time until the obtained result is smaller than the divisor, and the obtained result is used as a remainder. However, when the dividend and the divisor are different from each other, many subtraction iterations are required to calculate the remainder, and the modulo operation requires a long time.

Disclosure of Invention

The embodiment of the application provides a modular arithmetic processing method and a related product, and an arithmetic circuit can shorten the time required by modular arithmetic through a subtraction circuit and a shift register module.

A first aspect of an embodiment of the present application provides an arithmetic circuit, including a controller, a cache, a subtractor module, and a shift register module, where:

the controller compares whether a current dividend is more than or equal to 2 times of an original divisor, the original divisor and the current dividend are binary numbers, and the current dividend is the original dividend or a dividend obtained by the last subtraction operation;

when the current dividend is more than or equal to 2 times of the original divisor, the controller inputs the original divisor into the shift register module, the shift register module shifts the original divisor and outputs a current decrement which is N times of the original divisor and less than the current dividend to the subtractor module, wherein N is an integer more than or equal to 2;

the subtractor module executes a current subtraction operation, wherein the current subtraction operation is used for calculating a difference value between the current dividend and the current decrement and storing the difference value between the current dividend and the current decrement into a cache;

the controller determines a difference between the current dividend and the current divisor as a remainder of dividing the original dividend by the original divisor, if the difference is smaller than the original divisor.

A second aspect of the present embodiment provides a modular arithmetic processing method, including:

comparing whether the current dividend is more than or equal to 2 times of the original divisor, wherein the original divisor and the current dividend are binary numbers, and the current dividend is the original dividend or the dividend obtained by the last subtraction operation;

if the current dividend is more than or equal to 2 times of the original divisor, inputting the original divisor into a shift register module for shift processing to obtain a current decrement which is N times of the original divisor and less than the current dividend, wherein N is an integer more than or equal to 2;

performing a current subtraction operation, wherein the current subtraction operation is used for calculating a difference value between the current dividend and the current decrement, and storing the difference value between the current dividend and the current decrement in a cache;

and if the difference value between the current dividend and the current reduced number is smaller than the original divisor, taking the difference value between the current dividend and the current reduced number as the remainder of dividing the original dividend by the original divisor.

Optionally, the method further includes:

if the current dividend is less than 2 times of the original divisor and the current dividend is greater than or equal to the original divisor, taking the difference value between the current dividend and the original divisor as the remainder of dividing the original dividend by the original divisor;

and if the current dividend is less than 2 times of the original divisor and the current dividend is less than the original divisor, taking the current dividend as the remainder of dividing the original dividend by the original divisor.

Optionally, the method further includes:

if the difference between the current dividend and the current decrement is larger than the original divisor, the difference between the current dividend and the current decrement is used as a new current dividend, and the step of comparing whether the current dividend is larger than or equal to 2 times of the original divisor is executed.

Optionally, the inputting the original divisor into the shift register module for shift processing to obtain a current divisor that is N times the original divisor and smaller than the current dividend includes:

comparing the size of the highest m-bit binary number of the current dividend with the size of the original divisor, wherein the binary significant digit of the original divisor is m, and the binary significant digit of the current dividend is n; m and n are positive integers;

if the highest m-bit binary number of the current dividend is greater than or equal to the original divisor, inputting the original divisor into a shift register module to perform p times of first-class left shift alignment processing to obtain a current divisor; each time the first-class left-shift alignment process aligns the highest bit of the original divisor with the highest bit of the current dividend which is not aligned;

if the unaligned digit of the current dividend is greater than or equal to m, continuing to execute the first-class left-shift alignment processing; and if the unaligned digit of the current dividend is less than m, setting the unaligned digit of the current divisor to zero.

Optionally, the method further includes:

if the highest m-bit binary number of the current dividend is smaller than the original divisor, inputting the original divisor into a shift register module to perform u times of second-class left shift alignment processing to obtain a current divisor; each time the second type of left shift alignment processing aligns the highest bit of the original divisor with the unaligned highest bits of the current dividend except the highest bit;

if the unaligned digit except the highest digit of the current dividend is greater than or equal to m, continuing to execute the second type of left shift alignment processing; and if the unaligned digits of the current dividend except the highest digit are less than m, setting the unaligned digits of the current dividend to zero.

Optionally, after the difference between the current dividend and the current divisor is used as a remainder of dividing the original dividend by the original divisor, or after the current dividend is used as a remainder of dividing the original dividend by the original divisor, the method further includes:

calculating the current quotient corresponding to the current decrement obtained each time according to the number of left shift alignment processing in the current decrement obtained each time and the displacement of each left shift alignment processing;

and taking the sum of the current quotients corresponding to the current deductions obtained each time as the quotient of the original dividend divided by the original divisor.

Optionally, the calculating a current quotient corresponding to the current decrement obtained each time according to the number of left shift alignment processes in the current decrement obtained each time and the displacement amount of each left shift alignment process includes:

if the left shift alignment processing is first-class left shift alignment processing, the binary significant digit of the current decrement obtained at the current time is n, the total number of times of the first-class left shift alignment processing is p, and the current quotient corresponding to the current decrement obtained at the current time is calculated according to the following formula:

if the left shift alignment processing is second type left shift alignment processing, the binary significant digit of the current decrement obtained at the current time is n, the total number of times of the second type left shift alignment processing is u, and the current quotient corresponding to the current decrement obtained at the current time is calculated according to the following formula:

and H is the current quotient corresponding to the current decrement obtained at the current time.

Optionally, before the comparing whether the current dividend is greater than or equal to 2 times the original divisor, the method further includes:

calculating a ratio of the original dividend to the original divisor;

the step of comparing whether the current dividend is greater than or equal to 2 times the original divisor is performed in a case where a ratio of the original dividend to the original divisor is greater than a first threshold.

A third aspect of the embodiments of the present application provides a modular arithmetic processing apparatus, including a processor and a memory, where the memory is used for storing a computer program, and the computer program includes program instructions, and the processor is configured to call the program instructions to execute the modular arithmetic processing method in the second aspect of the embodiments of the present application.

A fourth aspect of the embodiments of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program causes a computer to execute a modulo operation processing method as in the second aspect of the embodiments of the present application. .

A fifth aspect of embodiments of the present application provides a computer program product, wherein the computer program product comprises a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps as described in the second aspect of embodiments of the present application. The computer program product may be a software installation package.

The arithmetic circuit in the embodiment of the application comprises a controller, a cache, a subtractor module and a shift register module, wherein the controller compares whether a current dividend is more than or equal to 2 times of an original divisor, the original divisor and the current dividend are both binary numbers, and the current dividend is the original dividend or a dividend obtained by the last subtraction operation; when the current dividend is more than or equal to 2 times of the original divisor, the controller inputs the original divisor into the shift register module, the shift register module shifts the original divisor and outputs a current decrement which is N times of the original divisor and less than the current dividend to the subtractor module, wherein N is an integer more than or equal to 2; the subtractor module executes a current subtraction operation, wherein the current subtraction operation is used for calculating a difference value between the current dividend and the current decrement and storing the difference value between the current dividend and the current decrement into a cache; the controller determines a difference between the current dividend and the current divisor as a remainder of dividing the original dividend by the original divisor, if the difference is smaller than the original divisor.

The arithmetic circuit of the embodiment of the application realizes the modular operation through the subtracter module and the shift register module, and can excavate the current divisor which is N times of the original divisor as much as possible through one-time iteration of the shift register module, thereby reducing the iteration times of the subtraction operation of the subtracter module and further shortening the time required by the modular operation.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an operational circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a first type of left shift alignment process provided in an embodiment of the present application;

FIG. 3 is a diagram illustrating a second type of left shift alignment process according to an embodiment of the present disclosure;

FIG. 4 is an exemplary diagram of a modulo operation provided by an embodiment of the present application;

FIG. 5 is an exemplary diagram of a quotient calculation provided in an embodiment of the present application;

FIG. 6 is a schematic flow chart of a modulo arithmetic processing method provided in the present application;

FIG. 7 is a schematic flow chart of another modulo operation processing method provided in the present application;

FIG. 8 is a schematic flow chart of another modulo operation processing method provided in the present application;

FIG. 9 is a schematic flow chart of another modulo operation processing method provided in the present application;

FIG. 10 is a schematic flow chart of another modulo operation processing method provided in the present application;

fig. 11 is a schematic structural diagram of a modulo arithmetic processing apparatus according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of another modulo operation processing apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The embodiment of the application discloses a modular arithmetic processing method and a related product, which can shorten the time required by modular arithmetic.

The following are detailed below.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an arithmetic circuit according to an embodiment of the present disclosure. As shown in fig. 1, the arithmetic circuit 100 includes a controller 11, a buffer 12, a subtractor module 13, and a shift register module 14. The buffer 12 is used for storing the original dividend and the original divisor, and the result obtained by each subtraction operation. The subtractor module 13 is configured to perform subtraction, and the shift register module 14 is configured to perform shift processing on data input to the shift register module 14. The controller 11 is configured to control the subtractor module 13 to perform the number of times of the subtraction operation and determine whether a result of the subtraction operation is a remainder of dividing the original dividend by the original divisor (i.e., a result of the modulo operation).

In the embodiment of the present application, the controller 11 may be connected to the buffer 12, and the controller 11 may send a control instruction to the buffer 12, input data (e.g., an original dividend) in the buffer 12 to the subtractor module 13, and input data (e.g., an original divisor) in the buffer 12 to the shift register module 14. The controller 11 may also send a control instruction to the shift register module 14 to control the shift register module 14 to shift the input data. The controller 11 may also send a control instruction to the subtractor module 13 to control the subtractor module 13 to perform subtraction processing on the data input from the buffer 12 and the data input from the shift register module 14.

The subtractor module 13 may be configured to perform the subtraction, and the subtractor module 13 may include one or more subtractors, and may process a plurality of subtractions simultaneously in parallel. The shift register module 14 may include one or more shift registers, and may perform shift processing of a plurality of data simultaneously. Each shift register may be composed of a plurality of flip-flops, each flip-flop for storing 1-bit binary data.

The cache 12 is a memory that can perform high-speed data exchange. The buffer 12 may be connected to other memories for loading data (e.g., an original dividend and an original divisor) from the other memories, and the result of the subtraction performed by the subtractor module 13 may also be input to the buffer 12 for storage.

The controller 11 may be a processor having a dedicated function for processing modulo arithmetic, or may be a processor having a general-purpose function.

The arithmetic circuit 100 of the embodiment of the present application may be integrated in a chip, and the controller 11, the buffer 12, the subtractor module 13, and the shift register module 14 in the arithmetic circuit 100 may be integrated into one module, or may be independent modules respectively.

The modulo operation may also be referred to as a modulo operation, a remainder operation, etc., and is for obtaining a remainder of the dividend following the divisor.

The operation circuit 100 of the embodiment of the present application can be applied to low-density parity-check (LDPC) coding and decoding, and Turbo coding and decoding of a transceiver.

The existing scheme is to use subtraction to make modulus, each time the original dividend is subtracted by the original divisor, the obtained result is used as a new dividend, and then the original divisor is subtracted by the new dividend until the new dividend is smaller than the original divisor, and the obtained result can be used as a remainder. The following short code shows a commonly used algorithm for hardware modulo circuits, exemplified by mod (2047, 5):

in the above short codes, divsor represents a divisor, divdensd represents a dividend, and remainder represents a remainder. As can be seen from the above short codes, for a dividend of 2047 and a divisor of 5, only the divisor can be subtracted in each subtraction iteration, and the final remainder can be obtained only by cycling 409 times to obtain the remainder, which requires a large number of subtraction iterations and a long time for modulo calculation.

The controller 11 compares whether the current dividend is greater than or equal to 2 times of the original divisor, the original divisor and the current dividend are both binary numbers, and the current dividend is the original dividend or the dividend obtained by the last subtraction operation;

when the current dividend is greater than or equal to 2 times of the original divisor, the controller 11 inputs the original divisor into the shift register module 14, the shift register module 14 shifts the original divisor and outputs a current divisor that is N times of the original divisor and smaller than the current dividend to the subtractor module 13, where N is an integer greater than or equal to 2;

the subtractor module 13 performs a current subtraction operation, where the current subtraction operation is used to calculate a difference between the current dividend and the current decrement, and store the difference between the current dividend and the current decrement in the buffer 12;

in the case where the difference between the current dividend and the current divisor is smaller than the original divisor, the controller 11 takes the difference between the current dividend and the current divisor as the remainder of dividing the original dividend by the original divisor.

In this embodiment, if the current dividend is greater than or equal to 2 times the original divisor, the shift register module 14 shifts the original divisor to obtain a current decrement that is N times the original divisor and smaller than the current dividend. The current decrement obtained by the shifting processing is at least 2 times of the original divisor, if the current dividend is less than 2 times of the original divisor, the current decrement obtained by the shifting processing is more than the current dividend, and the shifting processing cannot be carried out.

The original divisor, which is the first divisor, does not change during this iteration. The modulo operation in the embodiment of the present application is still implemented by using a subtractor, but the subtraction number and the subtracted number at each time are no longer fixed values (the fixed value is an original divisor), and the current subtracted number at each time of the subtraction operation is a current dividend obtained by the last subtraction operation of the subtractor module 13; the number of subtractions of each subtraction operation is a current number of subtractions which is N times of the original divisor and is smaller than the current dividend. When the shift register module 14 shifts the original divisor to the leftAnd determining the current decrement obtained by shifting the original divisor according to the number of times of left shifting and the number of bits of each shifting. Wherein each left shift by one bit, the original divisor is changed to 2 times the original divisor. For example, when the shift register module 14 performs a left shift process on the original divisor, if the original divisor is shifted left three times, and the number of bits left shifted each time is 7 bits, 4 bits, and 1 bit, the shift register module 14 shifts left the original divisor to obtain a current divisor (2 bits) that is the current divisor⁷+2⁴+2¹)，N＝(2⁷+2⁴+2¹). As can be seen, one iteration can dig out multiple 2's of the original divisor^aThe multiplied current subtraction number can only subtract N times of the original divisor in each subtraction iteration, so that the iteration times of the subtraction operation of the subtractor module are reduced, and the time required by the modulo operation can be shortened.

The embodiment of the application can be suitable for modulus operation under the condition that the original dividend is far larger than the original divisor.

Alternatively, in the case that the difference between the current dividend and the current decrement is greater than the original divisor, the controller 11 takes the difference between the current dividend and the current decrement as a new current dividend, and performs the step of comparing whether the current dividend is greater than or equal to 2 times the original divisor.

If the difference between the current dividend and the current divisor is larger than the original divisor, which indicates that the difference is not the final remainder, the difference is used as the new current dividend, the step of comparing whether the current dividend is larger than or equal to 2 times of the original divisor is executed again, and the next iteration of subtraction is executed.

Alternatively, in the case where the current dividend is less than 2 times the original divisor and the current dividend is greater than the original divisor, the controller 11 takes the difference between the current dividend and the original divisor as the remainder of dividing the original dividend by the original divisor;

in the case where the current dividend is less than 2 times the original divisor and the current dividend is less than the original divisor, the controller 11 divides the current dividend by the original divisor as a remainder of the original dividend.

In the embodiment of the present application, if the current dividend is less than 2 times of the original divisor, the current divisor obtained by the shift processing is greater than the current dividend, and the shift processing cannot be performed. In this case, the embodiment of the present application does not use shift processing, and the remainder of dividing the original dividend by the original divisor can be quickly determined by directly using one subtraction operation.

Optionally, the inputting of the original divisor into the shift register module 14 by the controller 11, the shifting processing performed by the shift register module 14 on the original divisor, and outputting a current divisor that is N times the original divisor and smaller than the current dividend to the subtractor module 13 includes:

the controller 11 compares the size of the highest m-bit binary number of the current dividend with the size of the original divisor, where the binary significand of the original divisor is m, and the binary significand of the current dividend is n; m and n are positive integers; n is greater than m;

when the highest m-bit binary number of the current dividend is greater than or equal to the original divisor, the controller 11 inputs the original divisor into the shift register module 14, and the shift register module 14 performs p times of first-class left shift alignment processing on the original divisor to obtain a current subtrahend, and inputs the current subtrahend into the subtractor module 13; each time the first-class left-shift alignment process aligns the highest bit of the original divisor with the highest bit of the current dividend which is not aligned; p is a positive integer;

in the case that the unaligned number of bits of the current dividend is greater than or equal to m, the shift register module 14 continues to perform the first type left shift alignment process;

in the event that the number of unaligned bits of the current dividend is less than m, the shift register module 14 zeroes the number of unaligned bits of the current divisor.

The significant binary digit of a certain binary number is a digit from a binary digit whose highest bit is not 0 to the lowest bit of the certain binary number. For example, 1101 has a binary significance equal to 4 and 0010 has a binary significance equal to 2.

In the embodiment of the application, the sizes of the highest m-bit binary number of the current dividend and the original divisor are easy to judge, and the sizes of the highest m-bit binary number of the current dividend and the binary number of the original divisor are compared one by one from the high bit to the low bit. For example, if the current dividend is 1789 (decimal, which is default to decimal if the following digits are not specified), the corresponding binary number is 11011111101; the original divisor is 5, which corresponds to a binary number of 101. The number of bits of the current dividend is 11 bits, i.e., n equals 11, and the number of bits of the original divisor is 3 bits, i.e., m equals 3. The highest 3 bits of the current dividend are taken, i.e. the highest bit of the binary number 110, 110 is equal to the highest bit of 101, both are 1, the next highest bit of 110 is 1, the next highest bit of 101 is 0, the next highest bit of 110 is greater than the next highest bit of 101, and therefore 110 is greater than 101. The top 3 bits of the current dividend are larger than the original divisor. For another example, if the current dividend is 1245, its corresponding binary number is 10011011101; the original divisor is 5, which corresponds to a binary number of 101. The number of bits of the current dividend is 11 bits, i.e., n equals 11, and the number of bits of the original divisor is 3 bits, i.e., m equals 3. Taking the top 3 bits of the current dividend, which is a binary number 100, it is clear that the top 3 bits of the current dividend are smaller than the original divisor.

The number of left shifts differs for each left shift alignment process of the first type. Each time the first-class left shift alignment process is to align the highest bit of the original divisor with the highest bit of the current dividend which is not aligned, and to set the unaligned bit of the current divisor to zero in the current subtrahend under the condition that the unaligned bit of the current dividend is less than m or the unaligned bit of the current dividend is 0, thus obtaining the current subtrahend.

Referring to fig. 2, fig. 2 is a schematic diagram of a first type of left shift alignment process according to an embodiment of the present disclosure. As shown in fig. 2, the specific procedure of the first type of left-shift alignment process is explained below by taking the current dividend as 2047 and the original divisor as 5 as an example. 2047 corresponds to a binary number of 11111111111 and 5 corresponds to a binary number of 101. 11111111111 has 11 bits (n is 11), the lowest bit is represented by b0, and the highest bit is represented by b 10; 101 have a total of 3 bits (m is 3), the lowest bit being denoted b0 and the highest bit b 2. Because the binary number "111" of the highest 3 bits of 2047 is greater than the original divisor 101, which meets the precondition of the first-class left shift processing, the original divisor is left-shifted for the first time, because the unaligned highest bit of the current dividend is b10, the original divisor is shifted 8 bits to the left as a whole, after the left shift for the first time, the highest bit b2 of the original divisor is aligned with the b10 bit of the current dividend, the next highest bit b1 of the original divisor is aligned with the b9 bit of the current dividend, the lowest bit b0 of the original divisor is aligned with the b8 bit of the current dividend (as the dark gray data of the current decrement in fig. 2), and the 3 bits of the original divisor subjected to the first left shift are taken as the highest three bits of the current decrement; next, judging that the unaligned digits (b 7-b 0, total 8 digits) of the current dividend are greater than 3, continuing to perform a second left shift on the original divisor, wherein the unaligned highest digit of the current dividend is b7, the original divisor is wholly shifted to the left by 5 digits, after the second left shift, the highest digit b2 of the original divisor is aligned with the b7 digit of the current dividend, the next highest digit b1 of the original divisor is aligned with the b6 digit of the current dividend, the lowest digit b0 of the original divisor is aligned with the b5 digit of the current dividend (such as grey data in the current subtraction in fig. 2), and taking the 3 digits of the original divisor subjected to the second left shift as the 4th to 6 th digits of the current subtraction; next, judging that the unaligned digits (b 4-b 0, 5 digits in total) of the current dividend are still larger than 3, continuing to perform left shift on the original divisor for the third time, because the unaligned highest digit of the current dividend is b4, moving the original divisor to the left by 2 digits as a whole, after the left shift for the third time, aligning the highest digit b2 of the original divisor with the b4 digit of the current dividend, aligning the next highest digit b1 of the original divisor with the b3 digit of the current dividend, aligning the lowest digit b0 of the original divisor with the b2 digit of the current dividend (such as light gray data of the current divisor in fig. 2), and taking the 3 digits of the original divisor subjected to the third left shift as the 7 th to 9 th digits of the current reduced number; next, the unaligned digits (b 1-b 0, 2 digits in total) of the current dividend are judged to be less than 3, and the unaligned digits of the current divisor are set to zero (such as the white data of the current divisor in FIG. 2), that is, the 10 th to 11 th digits of the current divisor are set to zero. The resulting current decrement is 10110110100, and the difference between the current dividend and the current decrement is 1001001011.

Optionally, when the highest m-bit binary number of the current dividend is smaller than the original divisor, the controller 11 inputs the original divisor into the shift register module 14, and the shift register module 14 performs u times of second-class left shift alignment processing on the original divisor to obtain a current divisor, and inputs the current divisor into the subtractor module 13; each time the second type of left shift alignment processing aligns the highest bit of the original divisor with the unaligned highest bits of the current dividend except the highest bit; u is a positive integer;

in the case that the unaligned number of bits of the current dividend other than the most significant bit is greater than or equal to m, the shift register module 14 continues to perform the second type of left shift alignment processing;

in the case that the unaligned number of bits of the current dividend other than the highest bit is less than m, the shift register module 14 sets the unaligned number of bits of the current subtrahend other than the highest bit to zero, or the shift register module 14 sets the unaligned number of bits of the current subtrahend other than the highest bit to zero.

Unless otherwise specified, the current dividend divided by the highest significant digit in the embodiment of the present application refers to the highest significant digit of the binary significant digits divided by the current dividend.

In the embodiment of the application, the left shift numbers of the second type of left shift alignment processing are different. Each time the second type of left shift alignment processing is to align the highest bit of the original divisor with the unaligned highest bit of the current dividend except the highest bit, and to set the unaligned bit of the current dividend except the highest bit to zero in the current deduction when the unaligned bit of the current dividend except the highest bit is less than m or the unaligned bit of the current dividend except the highest bit is 0, so as to obtain the current deduction.

Referring to fig. 3, fig. 3 is a schematic diagram of a second type of left shift alignment process according to an embodiment of the present application. As shown in fig. 3, the specific procedure of the second type of left-shift alignment process is explained below by taking the current dividend as 1245 and the original divisor as 5 as an example. 1245 corresponds to a binary number of 10011011101, and 5 corresponds to a binary number of 101. 10011011101 has 11 bits (n is 11), the lowest bit is denoted by b0, and the highest bit is denoted by b 10; 101 have a total of 3 bits (m is 3), the lowest bit being denoted b0 and the highest bit b 2. Because the binary number "100" of the highest 3 bits of the divisor 1245 is smaller than the original divisor 101, and meets the precondition of the second type of left shift processing, the original divisor is left-shifted for the first time, because the unaligned highest bit except the highest bit of the current dividend is b9, the original divisor is wholly left-shifted by 7 bits, after the left shift for the first time, the highest bit b2 of the original divisor is aligned with the b9 bit of the current dividend, the next highest bit b1 of the original divisor is aligned with the b8 bit of the current dividend, the lowest bit b0 of the original divisor is aligned with the b7 bit of the current dividend (such as the dark gray data of the current decrement in fig. 3), and the 3 bits of the original divisor left-shifted for the first time are taken as the highest three bits of the current decrement; next, judging that the unaligned digits (b 6-b 0, total 7 digits) of the current dividend are more than 3, continuing to perform left shift on the original divisor for the second time, because the unaligned highest digit except the highest digit of the current dividend is b6, moving the original divisor to the left by 5 digits as a whole, after the left shift for the second time, aligning the highest digit b2 of the original divisor with the b6 digits of the current dividend, aligning the next highest digit b1 of the original divisor with the b5 digits of the current dividend, aligning the lowest digit b0 of the original divisor with the b4 digits of the current dividend (such as middle gray data of the current decrement in fig. 3), and taking the 3 digits of the original divisor subjected to the left shift for the second time as the 4th to 6 digits of the current decrement; next, judging that the unaligned digits (b 3-b 0, 4 digits in total) of the current dividend are still larger than 3, continuing to perform left shift on the original divisor for the third time, because the unaligned highest digit except the highest digit of the current dividend is b3, moving the original divisor 1 digit to the left overall, after the left shift for the third time, aligning the highest digit b2 of the original divisor with the b3 digit of the current dividend, aligning the next highest digit b1 of the original divisor with the b2 digit of the current dividend, aligning the lowest digit b0 of the original divisor with the b1 digit of the current dividend (such as light gray data of the current decrement in fig. 3), and taking the 3 digits of the original divisor subjected to the third left shift as the 7 th to 9 th digits of the current decrement; next, if the number of unaligned bits (b0, 1 bit in total) of the current dividend is judged to be less than 3, the number of unaligned bits in the current subtrahend with the current dividend is set to zero (e.g., white data of the current subtrahend in fig. 3), i.e., the 10 th bit of the current subtrahend is set to zero. The resulting current decrement is 1011011010, and the difference between the current dividend and the current decrement is 1000000011.

The following describes a specific flow of the modulo operation according to the embodiment of the present application with reference to fig. 4. Referring to fig. 4, fig. 4 is a diagram illustrating an exemplary modulo operation according to an embodiment of the present disclosure. As shown in fig. 4, fig. 4 illustrates the process of dividing dividend 2047 by divisor 5 to obtain a remainder. The original dividend is 2047, which corresponds to a binary number of 11111111111, and has a total bit width of n-11 bits (bit), the least significant bit being denoted b0 and the most significant bit being denoted b 10. The original divisor is 5, the corresponding binary number is 101, the total bit width is m ═ 3 bits (bit), the lowest bit is denoted by b0, and the highest bit is denoted by b 2. The current reduced number of the original divisor after being shifted (specifically, the first type of left shift alignment processing that the original divisor is aligned with the original dividend 11111111111) is 10110110100, the first iteration is to subtract the original dividend 11111111111 from the current reduced number 10110110100 to obtain the current dividend as 1001001011, and since 1001001011 is greater than 101, the next shift processing and the next iteration are continuously executed; the current divisor of the original divisor after shifting (specifically, the current divisor is aligned with the current dividend 1001001011 obtained in the last iteration through the second type of left shift alignment processing) is 101101101, the current dividend 1001001011 obtained in the last iteration is subtracted from the current divisor 101101101 in the second iteration to obtain a new current dividend 11011110, and since 11011110 is greater than 101, the next shifting processing and the next iteration are continuously executed; the current divisor of the original divisor after shifting (specifically, the original divisor is aligned with the current dividend 11011110 obtained in the last iteration through the first left shift alignment processing) is 10110100, the third iteration is to subtract the current dividend 11011110 obtained in the last iteration from the current divisor 10110100 to obtain a new current dividend 101010, and because 101010 is greater than 101, the next shift processing and the next iteration are continuously executed; the current divisor of the original divisor after shifting (specifically, the first type left shift alignment processing that the original divisor is aligned with the current dividend 101010 obtained in the last iteration) is 101000, the fourth iteration is to subtract the current dividend 101010 obtained in the last iteration from the current divisor 101000 to obtain 10, since 10 is less than 101, the shifting processing and the iteration are ended, and 10 (the corresponding decimal number is 2) is taken as the remainder of dividing the original dividend by the original divisor.

As can be seen from fig. 4, compared with the existing scheme that the remainder needs to be iterated 409 times to obtain the final remainder, the scheme of fig. 4 only needs 4 iteration loops, so that the iteration number of the subtraction operation of the subtractor module is greatly reduced, and the time required by the modulo operation is further shortened.

Optionally, after taking the difference between the current dividend and the current divisor as the remainder of dividing the original dividend by the original divisor, or taking the current dividend as the remainder of dividing the original dividend by the original divisor, the controller 11 calculates the current quotient corresponding to the current divisor obtained each time according to the number of times of left-shift alignment processing in the current divisor obtained each time and the displacement amount of the left-shift alignment processing each time;

the controller 11 uses the sum of the current quotients corresponding to the current decrements obtained each time as the quotient of the original dividend divided by the original divisor.

In the embodiment of the present application, the number of times of left shift alignment processing in each obtained current decrement refers to: each time the original divisor is shifted left by the number of times the original divisor is aligned. The shift amount per left shift alignment process refers to: each time the original divisor is left shifted by an aligned left shift number.

For example, if the number of times of left shift alignment processing in a current decrement obtained at a time is 3 and the displacement amount of each left shift alignment processing is 7, 4, 1, respectively, then the current quotient corresponding to the current decrement obtained at the time is 2⁷+2⁴+2¹＝146。

Optionally, the calculating, by the controller 11, a current quotient corresponding to the current decrement obtained each time according to the number of times of left shift alignment processing in the current decrement obtained each time and the displacement amount of each left shift alignment processing includes:

if the left shift alignment process is a first type of left shift alignment process, if the binary significant digit of the current decrement obtained at the current time is n and the total number of times of the first type of left shift alignment process is p, the controller 11 calculates a current quotient corresponding to the current decrement obtained at the current time according to the following formula:

and H is the current quotient corresponding to the current decrement obtained at the current time. Σ is the sign of the summation, n is the binary significand of the current divisor, m is the binary significand of the original divisor, and z is summed from 1 to p.

Specifically, as can be seen from fig. 2, if the binary significant digit of the current decrement obtained at the current time is n-11, the total number of times of performing the first-type left-shift alignment processing on the original divisor of the current decrement obtained at the current time is p-3, and the digit of the original divisor is m-3, then the current quotient H-2 corresponding to the current decrement obtained at the current time is 2⁸+2⁵+2²＝292。

if the left shift alignment process is a second type left shift alignment process, if the binary significant digit of the current decrement obtained at the current time is n and the total number of times of the second type left shift alignment process is u, the controller 11 calculates a current quotient corresponding to the current decrement obtained at the current time according to the following formula:

and H is the current quotient corresponding to the current decrement obtained at the current time. Σ is the sign of the summation, n is the binary significand of the current divisor, m is the binary significand of the original divisor, and z is summed from 1 to u.

Specifically, as can be seen from fig. 3, if the binary significant digit of the current decrement obtained at the current time is n-11, the total number of times of performing the second-type left-shift alignment processing on the original divisor of the current decrement obtained at the current time is u-3, and the digit m of the original divisor is 3, then the current quotient H-2 corresponding to the current decrement obtained at the current time is 2⁷+2⁴+2¹＝146。

The following describes a specific flow of quotient finding in the embodiment of the present application with reference to fig. 5. Referring to fig. 5, fig. 5 is an exemplary diagram of a quotient query according to an embodiment of the present disclosure. As shown in fig. 5, fig. 5 illustrates the process of calculating a quotient in the process of dividing dividend 2047 by divisor 5 to obtain a remainder. The original dividend is 2047, which corresponds to a binary number of 11111111111, and has a total bit width of n-11 bits (bit), the least significant bit being denoted b0 and the most significant bit being denoted b 10. The original divisor is 5, the corresponding binary number is 101, the total bit width is m ═ 3 bits (bit), the lowest bit is denoted by b0, and the highest bit is denoted by b 2. The current divisor after the original divisor is shifted (specifically, the first type of left shift alignment processing that the original divisor is aligned with the original dividend 11111111111) is 10110110100, in the process of obtaining the current divisor, the original divisor is shifted three times, the shift amounts are respectively 8, 5 and 2, and then the current quotient H corresponding to the current divisor obtained at the current time is obtained₁＝2⁸+2⁵+2²292. The first iteration is to subtract the original dividend 11111111111 from the current decrement 10110110100 to obtain the current dividend 1001001011, and since 1001001011 is greater than 101, the next shift processing and the next iteration are continued; the original divisor is shiftedThe current divisor after the bits (specifically, the original divisor is aligned with the current dividend 1001001011 obtained in the last iteration in the second type of left shift alignment process) is 101101101, and in the process of obtaining the current divisor, the original divisor is shifted three times, the shift amounts are 6, 3, and 0, respectively, and then the current quotient H corresponding to the current divisor obtained at the current time is H₂＝2⁶+2³+2⁰73. In the second iteration, the current dividend 1001001011 obtained in the last iteration is subtracted from the current subtraction number 101101101 to obtain a new current dividend of 11011110, and since 11011110 is greater than 101, the next shift processing and the next iteration are continuously executed; the current divisor after the original divisor is shifted (specifically, the original divisor is shifted to the left in the first class where the current dividend 11011110 obtained in the last iteration is aligned) is 10110100, and in the process of obtaining the current divisor, the original divisor is shifted twice, the shift amounts are 5 and 2 respectively, and then the current quotient H corresponding to the current divisor obtained at the current time is obtained₃＝2⁵+2²36. The third iteration is to subtract the current dividend 11011110 obtained from the last iteration from the current deduction 10110100 to obtain a new current dividend 101010, and because 101010 is larger than 101, the next shift processing and the next iteration are continuously executed; the current divisor after the original divisor is shifted (specifically, the original divisor is shifted once and shifted by 3 in the process of obtaining the current divisor, if the original divisor is shifted by one time, the current divisor H is the current quotient H corresponding to the current divisor obtained at this time if the shift amount is 3), is 101000 (specifically, the original divisor is left-shifted and aligned with the current dividend 101010 obtained at the last iteration)₄＝2³8. The fourth iteration is to subtract the current dividend 101010 from the current divisor 101000 obtained from the previous iteration to obtain 10, and since 10 is smaller than 101, the shift processing and the iteration are ended, and 10 (corresponding to a decimal number of 2) is used as the remainder of dividing the original dividend by the original divisor. The dividend 2047 is divided by the divisor 5 to obtain the quotient H ═ H₁+H₂+H₃+H₄292+73+36+8 409. In the existing scheme, the quotient is the iteration number, and the more the iteration number is, the more time is required for obtaining the quotient. The embodiment of the application is based on each timeIn the iteration, the quotient is calculated according to the number of times of left shift alignment processing in the current deduction and the displacement of each left shift alignment processing, and because the iteration number is greatly reduced, the calculation amount for obtaining the quotient is also reduced, and the time for calculating the quotient can be shortened.

Optionally, before the controller 11 compares whether the current dividend is greater than or equal to 2 times the original divisor, the controller 11 calculates a ratio of the original dividend to the original divisor, and in case that the ratio of the original dividend to the original divisor is greater than a first threshold, the controller 11 performs the step of comparing whether the current dividend is greater than or equal to 2 times the original divisor.

Optionally, in a case that the ratio of the original dividend to the original divisor is smaller than the first threshold, the controller 11 calculates a remainder of dividing the original dividend by the original divisor as follows:

performing difference value calculation, and subtracting the original divisor from the current dividend to obtain a difference value; the current dividend is the original dividend or a difference value obtained by calculating the previous difference value;

judging whether the difference value is smaller than the original divisor;

if the difference value is larger than or equal to the current dividend value, taking the difference value as a new current dividend value, and continuing to execute the calculation of the difference value;

if so, the difference value is taken as the remainder of dividing the original dividend by the original divisor.

In the embodiment of the present application, the first threshold may be preset, for example, the first threshold may be set to 4. Under the condition that the ratio of the original dividend to the original divisor is smaller than a first threshold value, the remainder can be obtained only by iteration for a plurality of times without shifting; in the case that the ratio of the original dividend to the original divisor is greater than the first threshold, the remainder can be quickly found by the shift processing and the subtraction iteration. The embodiment of the application can improve the intelligence of the modular arithmetic.

Referring to fig. 6, fig. 6 is a schematic flow chart of a modulo operation processing method provided in the present application, and as shown in fig. 6, the method includes the following steps.

601, comparing whether the current dividend is more than or equal to 2 times of the original divisor, wherein the original divisor and the current dividend are binary numbers, and the current dividend is the original dividend or the dividend obtained by the last subtraction operation;

602, if the current dividend is greater than or equal to 2 times of the original divisor, inputting the original divisor into the shift register module for shift processing to obtain a current decrement which is N times of the original divisor and less than the current dividend, wherein N is an integer greater than or equal to 2;

603, performing a current subtraction operation, wherein the current subtraction operation is used for calculating a difference value between the current dividend and the current decrement, and storing the difference value between the current dividend and the current decrement in a cache;

604, if the difference between the current dividend and the current divisor is less than the original divisor, the difference between the current dividend and the current divisor is used as the remainder of the original dividend divided by the original divisor.

Optionally, as shown in fig. 7, after step 603 is performed, the following step 605 may also be performed.

605 if the difference between the current dividend and the current decrement is greater than the original divisor, the difference between the current dividend and the current decrement is used as the new current dividend, and the above step 601 is executed.

Optionally, as shown in fig. 8, after step 601 is executed, the following step 606 or step 607 may also be executed.

606, if the current dividend is less than 2 times of the original divisor and the current dividend is greater than or equal to the original divisor, taking the difference between the current dividend and the original divisor as the remainder of dividing the original dividend by the original divisor;

607, if the current dividend is less than 2 times the original divisor and the current dividend is less than the original divisor, the current dividend is used as the remainder of the original dividend divided by the original divisor.

Optionally, in step 602, inputting the original divisor into the shift register module for shift processing, to obtain a current divisor that is N times the original divisor and smaller than the current dividend, which may include the following steps:

(11) comparing the size of the highest m-bit binary number of the current dividend with the size of the original divisor, wherein the binary significant digit of the original divisor is m, and the binary significant digit of the current dividend is n; m and n are positive integers;

(12) if the highest m-bit binary number of the current dividend is greater than or equal to the original divisor, inputting the original divisor into a shift register module to perform p times of first-class left shift alignment processing to obtain a current divisor; each time the first-class left shift alignment process aligns the highest bit of the original divisor with the highest bit of the current dividend which is not aligned;

(13) if the unaligned digit of the current dividend is greater than or equal to m, continuing to execute the first-class left shift alignment processing; if the unaligned digit of the current dividend is less than m, setting the unaligned digit of the current dividend and the current dividend in the current deduction to zero;

if n is a non-integral multiple of m, n is p × m + s; p and s are positive integers;

if n is an integral multiple of m, n is t m; t is a positive integer.

(21) comparing the size of the highest m-bit binary number of the current dividend with the size of the original divisor, wherein the binary significant digit of the original divisor is m, and the binary significant digit of the current dividend is n; m and n are positive integers;

(22) if the highest m-bit binary number of the current dividend is smaller than the original divisor, the original divisor is input into a shift register module to carry out u times of second-class left shift alignment processing to obtain the current divisor; each time the second type of left shift alignment processing aligns the highest bit of the original divisor with the unaligned highest bits of the current dividend except the highest bit;

(23) if the unaligned digit except the highest digit of the current dividend is greater than or equal to m, continuing to execute the second type of left shift alignment processing; if the unaligned digits of the current dividend except the highest digit are less than m, setting the unaligned digits of the current dividend and the current dividend in the current deduction to zero;

if n-1 is a non-integral multiple of m, n-1 is u m + v, and u and v are positive integers;

if n-1 is a non-integral multiple of m, n-1 is x m; x is a positive integer.

Optionally, as shown in fig. 9, after step 604, step 606, or step 607 is executed, the following steps may also be executed:

608, calculating a current quotient corresponding to the current decrement obtained each time according to the number of left shift alignment processing in the current decrement obtained each time and the displacement amount of each left shift alignment processing;

609, taking the sum of the current quotients corresponding to the current deductions obtained each time as the quotient of the original dividend divided by the original divisor.

Optionally, step 608 may include the steps of:

if the left shift alignment processing is the second type left shift alignment processing, the binary significant digit of the current decrement obtained at the current time is n, the total times of the second type left shift alignment processing is u, and the current quotient corresponding to the current decrement obtained at the current time is calculated according to the following formula:

Optionally, as shown in fig. 10, before performing step 601, the following steps may also be performed:

610, calculating the ratio of the original dividend to the original divisor;

611, the original dividend is compared with the original divisor for whether the ratio is larger than the first threshold, if yes, step 601 is executed.

Optionally, after the step 610 is executed, the following steps may also be executed:

if the ratio of the original dividend to the original divisor is smaller than the first threshold, calculating the remainder of the original dividend divided by the original divisor as follows:

(31) performing difference value calculation, and subtracting the original divisor from the current dividend to obtain a difference value; the current dividend is the original dividend or the difference obtained by the previous difference calculation;

(32) judging whether the difference value is smaller than the original divisor;

(33) if the difference value is larger than or equal to the current dividend value, taking the difference value as a new current dividend value, and continuing to execute the calculation of the difference value;

(34) if so, the difference value is taken as the remainder of dividing the original dividend by the original divisor.

The main body for executing each step in fig. 6 to fig. 10 may be the arithmetic circuit shown in fig. 1, and specifically may be a controller, a shift register module or a subtractor module in the arithmetic circuit.

The specific implementation of the method shown in fig. 6 to 10 can be referred to the embodiment of the operation circuit in fig. 1 to 5, and is not described herein again.

According to the modular arithmetic processing method, modular arithmetic can be achieved through the subtracter module and the shift register module, and the current subtraction number which is N times of the original divisor can be found out through one-time iteration of the shift register module as far as possible, so that the iteration times of the subtraction operation of the subtracter module are reduced, and the time required by the modular arithmetic is shortened.

Referring to fig. 11, fig. 11 is a schematic structural diagram of a modulo operation processing apparatus according to an embodiment of the present application, and as shown in fig. 11, the modulo operation processing apparatus includes a comparing unit 1101, a shift processing unit 1102, a subtraction unit 1103, and a remainder unit 1104, where:

a comparing unit 1101, configured to compare whether a current dividend is greater than or equal to 2 times of an original divisor, where the original divisor and the current dividend are both binary numbers, and the current dividend is the original dividend or a dividend obtained by a previous subtraction operation;

a shift processing unit 1102, configured to, when the current dividend is greater than or equal to 2 times of the original divisor, input the original divisor into a shift register module to perform shift processing, so as to obtain a current divisor that is N times of the original divisor and smaller than the current dividend, where N is an integer greater than or equal to 2;

a subtraction unit 1103, configured to perform a current subtraction operation, where the current subtraction operation is used to calculate a difference between the current dividend and the current decrement, and store the difference between the current dividend and the current decrement in a buffer;

a complementation unit 1104, configured to, in a case that a difference between the current dividend and the current divisor is smaller than the original divisor, take the difference between the current dividend and the current divisor as a remainder of dividing the original dividend by the original divisor.

The modulo arithmetic processing apparatus shown in fig. 11 can be implemented by referring to the method embodiments shown in fig. 6 to fig. 10, and repeated descriptions are omitted.

The modulo operation processing device of the embodiment of the application can realize modulo operation through the subtracter module and the shift register module, and can dig out the current decimal fraction which is N times of the original divisor as much as possible through one-time iteration of the shift register module, thereby reducing the iteration times of the subtraction operation of the subtracter module, and further shortening the time required by the modulo operation.

Referring to fig. 12, fig. 12 is a schematic structural diagram of another modulo operation processing apparatus according to an embodiment of the present application, and as shown in fig. 12, the modulo operation processing apparatus 1200 includes a processor 1201 and a memory 1202, and the processor 1201 and the memory 1202 may be connected to each other through a communication bus 1203. The communication bus 1203 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus 1203 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 12, but this is not intended to represent only one bus or type of bus. The memory 1202 is used for storing a computer program comprising program instructions, which the processor 1201 is configured to invoke, the program comprising instructions for performing the method shown in fig. 2.

The processor 1201 may be a general purpose Central Processing Unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to control the execution of programs according to the above schemes. The processor 1201 may be the controller in fig. 1.

The Memory 1202 may be, but is not limited to, a Read-Only Memory (ROM) or other type of static storage device that can store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that can store information and instructions, an Electrically Erasable Programmable Read-Only Memory (EEPROM), a compact disc Read-Only Memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be self-contained and coupled to the processor via a bus. The memory may also be integral to the processor.

Embodiments of the present application also provide a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any one of the modulo operation processing methods described in the above method embodiments.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: various media capable of storing program codes, such as a usb disk, a read-only memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and the like.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash memory disks, read-only memory, random access memory, magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An arithmetic circuit comprising a controller, a buffer, a subtractor module, and a shift register module, wherein:

2. The operational circuit of claim 1,

in a case where the current dividend is less than 2 times the original divisor and the current dividend is greater than or equal to the original divisor, the controller sets a difference value of the current dividend and the original divisor as a remainder of dividing the original dividend by the original divisor;

in a case where the current dividend is less than 2 times the original divisor and the current dividend is less than the original divisor, the controller divides the current dividend by the original divisor as a remainder of the original dividend.

3. The operational circuit of claim 2,

and in the case that the difference value between the current dividend and the current decrement is greater than the original divisor, the controller takes the difference value between the current dividend and the current decrement as a new current dividend, and performs the step of comparing whether the current dividend is greater than or equal to 2 times the original divisor.

4. The operational circuit of claim 2 or 3, wherein the controller inputs an original divisor into the shift register module, and the shift register module shifts the original divisor and outputs a current divisor that is N times the original divisor and smaller than the current dividend to the subtractor module, comprising:

the controller compares the size of the highest m-bit binary number of the current dividend with the size of the original divisor, wherein the binary significant digit of the original divisor is m, and the binary significant digit of the current dividend is n; m and n are positive integers;

when the highest m-bit binary number of the current dividend is greater than or equal to the original divisor, the controller inputs the original divisor into the shift register module, the shift register module performs p times of first-class left shift alignment processing on the original divisor to obtain a current deduction, and the current deduction is input into the subtractor module; each time the first-class left-shift alignment process aligns the highest bit of the original divisor with the highest bit of the current dividend which is not aligned;

when the unaligned digit number of the current dividend is greater than or equal to m, the shift register module continues to execute the first type left shift alignment processing;

the shift register module zeroes a number of unaligned bits of the current dividend in the current decrement that is less than m.

5. The operational circuit of claim 4,

when the highest m-bit binary number of the current dividend is smaller than the original divisor, the controller inputs the original divisor into the shift register module, the shift register module performs u times of second-class left shift alignment processing on the original divisor to obtain a current deduction, and the current deduction is input into the subtractor module; each time the second type of left shift alignment processing aligns the highest bit of the original divisor with the unaligned highest bits of the current dividend except the highest bit;

in the case that the unaligned digit except the highest digit of the current dividend is greater than or equal to m, the shift register module continues to execute the second type of left shift alignment processing;

the shift register module zeroes unaligned bits of the current divisor other than a most significant bit of the current dividend.

6. The operational circuit of claim 4 or 5,

after the difference value between the current dividend and the current divisor is used as the remainder of dividing the original dividend by the original divisor, or the current dividend is used as the remainder of dividing the original dividend by the original divisor, the controller calculates the current quotient corresponding to the current divisor obtained each time according to the number of left-shift alignment processing in the current divisor obtained each time and the displacement amount of the left-shift alignment processing each time;

and the controller takes the sum of the current quotients corresponding to the current deductions obtained each time as the quotient of the original dividend divided by the original divisor.

7. The arithmetic circuit of claim 6, wherein the controller calculates the current quotient corresponding to each of the obtained current decrements based on the number of left shift register processes in each of the obtained current decrements and the amount of shift for each of the left shift register processes, comprising:

under the condition that the left shift alignment processing is first-class left shift alignment processing, if the binary significant digit of the current decrement obtained at the current time is n and the total number of times of the first-class left shift alignment processing is p, the controller calculates the current quotient corresponding to the current decrement obtained at the current time according to the following formula:

under the condition that the left shift alignment processing is second-class left shift alignment processing, if the binary significant digit of the current decrement obtained at the current time is n and the total number of times of the second-class left shift alignment processing is u, the controller calculates the current quotient corresponding to the current decrement obtained at the current time according to the following formula:

8. A modular arithmetic processing method is characterized by comprising the following steps:

9. A modulo operation processing apparatus comprising a processor and a memory, the memory being for storing a computer program comprising program instructions, the processor being configured to invoke the program instructions to perform the modulo operation processing method of claim 8.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program comprising program instructions that, when executed by a processor, cause the processor to execute the modulo operation processing method according to claim 8.