GB2261991A - Noise supression in memory device - Google Patents
Noise supression in memory device Download PDFInfo
- Publication number
- GB2261991A GB2261991A GB9224770A GB9224770A GB2261991A GB 2261991 A GB2261991 A GB 2261991A GB 9224770 A GB9224770 A GB 9224770A GB 9224770 A GB9224770 A GB 9224770A GB 2261991 A GB2261991 A GB 2261991A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal line
- wiring
- memory device
- signal lines
- noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B15/00—Suppression or limitation of noise or interference
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
This invention relates to an arrangement method of signal lines o1, o2, o3, o4 of a peripheral circuit of a memory array block within a chip in a semiconductor memory device wherein shield wirings S1, S2, S3 are inserted between signal lines, so that a noise transmission path caused by coupling capacitance between adjacent signal lines is cut off, and therefore, the noise generated at each signal line of the peripheral circuit of the memory array block is suppressed. Shield wiring may be installed also between first and second signal line groups. Thus, malfunction of the chip may be prevented and the reliability of the semiconductor memory device can be improved. <IMAGE>
Description
NOISE SUPPRESSION IN MEMORY DEVICE
The present invention relates to semiconductor memory devices.
A peripheral circuit of a memory array block in a semiconductor memory device has a number of signal lines, such as a data bus and a control bus conveying a data signal and a control signal respectively, with the result that mutual interference between signal lines has been experienced. For example, in the case that a signal with an irregular voltage level such as a
TTL (Transistor-Transistor Logic) signal level is applied to a peripheral circuit, the interference can be much too serious for regular operation of the peripheral circuit, and is one of the factors of degradation of reliability in a highly integrated semiconductor memory device.
Figure 1 of the accompanying diagrammatic drawings is a diagram showing a conventional wiring arrangement method of signal lines. The wiring arrangement method of the signal lines shown in Figure 1 is well known in the art, and signal lines constructed with a metal line or polysilicon, etc. are arranged in parallel, crossed or stacked with one another. However, since each signal line is adjacently arranged without shielding, noise occurs at any signal line due to specific resistance and coupling capacitance of the signal line. The noise has an influence on an adjacent signal line, which may thereby cause malfunction of a chip.For example, when any signal line performs a swing operation from logic "high" to "low", or from logic "low" to "high", since a signal line adjacent thereto does not maintain a previous state, a phenomenon such as a glitch phenomenon generating a momentary pulse wave may occur. and the chip is liable to malfunction.
In Figure 2 of the accompanying diagrammatic drawings Figure 2A is a circuit diagram showing a signal line model of Figure 1, Figure 2B is a partial, more detailed diagram of Figure 2A, and Figure 2C is an equivalent circuit diagram of Figure 2B. The influence of the noise on an adjacent signal line in the construction of Figure 1 will be expressed with reference to
Figures 2B and 2C. Initial conditions are as follows:
1.If it is assumed that the thickness d of a dielectric between the substrate and wiring A is the same as the thickness d' of a dielectric between the substrate and wiring B, the dielectric under the wiring A is the same substance as the dielectric under the wiring B; the width b of the wiring A is the same as the width b' of the wiring B; and the length e of the wiring A is the same as the length e' of the wiring B, then it can be appreciated that the capacitance CA between the wiring A and the substrate and the capacitance CB between the wiring B and the substrate are the same as each other, that is
CA=CB;
2. If it is assumed that initial voltage conditions of the wirings A and the wiring B are the same as each other, then it can be appreciated that the voltage VA of the wiring A and the voltage of the VB of the wiring B are the same as each other, that is VA=VB;
3.It is assumed that the thickness a of the wiring A and the thickness a' of the wiring B are the same as each other, and there is a given interval 1 between the wiring A and the wiring B.
Under the above initial conditions, i.e. CA=CB, VA=VB and a=a', if a noise AVA is generated from the wiring A, the noise AVA has an influence on the wiring B to cause a noise avB. To calculate the noise AVB, the following equation can be introduced. That is,
V = QIC where V, Q and C are voltage charge and capacitance respectively. Then the following equation can readily be obtained.
AVB = CAB#(VA+AVA-VB)/(CAB+CB) And if the above initial conditions are applied,
AVB = CAB#AVA/(CAB+CB) Consequently, the noise AVB has an effect on the wiring B. The noise
AVB is generated whenever a given signal line performs a swing operation, and in a highly integrated semiconductor memory device having a small transistor size, the noise can be much too severe.
Preferred embodiments of the present invention aim to provide an arrangement method of signal lines for minimizing the generation of noise.
It is another aim to provide a semiconductor memory device capable of obtaining a stable circuit operation by suppressing noise between signal lines.
According to one aspect of the present invention, there is provided a method of arranging signal lines in a semiconductor memory device, comprising the step of inserting shield wiring between first and second signal lines adjacent to each other, to protect said first or second signal line from the influence of noise generated from a transition operation of said second or first signal line.
Preferably, a voltage level of said shield wiring is fixed to a constant voltage level, such as a power supply voltage level or a ground voltage level.
According to another aspect of the present invention, there is provided a semiconductor memory device having a memory array block and a peripheral circuit to provide signals for enabling operation of said memory array block, wherein shield wirings are inserted between a number of signal lines in said peripheral circuit, thereby to suppress noise and prevent malfunction of a respective chip when a given signal line performs a transition operation.
Preferably, a voltage level of said shield wiring is maintained at a constant voltage level.
According to a further aspect of the present invention, there is provided a method of arranging signal lines in a semiconductor memory device, comprising the step of inserting shield wiring between first and second signal line groups, to protect said first or second signal line group from the influence of noise generated from a transition operation of said second or first signal line group.
The invention extends to a semiconductor memory device having signal lines arranged by a method according to any of the preceding aspects of the invention.
For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 3 to 6 of the accompanying diagrammatic drawings, in which:
Figure 3 is a diagram showing a wiring arrangement method according to one example of a preferred embodiment of the present invention;
Figure 4A is a circuit diagram showing the signal line modelling of
Figure 3;
Figure 4B is a partial, more detailed diagram of Figure 4A; Figure 4C is an equivalent circuit diagram of Figure 4B;
Figure 5 is a diagram showing a wiring arrangement method according to another example of a preferred embodiment of the present invention; and
Figure 6 is a circuit diagram showing the signal line modelling of
Figure 5.
In the illustrated embodiments of the invention, a shield wiring is inserted between given first and second signal lines (or groups) included in a memory array block and/or a peripheral circuit of a memory array block in a chip.
Referring now to Figure 3, hatched blocks S1 to S3 are shield wirings.
The shield wiring is installed between signal lines in a peripheral circuit of a memory array block in a chip. Therefore, even if a signal line +1 performs a swing (transition) operation, the swing operation has little effect on a signal line #2 because of the shield wiring S1. Similarly, in the case of signal lines or or #4, the same effect is obtained. The influence of noise on an adjacent signal line in the construction of Figure 3 will be described with reference to
Figures 43 and 4C. It is assumed that initial conditions are as follows.
1. If it is assumed that the thicknesses d, d' and d" of respective dielectrics between the substrate and the wirings X, Y and Z are the same as each another, the dielectrics under the wirings X, Y and Z are of the same substance; the widths b, b', and b" of the wirings X, Y and Z are the same as each another; and the lengths e, e', and e" of the wirings X, Y and Z are the same as each another, then it can be appreciated that the capacitances Cx,
Cy and Cz between the wirings X, Y and Z and the substrate are the same as each another, that is Cx=Cy=Cz;
2.If it is assumed that the thicknesses a, a' and a" of wirings X, Y and Z are the same as each another; the lengths e, e', and e" of the wirings
X, Y, and Z are the same as each another; and the interval 1 between the wiring X and the wiring Y is the same as the interval 1' between the wiring
Y and the wiring Z, then it can be appreciated that the capacitance Cxy between the wiring X and the capacitance Cyz between the wiring Y and the wiring Z are the same as each other, that is Cxy=Cyz 3.If it is assumed that initial voltage conditions of the wirings X, Y and Z are the same as each another, then it can be appreciated that the voltages Vx, Vy and Vz of the wirings X, Y and Z are the same as each another, that is Vx=Vy=Vz;
Under the above initial conditions, if the wiring X generates a noise
AVx, the noise AVx has an effect on the wiring Z to cause a noise tVz. The value of the noise av, will be compared with that of the noise AVB of the conventional method. Moreover, the noise of AVx has an influence on the wiring Y to cause a noise AVy. By calculation, the noise AVy is obtained as the following equation.
AVy = CXY (VX + AV#Vy)/(C# + Cy + Cy#.
If the above initial conditions are applied, #Vy = C###AVx/(2Cxy+Cy).
If all of the initial conditions of the conventional method and the illustrated embodiments of the invention are the same as each other, we can conclude that the noise AVy is less than the noise AVB by inserting the wiring Y.
Sequentially, the noise AVy has influence on the wiring Z. In this case, the following equation is obtained.
AVz CYZ Cyz = (Vy+AVy-V/(Cyz+C0.
If the above initial conditions are also applied,
AVz = CXZ-AVYI(CXZ+CZ)-
Recall that AVy = Cxy AVX/(2Cxy+Cy), AVz = {CXZ/CXZ+CZ)}. (C##AVx/(2Cxz+Cz) = (CXZ.#Vx)/(CXZ+CZ).{CXZ/(2CXZ+CZ).
The term {CXZ/(2CXZ+CZ)} is less than 1, that is {CXZ/(2CXZ+CZ)} ( 1.
If all of the initial conditions of the conventional method and the present invention are the same to each other, it can be readily appreciated that AVz (AVB Consequently, even if the voltage Vz of the wiring Z is influenced by the noise AVx, the value of Vz+AVz becomes small. That is, there is an effect of the noise AVy by the wiring Y inserted between the wiring X and wiring Z, and in the case that the wiring Y is connected to, for example, a power voltage line, since coupling efficiency becomes lower, the noise transmitted to wirings adjacent to each other can be suppressed.
Referring to Figure 5, a hatched block S11 is a shield wiring. In the construction of Figure 3, the shield wiring is installed between the signal lines included in the peripheral circuit of the memory array block. However, in the construction of Figure 5, the shield wiring is installed between first and second signal line groups included in the memory array block or/and the peripheral circuit of the memory array block. In the memory array block or in the peripheral circuit of the memory array block, there are a row address signal line group, a column address signal line group, a signal line group for decoding a row address, a signal line group for decoding a column address, and the like.In the case that the above-mentioned signal line groups are adjacent to each other in the memory array block, constructed to a design rule of a sub-micron range, if the row address signal line group carries out a transition operation then, for example, the column address signal line group adjacent thereto may be influenced by the transition operation. At this time, the effect of transmission noise can be simply prevented by the shield wiring Sll. Thus, the shield wiring S11 may be installed in the memory array block, in the peripheral circuit of the memory array block, or in the memory array block and the peripheral circuit, respectively.Moreover, the shield wiring of Figure 2 or 5 may be constructed with a metal line or polysilicon, etc., and a voltage level thereof can be fixed by the use of any wiring maintaining a floating state, a power voltage line or a ground voltage line.
When the shield wiring of Figure 3 inserted between individual signal lines in a peripheral circuit of a memory array block is installed in the memory array block, the degree of integration should be considered.
As described above, since the shield wiring cuts off a noise transmission path caused by the coupling capacitance between adjacent signal lines, noise generated at each signal line of the peripheral circuit of the memory array block in the chip is suppressed. Moreover, since the noise path between the signal line groups adjacent to each other is cut off, malfunction of the chip is prevented and the reliability of the semiconductor memory device can be improved.
While preferred embodiments of the present invention have been particularly shown and described, it will be understood by those skilled in the art that foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
Claims (7)
1. A method of arranging signal lines in a semiconductor memory device, comprising the step of inserting shield wiring between first and second signal lines adjacent to each other, to protect said first or second signal line from the influence of noise generated from a transition operation of said second or first signal line.
2. A method as claimed in claim 1, wherein a voltage level of said shield wiring is fixed to a constant voltage level, such as a power supply voltage level or a ground voltage level.
3. A semiconductor memory device having a memory array block and a peripheral circuit to provide signals for enabling operation of said memory array block, wherein shield wirings are inserted between a number of signal lines in said peripheral circuit, thereby to suppress noise and prevent malfunction of a respective chip when a given signal line performs a transition operation.
4. A semiconductor memory device as claimed in claim 3, wherein a voltage level of said shield wiring is maintained at a constant voltage level.
5. A method of arranging signal lines in a semiconductor memory device, comprising the step of inserting shield wiring between first and second signal line groups, to protect said first or second signal line group from the influence of noise generated from a transition operation of said second or first signal line group.
6. A method of arranging signal lines in a semiconductor memory device, the method being substantially as hereinbefore described with reference to
Figures 3 to 6 of the accompanying drawings.
7. A semiconductor memory device having signal lines arranged by a method according to any of claims 1, 2, 5 and 6.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910021539A KR940008132B1 (en) | 1991-11-28 | 1991-11-28 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9224770D0 GB9224770D0 (en) | 1993-01-13 |
| GB2261991A true GB2261991A (en) | 1993-06-02 |
Family
ID=19323732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9224770A Withdrawn GB2261991A (en) | 1991-11-28 | 1992-11-26 | Noise supression in memory device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH05226340A (en) |
| KR (1) | KR940008132B1 (en) |
| DE (1) | DE4235177A1 (en) |
| FR (1) | FR2690026A1 (en) |
| GB (1) | GB2261991A (en) |
| IT (1) | IT1256448B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2286286A (en) * | 1993-12-31 | 1995-08-09 | Hyundai Electronics Ind | Semiconductor device having shield conduction lines |
| US6510545B1 (en) * | 2000-01-19 | 2003-01-21 | Sun Microsystems, Inc. | Automated shielding algorithm for dynamic circuits |
| US8085598B2 (en) | 2006-02-03 | 2011-12-27 | Renesas Electronics Corporation | Nonvolatile semiconductor memory device |
| US8286118B2 (en) | 2002-07-29 | 2012-10-09 | Synopsys, Inc. | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices |
| US8386979B2 (en) | 2002-07-29 | 2013-02-26 | Synopsys, Inc. | Method and apparatus to design an interconnection device in a multi-layer shielding mesh |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0650194B1 (en) * | 1993-10-21 | 1999-11-10 | Advanced Micro Devices, Inc. | High density dynamic bus |
| US5966317A (en) * | 1999-02-10 | 1999-10-12 | Lucent Technologies Inc. | Shielded bitlines for static RAMs |
| JP3987847B2 (en) | 2003-10-17 | 2007-10-10 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device equipped with MIM structure resistor |
| JP4939804B2 (en) | 2005-12-21 | 2012-05-30 | 三星電子株式会社 | Nonvolatile semiconductor memory device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2134708A (en) * | 1983-01-18 | 1984-08-15 | Western Electric Co | Integrated circuits |
| EP0353426A2 (en) * | 1988-06-10 | 1990-02-07 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device comprising conductive layers |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60254654A (en) * | 1984-05-30 | 1985-12-16 | Nec Corp | Semiconductor ic |
| JPH0235771A (en) * | 1988-07-26 | 1990-02-06 | Nec Corp | Semiconductor storage device |
| JPH0265238A (en) * | 1988-08-31 | 1990-03-05 | Seiko Epson Corp | Semiconductor integrated device |
-
1991
- 1991-11-28 KR KR1019910021539A patent/KR940008132B1/en not_active IP Right Cessation
-
1992
- 1992-10-07 FR FR9211892A patent/FR2690026A1/en active Pending
- 1992-10-19 DE DE4235177A patent/DE4235177A1/en not_active Withdrawn
- 1992-11-25 IT ITMI922697A patent/IT1256448B/en active IP Right Grant
- 1992-11-26 GB GB9224770A patent/GB2261991A/en not_active Withdrawn
- 1992-11-27 JP JP4318074A patent/JPH05226340A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2134708A (en) * | 1983-01-18 | 1984-08-15 | Western Electric Co | Integrated circuits |
| EP0353426A2 (en) * | 1988-06-10 | 1990-02-07 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device comprising conductive layers |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2286286A (en) * | 1993-12-31 | 1995-08-09 | Hyundai Electronics Ind | Semiconductor device having shield conduction lines |
| GB2286286B (en) * | 1993-12-31 | 1998-05-27 | Hyundai Electronics Ind | Improvements in or relating to the fabrication of semiconductor devices |
| US6510545B1 (en) * | 2000-01-19 | 2003-01-21 | Sun Microsystems, Inc. | Automated shielding algorithm for dynamic circuits |
| US8286118B2 (en) | 2002-07-29 | 2012-10-09 | Synopsys, Inc. | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices |
| US8386979B2 (en) | 2002-07-29 | 2013-02-26 | Synopsys, Inc. | Method and apparatus to design an interconnection device in a multi-layer shielding mesh |
| US8701068B2 (en) | 2002-07-29 | 2014-04-15 | Synopsys, Inc. | Interconnection device in a multi-layer shielding mesh |
| US8881086B2 (en) | 2002-07-29 | 2014-11-04 | Synopsys, Inc. | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices |
| US8085598B2 (en) | 2006-02-03 | 2011-12-27 | Renesas Electronics Corporation | Nonvolatile semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4235177A1 (en) | 1993-06-03 |
| ITMI922697A1 (en) | 1994-05-25 |
| ITMI922697A0 (en) | 1992-11-25 |
| KR930010974A (en) | 1993-06-23 |
| JPH05226340A (en) | 1993-09-03 |
| FR2690026A1 (en) | 1993-10-15 |
| GB9224770D0 (en) | 1993-01-13 |
| IT1256448B (en) | 1995-12-05 |
| KR940008132B1 (en) | 1994-09-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |