GB2260629A

GB2260629A - A segment descriptor cache for a microprocessor

Info

Publication number: GB2260629A
Application number: GB9216731A
Authority: GB
Inventors: Gary N Hammond; Pradeep Dubey
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 1991-10-16
Filing date: 1992-08-06
Publication date: 1993-04-21
Anticipated expiration: 2012-08-06
Also published as: FR2683061B1; JPH05210593A; GB9216731D0; FR2683061A1; DE4234194A1; GB2260629B

Abstract

An improved memory segmentation system in a microprocessor, for generating a segment descriptor based on a segment selector, comprises an associative descriptor cache 570 to retain previously fetched, unscrambled, and tested descriptors for subsequent access by the same selectors. If on a memory access the descriptor is not found in the descriptor cache, the selector 501 is used to fetch a scrambled, raw descriptor from memory 530. The scrambled descriptor is then unscrambled at 550 before loading into a segment register 560. The same unscrambled descriptor is also used to update the descriptor cache 570 such that it may be found in the future. The descriptor unscrambling is necessitated by provision of backward compatibility with prior processor architectures. <IMAGE>

Description

-% ') 1 3 5 n - Z_ J A SEGENT DESCRIPTOR CACHE FOR A MICROPROCESSOR

DACKGRO NI? QE THE INVENTIQ14 The present invention relates to memory management systems for computers and more specifically, to memory segmentation systems for microprocessors with increased data access speed and efficiency.

2. ART 13ACKGRQUND:

Memory management is a hardware mechanism which lets operating systems create simplified environments for running programs such that when several programs are running at the same time, they may each be given an independent address space to avoid interference with each other. Memory management typically consists of segmentation and paging. Segmentation is used to give each program several independent, protected address spaces ("segments"). Paging is used to support an environment where large address spaces are simulated using a small amount of random access memory ("RAM") and some disk storage. System designers may choose to use either or both of these mechanisms. When several programs are running at the same time, either mechanism can be used to protect programs against interference from other programs.

Segmentation allows memory to be completely unstructured and simple, like the memory model of a simple 8-bit processor. or highly structured with address translation and protection. Each segment is an independent, protected address space. Access to seoments is controlled by data which describes its size, the privilege level required to access it, the kinds of memory references which can be made to it (instruction fetch, stack push or pop, read operation, write operation, etc.), and whether it is present in memory.

Reference is now made to Fig. 1(a), where a pictorial representation of nieniory address translation mechanism is shown. Segmentation mechanism 105 translates segmented (logical) address 100 into an address for a continuous, unsegmented address space, called linear address 110. If paging is enabled, paging mechanism 115 translates linear address 110 into physical address 120. If paging 115 is not enabled, linear address 110 is used as physical address 120. Physical address 120 ultimately appears on the address bus coming out of the processor.

An example of a memory management system can be found implemented in the i486"m microprocessors manufactured by Intel Corporation of Santa Clara, California, the Assignee of the present application. In the 1486TM' microprocessors, a logical address consists of the 16-bit segment selector for its segment and a 32-bit offset into the segment. With reference to rig. i(a), logical address 100 is translated into linear address 110 by adding offset 101 to base address 103 of the segment. Base address 103 is derived from segment descriptor 104, which is a data structure in memory which provides the size and location of a segment, as well as access control information. For example, the segment descriptor in a i486Tm microprocessor comes from one of two tables, the global descriptor table (GDT) or the local descriptor table (LDT). There is one GDT for all programs in the system, and one LDT for each separate - program or task being run. If the operating system allows, different programs can share the same LDT. The system also may be set up with no LDTs; all programs will then use the GDT. For more information with regara to the i486TM microprocessors, please refer to 1486"m Microprocessor8 Programmers Reference Manual, available from Intel Corporation, Santa Clara, California.

1 The translated address is linear address 110. If paging mechanism is not used, the linear address 110 is physical address 120. If paging is used, a second level of address translation is needed to produce physical address 120.

Reference is again made to Fig. 1(a). Segment selector 102 is shown pointing to segment descriptor 104 which defines a segment. A program in the i486T," microprocessors may call for more segments than those segment selectors currently occupying segment registers. When this is true, the program uses forms of MOVE instructions to change the contents of the segment registers when it needs to access a new segment. As shown in Fig. I (b), segment selector 132 identifies a segment descriptor by specifying descriptor table 133 and descriptor index 134 within that table.

Reference is now made to Fig. 2, where a descriptor format in the i486TM microprocessor is illustrated. However, because the descriptor format needs to provide backward compatibility for prior processor architectures, the descriptor format becomes scrambled when it is stored in memory. To simplify internal processor operations, a raw scrambled descriptor must be transformed into a unscrambled descriptor, The transformation of a scrambled segment descriptor 300 into an unscrambled segment descriptor 310 for the i486T'M processors is illustrated in Fig. 3.

The present invention provides an improved memory management system for memory operations in microprocessors. As will be described, a segment descriptor cache is used to retain previously fetched, unscrambled, and tested descriptors such that on subsequent segment register loads, the segment descriptor can be sourced from the cache and loaded directly into the segment descriptor register file in one clock, thus bypassing all of the work and overhead usually associated with segment register loads. As will be apparent to those skilled in the at', the memory system of the preseni invention allows segment descriptors to be directly loaded into the segment register when the segment descriptors are cached in the segment descriptor cache after -4associative searching by the segment selector. It the descriptor is not present in the descriptor cache, the sele6tor is used to fetch the descriptor from a descriptor table in memory, unscrambles and tests the descriptor, and updates the descriptor cache with the newly fetched, unscrambled and tested descriptor such that the descriptor may be made available subsequently.

SUMMARY QE THE INVENTION

Therefore, it is an object of the present invention to provide an improved memory system to achieve greater data access speed and efficiency.

it is another object of the present invention to provide an improved memory system with a segment descriptor cache such that the previously fetched and unscrambled segment descriptors can be cached for subsequent usage.

The present invention discloses an improved memory management system in microprocessors for generating a segment descriptor in response to a segment selector. In one embodiment, the memory system of the present invention comprises a descriptor cache to retain previously fetched, unscrambled, and tested descriptors for subsequent access by the same selectors. If the descriptor is not found in the descriptor cache, the selector is used to fetch a scrambled, raw descriptor from memory. The scrambled descriptor is then unscrambled before loading into a segment register. The same unscrambled descriptor is also used to update the descriptor cache such that it may be found subsequently.

-6BRIEF 12ESQRIET1 N QF THE DRAWIN S FIGURE 1(a) is a pictorial representation of a memory address translation mechanism.

segment descriptor.

FIGURE 1(b) illustrates the format of a segment selector.

FIGURE 2 illustrates the format of a segment descriptor.

FIGURE -3 illustrates the process of unscrambling a scrambled FIGURE 4 is a block diagram representation of the process of loading a protected mode segment register.

FIGURE 5 is a block diagram representation of a memory segmentation system incorporating the teaching of the present invention.

FIGURE 6 is a flow chart illustrating the operation of a segment descriptor load.

replacement algorithm.

1 FIGURE 7 illustrates a currently implemented descriptor cache.

FIGURE 8 illustrates a currently implemented psuedo LRU D-ETAILE12 DESCRIEWN OF THE INVENTIQU An improved memory management system for memory operations in computers is disclosed having particular applications for use by microprocessor memory systems employing segmentation technique to enhance memory access efficiency. In the following description for purposes of explanation, specific memories, organizations, architectures, data rates, etc. are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known circuits are shown in block diagram form in order not to obscure the present invention unnecessarily.

Reference is now made to Fig. 4, where the process of loading a segment register is described in block diagram format. It should be appreciated by those skilled in the art that the segment register load is basic to any segmentation memory management scheme. As shown, when the processor encounters a selector from an instruction such as MOVE SEG REG, the processor first tests the selector for any privilege violations such that a less privileged program cannot use a more privileged program to access protected data. If no privilege violation is found, then an 8-byte descriptor is fetched by the processor from memory/data cache based on the selectors identifying a descriptor table and a descriptor within that table. This descriptor is tested for privilege violations. If no privilege violation is found, then the descriptor is unscrambled and information regarding the segment such as the size and location of the segment, as well as control and status information, can be loaded into the segment register for the program to execute.

As will be appreciated by those skilled in the art, the present invention provides an improved memory system by allowing previously fetched and tested descriptors to be retained in an associative memory. On subsequent segment descriptor loads of the same descriptor, the segment descriptor cache is searched. If the segment descriptor cache contains the desired entry, the segment register file can be directly loaded from the segment descriptor cache, thus bypassing all the steps required in a process without the segment descriptor cache. As such, the performance of the memory segmentation system is greatly enhanced.

Reference is now made to Fig. 5, where the memory system for a segment register load incorporating the teaching of the present invention is shown. It should be understood by those skilled in the art that the dimensions of the buses are for illustrative purposes only and that the present invention can be practiced without the specific detail of the illustration. As shown in Fig. 5, system 500 comprises selector privilege tester 510 for testing any privilege violations in selector 501 such that a less privileged program cannot gain access to protected data. As used in the current implementation, when the privilege field of the segment selector contains a privilege level having a greater value (i.e. less privileged) than the program, the selector overrides the program's privilege level. If selector 501 passes privilege tester 510, it is transferred to descriptor address generator 520. Descriptor address generator 520 then generates the proper address of the descriptor in the descriptor table for the selector. Currently, two descriptor tables are used - global and local descriptor tables. The address generation process involves changing the current segment to specify a table based on the selection by selector 501, and setting the Effective Address to selector's index value. With the Effective Address, a descriptor can be fetched from memory 530 and latched into unscrambler 550 and descriptor tester 540. Descriptor tester 540 checks the descriptor to control its access to the segment. If an access violation occurs, a fault is generated to the processor. If no access violation occurs, unscrambler 550 transforms the descriptor into an internal unscrambled form as shown in Fig. 3. A successful descriptor is loaded into segment register file 560 and updated into descriptor cache 570 for future use.

Reference is now made to Fig. 6, where a flow chart identifying the sequence of operation of a segment descriptor load is shown. When selector 501 is encountered as in a MOV Sreg instruction, descriptor cache 570 is looked up. If a corresponding descriptor is found ("a hit"), then the descriptor loaded from descriptor cache 570 inta segment register file 560, along with selector 501. If no corresponding descriptor is found ("a miss"), then selector 501 is tested for privilege violations such that a fault may be generated for a selector with insufficient privilege level. If selector 501 passes the privilege tester 510, then descriptor linear address can be calculated and descriptor is fetched from memory 530. Descriptor is also tested for its pdvilege level and a fault is generated for any privilege violations. Descriptor is unscrambled and the unscrambled descriptor is loaded into segment register file 560. The unscrambled descriptor is also used to update descdptor cache 570.

is Reference is now made to Fig. 7, where a diagram representing the currently implemented segment descriptor cache is shown. Although a 4 -by1 6 set-associative cache is illustrated, it should be understood by those skilled in the art that other organizations can be easily implemented to achieve the desired functionality. Descriptor cache 770 is divided into three arrays: tag array 720, data array 730, and Least Recently Used ("LRU") array 710. The selector bits 14:3] are used as the set number and index into the descriptor cache. Each set is composed of 4 "ways", each of which is associatively searched for the desired entry.

The LAU entry 715 is composed of 3 bits used to determine which way" in the set is least recently used. When a new entry is to be placed in the descriptor cache, the LAU entry for the set determines which entry can be replaced with a minimum of performance impact. As shown in rig. 8, a psuedo LAU algorithm is used with the 3 LAU bits, called LO, L1. & L2, to determine which entry to replace.

Descriptor tag 740 from tag array 720 comprises the remaining selector bits and privilege level of the processor when the entry was placed in the descriptor cache. The tag also contains a valid bit 741 indicating if the entry is valid, and a code segment flag (CS) 742. The CS flag 742 is used to identify the type of descriptor cached, since different protection checks are applied for CS as opposed to data segments. Data array 730 contains unscrambled segment descriptors, each of which contains access rights 751, base address 752, and limit 753.

While the present invention has been described with reference to Figs. 1 through 8, it will be appreciated that the figures are for illustrative purposes only, and do not limit the spirit and scope of the invention.

Claims

-11CLAIMS

1. A memory segmentation system for a microprocessor, said memory segmentation system loading a segment descriptor in a second format into a segment register in response to a segment selector load instruction, said memory segmentation system comprising:

descriptor cache means for receiving said segment selector, said descriptor cache means storing a plurality of segment descriptors in said second format, each of said segment descriptors in said second format being associated with a plurality of segment selectors such that said descriptor cache means outputs a segment descriptor in said second format to said segment register if said segment descriptor in said second format is associated with said segment selector; selector test means for receiving said segment selector when no segment descriptor in said second format in said descriptor cache means is associated with said segment selector, said selector test means determining whether said segment selector has a first predetermined privilege level; descriptor linear address generate means coupled to said selector test means for generating a descriptor linear address from said segment selector; descriptor fetch means for fetching a segment descriptor in a first format from a descriptor table based on said descriptor linear address; descriptor test means for determining whether said segment descriptor in said first format has a second predetermined privilege level; and descriptor format means for formatting said descriptor in said first format into said second format if said segment descrivtor in said first format h3s said second predetermined privilege level, said format means outputting said second format to said descriptor cache means to update its contents such said segment descriptor in said second format is associated with said segment -12selector, said descriptor cache means also outputting said segment descriptor in said second format to said segment register, whereby said segment descriptor in said second format is directly loaded from said descriptor cache means when said segment selector is received by said descriptor cache means.

2. A memory segmentation system according to claim 1, said descriptor cache means further comprising:

a set array comprising a plurality of sets, one of said sets being selected by said segment selector, each of said sets being replaced according to a predetermined replacement algorithm; a tag array comprising a plurality of descriptor tags, said tag array organized into a plurality of sets, each of said sets being a plurality of ways setassociative with said sets from said set array; and a data array comprising a plurality of segment descriptor in said second format, said data array being set-associative with each of said sets of said tag array.

3. A memory segmentation system according to claim 2, wherein said set array implements a least recently used replacement algorithm.

13-

4. In a microprocessor memory management system, a segment of the memory being specified by a segment descriptor in a second format in a segment register, said segment descriptor in said second format being specified by a segment selector, a method of loading said segment descriptor in said second format into a segment register in response to a segment selector load instruction, said method comprising:

inputting a segment selector to descriptor cache means; searching through said descriptor cache means to determine if a segment descriptor in a second format corresponding to said segment selector is present in said descriptor cache means, and if so, loading said segment descriptor in said second format into said segment register, said descriptor cache means comprising a plurality of segment descriptors in said second format being associated with a plurality of corresponding segment selectors; if said segment descriptor in said second format is not present in said descriptor cache means, testing said segment selector in a selector test means lo, determine whether said segment selector has a first predetermined privilege level; generating a descriptor linear address in linear address generate means; fetching said segment descriptor in a first format from a descriptor table based on said descriptor linear address, said descriptor table storing a plurality of segment descriptors in said first format; testing said segment descriptor in said first format in descriptor test means to determine whether said segment descriptor in said first format has a second predetermined privilege level; formatting said segment descriptor in said first format into said second format in descriptor format means; I -14loading said segment djescriptor in said second format into said segment register; updating said descriptor cache means with said segment descriptor in said second format uch that if the same segment selector is received by said descriptor cache means subsequently, said descriptor cache means directly causes said segment descriptor in said second format to be loaded into said segment register, whereby a segment is specified based on said segment descriptor in said second format loaded into said segment register.

5. A method according to claim 4, wherein said descriptor cache means comprises a set array, a tag array, and a data array, said searching through said descriptor cache means further comprising:

said selector specifying a set from said set array; selecting a tag from said tag array corresponding to said set from said set array, said tag array organized into a plurality of ways set- associative with said set array; and selecting said segment descriptor in said second format corresponding to said tag from said tag array.

6. A method according to claim 5, further comprising replacing each of said sets from said set array according a predetermined replacement algorithm.

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