GB2259606A - Electrostatic discharge protection in a semiconductor memory - Google Patents
Electrostatic discharge protection in a semiconductor memory Download PDFInfo
- Publication number
- GB2259606A GB2259606A GB9207050A GB9207050A GB2259606A GB 2259606 A GB2259606 A GB 2259606A GB 9207050 A GB9207050 A GB 9207050A GB 9207050 A GB9207050 A GB 9207050A GB 2259606 A GB2259606 A GB 2259606A
- Authority
- GB
- United Kingdom
- Prior art keywords
- electrostatic discharge
- discharge protection
- pins
- diffusion regions
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000009792 diffusion process Methods 0.000 claims abstract description 47
- 239000012535 impurity Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
One or all power supply pins are protected against electrostatic discharge, in a semiconductor device which uses a plurality of power supply voltage pins VCC1-2 and earthing voltage pins VSS1-2. A semiconductor device such as a DRAM is integrated on a substrate 5, and E.S.D. protection devices 201-220 each comprise a plurality of first impurity diffusion regions 10 formed on the semiconductor substrate 5 in contact with a plurality of input/output pins 1. A plurality of second impurity diffusion regions 20 are in contact with the plurality of earthing voltage pins VSS1-2 in common and are separated from the plurality of first impurity diffusion regions. A plurality of third impurity diffusion regions 30 are in contact with the plurality of power supply voltage pins VGG1-2 in common and are separated from the plurality of first and second impurity diffusion regions. Earth wiring 221 and power supply wiring 231 connect the power supply and earth voltage pins to the devices 201-220. <IMAGE>
Description
' r rg ^A ELECTROSTATIC DISCHARGE PROTECTION DEVICE IN SENUCONDUCTOR
MEMORY The present invention relates to electrostatic discharge protection devices in semiconductor memories.
In a semiconductor memory device, a power supply voltage Vcc and an earthing voltage Vss are used as a basic power supply. These power supply voltages are supplied to the inside of a chip through pins attached to the memory chip. The operation power supply of a semiconductor memory device is improved so as to operate at a lower power supply level, following the trend of lower power and higher integration. The power supply pins being exposed to the outside of chips, they are apt to be affected by outside static electricity. In this case, noise is produced in the power supply pins, thereby causing a direct influence on their internal operations. Such a phenomenon is called electrostatic discharge. This is known as a specific characteristic in a complementary metal oxide semiconductor (C-MOS) memory chips. In order to restrain power supply noise in the interior of a chip caused by the electrostatic discharge, a stress current in the power supply pin caused by electrostatic discharge must be made to flow through another passage so as not to flow into the chip. Electrostatic discharge is discussed, in the paper, 'Transaction of Electron Device", August 1988, page 2133.
Figures 1A and IB of the accompanying diagrammatic drawings show the structures of a known electrostatic discharge protection element. See Korean patent application No. 91-1125.
Referring to the plan view of Figure 1A and the sectional view of Figure 1B, n' diffusion regions 20, 30 are formed respectively at lower parts of metallic distributing wires 21, 31 connected to an earthing voltage Vss and a power supply voltage Vcc through contact regions 22, 32. A metallic distributing wire 11 connected to an input pin 1 is also in contact with an n' diffusion region 10 at a lower part thereof through contact region 12 in a similar form. The three n' diffusion regions 10, 20, 30 are separated from one another by field oxide layers 15 formed on a substrate 5. Here, it may be understood that the substrate 5 is a monolithic substrate on which a semiconductor device or a memory device is formed. The diffusion regions 10, 20, 30 may also be formed within a well having an n- type conduction type. The n' diffusion regions 10, 20, 30 are those which exist to let a stress current flow by utilizing a punch-through phenomenon when the stress current has flowed into their corresponding pins. For instance, when a stress current is generated in the power supply voltage terminal, the stress current runs out through the n' diffusion region 20 in the lower part of the metallic distributing wire 21 and the n' diffusion region 30 in the lower part of the metallic distributing wire 31 of the power supply voltage terminal Wc. That is, a punch through phenomenon between the diffusion regions is utilized.
A conventional instance where the electrostatic discharge protection element illustrated in Figures 1A and 1B is used in a memory chip is illustrated in Figure 2 of the accompanying diagrammatic drawings. It shows a constitution in which a power supply is supplied to each electrostatic discharge protection element of inputloutput pins in a 64K x 16 dynamic random access memory (DRAM) designed by the Toshiba Co, Ltd and Samsung Electronics Co, Ltd. As shown in Figure 2, there are three power supply voltage pins Vccl, Wc2, WO, three earthing voltage pins Vssl, Vss2, VsO and four input/output pins Pl, P2, P3, P4. Electrostatic discharge protection elements 200a, 200b, 200c, 200d of Figure 2 are connected to each input/output pin in a form such as Figures 1A and 1B. The first electrostatic discharge protection element 200a connected to the first inputloutput pin P1 is connected only to the first power supply voltage pin Vccl and first earthing voltage pin Vssl. The second earthing voltage pin Vss2 and third power supply voltage pin Wc3 are connected to the second electrostatic discharge protection element 200b connected to the second input/output pin P2. The second electrostatic discharge protection element 200b is connected to the third electrostatic discharge protection element 200c. The third earthing voltage pin Vss3 and the fourth electrostatic discharge protection element 200d are connected to the third electrostatic discharge protection element 200c connected to the third input/output pin P3. The second power supply voltage pin Wc2 is connected to the fourth electrostatic discharge protection element 200d connected to the fourth input/output pin P4. Here, it may be appreciated that the electrostatic discharge protection elements are connected to the power supply and earthing voltage pins as shown in Figures 1A and 1B.
In such a conventional constitution, the first power supply voltage pin Vccl and the first earthing voltage pin VssI may be protected against electrostatic discharge by thQ first electrostatic discharge protection element 200a, but other pins, that is, the second power supply and earthing voltage pins Wc2, Vss2, and the third power supply and earthing voltage pins Wc3, VsO cannot be protected thereagainst because no punch-through passage exists. Furthermore, the second electrostatic discharge protection element 200b may protect the second earthing voltage pin Vss2 and the third power supply voltage pin Wc3 against electrostatic discharge, but it is unable to protect the first earthing voltage pin Vssl, the first power supply voltage pin Vccl, the second power supply voltage pin Wc2, the third earthing voltage pin Vss3 and the third power supply voltage pin Wc3 thereagainst. Similarly, the third electrostatic discharge protection element 200c may protect the third earthing voltage pin VsO and the third power supply voltage pin Wc3 but it is unable to protect other power supply voltage pins. The fourth electrostatic discharge protection element 200d may protect only the second power supply voltage pin Wc2 and third earthing voltage pin VssI In the case where several power supply voltage pins are used in a highly integrated circuit, a stress phenomenon may be caused by electrostatic discharge among all pins.
S051 if stress is caused to any pin, it must be protected. In the conventional constitution of Figure 2, however, it is impossible to protect all power supply voltage pins against electrostatic discharge.
Preferred embodiments of the present invention aim to provide a device which can protect all pins against electrostatic discharge in a semiconductor device which uses a plurality of power supply voltage pins.
According to one aspect of the present invention, there is provided an electrostatic discharge protection device in a semiconductor device having a plurality of inputloutput pins, a plurality of power supply voltage pins and a plurality of earthing voltage pins, the protection device comprising:
a plurality of first impurity diffusion regions formed on a semiconductor substrate, being in contact with said plurality of input/output pins, respectively; a plurality of second impurity diffusion regions formed on said semiconductor substrate, being in contact with said plurality of power supply voltage pins in common, said plurality of second impurity diffusion regions being separated from said plurality of first impurity diffusion regions by a given distance; and a plurality of third impurity diffusion regions formed on said semiconductor substrate, being in contact with said plurality of earthing voltage pins in common, said plurality of third impurity diffusion regions being separated from said plurality of first and second impurity diffusion regions by a given distance, respectively.
Preferably, said first to third impurity diffusion regions are of the same conductive type.
According to another aspect of the present invention, there is provided an electrostatic discharge protection device in a semiconductor device having a plurality of input/output pins, a plurality of power supply voltage pins and a plurality of earthing voltage pins, the protection device comprising:
a plurality of first impurity diffusion regions of a second conductive type formed on a semiconductor substrate of a first conductive type, being in contact with said plurality of input/output pins, respectively; a plurality of second impurity diffusion regions of the second conductive type formed on said semiconductor substrate, being in contact with said plurality of power supply voltage pins in common; a plurality of third impurity diffusion regions of the second conductive type formed on said semiconductor substrate, being in contact with said plurality of earthing voltage pins in common; and a plurality of field oxide layers formed on said semiconductor substrate, for separating said first to third impurity diffusion regions by a given distance.
Preferably, said first impurity diffusion regions are in contact with said inputloutput pins by means of metal.
Preferably, said second impurity diffusion regions are in contact with said power supply voltage pins by means of metal.
Preferably, said third impurity diffusion regions are in contact with said earthing voltage pins by means of metal.
Preferably, each of said first, second and/or third impurity diffusion regions is formed within a well of the second conductive type, respectively.
According to a further aspect of the present invention, there is provided an electrostatic discharge protection device in a semiconductor device, the protection device comprising:
a plurality of inputloutput pins being respectively connected to an electrostatic discharge protection element; a plurality of power supply voltage pins being connected to said electrostatic discharge protection element in common; and a plurality of earthing voltage pins being connected to said electrostatic discharge protection element in common.
Preferably, said plurality of power supply voltage pins are commonly connected to said electrostatic discharge protection element by means of a metallic distributing wire.
Preferably, said plurality of earthing voltage pins are commonly connected to said electrostatic discharge protection element by means of a 10 metallic distributing wire.
The invention extends to a semiconductor device provided with an electrostatic discharge protection device according to any of the preceding aspects of the invention.
For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 3 and 4 of the accompanying diagrammatic drawings, in which:
Figure 3 is a plan schematic diagram of one example of an electrostatic discharge protection device according to the present invention; and Figure 4 illustrates an optimum embodiment of the present invention.
In the figures, like reference numerals denote like or corresponding parts.
Referring to Figure 3, to meet the convenience of description, those parts which have nothing to do with electrostatic discharge protection in memory chip 400 are not illustrated. All power supply and earthing voltage pins Wcl, Wc2, Wc3, Vssl, Vss2, VsO and electrostatic discharge protection elements 200e, 200f, 200g, 200h are connected in common. The first to third power supply voltage pins Vccl, Wc2, Wc3 are connected in common with the n' diffusion region (numeral 30 of Figure 1B) of first to fourth electrostatic discharge protection elements 200e, 200f, 200g, 200h through the metallic distributing wire 31 for power supply voltage. The first to third earthing voltage pins Vss l, Vss2, Vss3 are connected in common with the n' diffusion region (numeral 20 of Figure 1B) of first to fourth electrostatic discharge protection elements 200e, 200f, 200g, 200h through the metallic distributing wire 21 for earthing voltage. Consequently, a punch through passage may be formed between all power supply pins and all electrostatic discharge protection elements within the chip 400. Thus, if a stress is caused to one power supply pin or to all power supply pins, protective function can be performed against electrostatic discharge. It makes no difference if more power supply pins are installed within the chip.
Figure 4 shows one embodiment according to the layout of Figure 3.
This embodiment of the present invention is applied to a 16Mega DRAM.
Twenty electrostatic discharge protection elements 201, 202,..., 220 are connected to twenty input/output pins in a form such as Figure 1A, respectively, and are all connected in common with power supply and earthing voltage pins Vccl, Wc2, Vssl, VssI So, if a stress is caused to any one of the power supply pins, or to several or all power supply pins, electrostatic discharge protection operations may be conducted regardless of position. Although an instance where four pins are installed is described in the embodiment of Figure 4, power supply pins may be installed according to the present invention irrespective of number. In this case, however, the thickness of power line which is connected to the electrostatic discharge protection elements must be optimum in order to minimize influence caused by power supply noise when the electrostatic discharge protection elements and the power supply pins are connected to each other.
The above-described embodiments of the present invention are able to protect against stress caused to one power supply pin or to all power supply pins by electrostatic discharge in a semiconductor memory device, and therefore have the effect of realizing a more stable and reliable semiconductor memory device against power supply noise caused by electrostatic discharge.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.
The term "ground potentiaP (or "ground voltage" or "earth" potential or voltage) is used conveniently in this specification to denote a reference potential. As will be understood by those skilled in the art, although such reference potential may typically be zero potential, it is not essential that it is so, and may be a reference potential other than zero.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features andlor steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
11 -
Claims (13)
1. An electrostatic discharge protection device in a semiconductor device having a plurality of input/output pins, a plurality of power supply voltage pins and a plurality of earthing voltage pins, the protection device comprising:
a plurality of first impurity diffusion regions formed on a semiconductor substrate, being in contact with said plurality of input/output pins, respectively; a plurality of second impurity diffusion regions formed on said semiconductor substrate, being in contact with said plurality of power supply voltage pins in common, said plurality of second impurity diffusion regions being separated from said plurality of first impurity diffusion regions by a given distance; and a plurality of third impurity diffusion regions formed on said semiconductor substrate, being in contact with said plurality of earthing voltage pins in common, said plurality of third impurity diffusion regions being separated from said plurality of first and second impurity diffusion regions by a given distance, respectively.
2. An electrostatic discharge protection device according to claim 1, wherein said first to third impurity diffusion regions are of the same conductive type.
3. An electrostatic discharge protection device in a semiconductor device having a plurality of input/output pins, a plurality of power supply voltage pins and a plurality of earthing voltage pins, the protection device comprising:
a plurality of first impurity diffusion regions Of a second conductive type formed on a semiconductor substrate of a first conductive type, being in contact with said plurality of input/output pins, respectively; a plurality of second impurity diffusion regions of the second conductive type formed on said semiconductor substrate, being in contact with said plurality of power supply voltage pins in common; a plurality of third impurity diffusion regions of the second conductive type formed on said semiconductor substrate, being in contact with said plurality of earthing voltage pins in common; and is a plurality of field oxide layers formed on said semiconductor substrate, for separating said first to third impurity diffusion regions by a given distance.
4. An electrostatic discharge protection device according to claim 3, wherein said first impurity diffusion regions are in contact with said inputloutput pins by means of metal.
5. An electrostatic discharge protection device according to claim 3 or 4, wherein said second impurity diffusion regions are in contact with said power supply voltage pins by means of metal.
6. An electrostatic discharge protection device according to claim 3, 4 or 5, wherein said third impurity diffusion regions are in contact with said earthing voltage pins by means of metal.
7. An electrostatic discharge protection device according to any of claims 3 to 6, wherein each of said first, second and/or third impurity diffusion regions is formed within a well of the second conductive type, respectively.
8. An electrostatic discharge protection device in a semiconductor device, the protection device comprising:
a plurality of input/output pins being respectively connected to an electrostatic discharge protection element; is a plurality of power supply voltage pins being connected to said electrostatic discharge protection element in common; and a plurality of earthing voltage pins being connected to said electrostatic discharge protection element in common.
9. An electrostatic discharge protection device according to claim 8, wherein said plurality of power supply voltage pins are commonly connected to said electrostatic discharge protection element by means of a metallic distributing wire.
10. An electrostatic discharge protection device according to claim 8 or 9, wherein said plurality of earthing voltage pins are commonly connected to said electrostatic discharge protection element by means of a metallic distributing wire.
11. An electrostatic discharge protection device substantially as hereinbefore described with reference to Figures 1 and 3 of the accompanying drawings.
12. An electrostatic discharge protection device substantially as hereinbefore described with reference to Figures 1, 3 and 4 of the 10 accompanying drawings.
13. A semiconductor device provided with an electrostatic discharge protection device according to any of the preceding claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910016125A KR940009605B1 (en) | 1991-09-16 | 1991-09-16 | Electrostatic discharge protection device of semiconductor memory |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9207050D0 GB9207050D0 (en) | 1992-05-13 |
| GB2259606A true GB2259606A (en) | 1993-03-17 |
| GB2259606B GB2259606B (en) | 1996-01-17 |
Family
ID=19319990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9207050A Expired - Fee Related GB2259606B (en) | 1991-09-16 | 1992-03-31 | Electrostatic discharge protection device in semiconductor memory |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH077820B2 (en) |
| KR (1) | KR940009605B1 (en) |
| DE (1) | DE4207010C2 (en) |
| GB (1) | GB2259606B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003007380A1 (en) * | 2001-07-13 | 2003-01-23 | Ricoh Company, Ltd. | Semiconductor apparatus with improved esd withstanding voltage |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0291242A2 (en) * | 1987-05-15 | 1988-11-17 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
| EP0352896A2 (en) * | 1988-06-27 | 1990-01-31 | Advanced Micro Devices, Inc. | ESD protection circuitry for bipolar processes |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59100550A (en) * | 1982-11-30 | 1984-06-09 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6153761A (en) * | 1984-08-24 | 1986-03-17 | Hitachi Ltd | Semiconductor device |
| JPH0793361B2 (en) * | 1987-04-17 | 1995-10-09 | 日本電気株式会社 | Semiconductor input protection device |
| JPH02111064A (en) * | 1988-10-20 | 1990-04-24 | Nec Corp | Electrostatic breakdown protective circuit of monolithic ic |
| JPH061802B2 (en) * | 1989-03-14 | 1994-01-05 | 株式会社東芝 | Semiconductor device |
| JPH065705B2 (en) * | 1989-08-11 | 1994-01-19 | 株式会社東芝 | Semiconductor integrated circuit device |
| JPH03180052A (en) * | 1989-12-08 | 1991-08-06 | Nec Corp | Semiconductor integrated circuit |
| KR920015549A (en) * | 1991-01-23 | 1992-08-27 | 김광호 | Electrostatic Discharge Protection Device for Semiconductor Devices |
-
1991
- 1991-09-16 KR KR1019910016125A patent/KR940009605B1/en not_active IP Right Cessation
-
1992
- 1992-03-05 DE DE4207010A patent/DE4207010C2/en not_active Expired - Fee Related
- 1992-03-31 GB GB9207050A patent/GB2259606B/en not_active Expired - Fee Related
- 1992-03-31 JP JP4077037A patent/JPH077820B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0291242A2 (en) * | 1987-05-15 | 1988-11-17 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
| EP0352896A2 (en) * | 1988-06-27 | 1990-01-31 | Advanced Micro Devices, Inc. | ESD protection circuitry for bipolar processes |
Non-Patent Citations (1)
| Title |
|---|
| KOREAN PATENT APPLICATION No. 91-1125 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003007380A1 (en) * | 2001-07-13 | 2003-01-23 | Ricoh Company, Ltd. | Semiconductor apparatus with improved esd withstanding voltage |
| US6744100B2 (en) | 2001-07-13 | 2004-06-01 | Ricoh Company, Ltd. | Semiconductor apparatus with improved ESD withstanding voltage |
| US6946708B2 (en) | 2001-07-13 | 2005-09-20 | Ricoh Company, Ltd. | Semiconductor apparatus with improved ESD withstanding voltage |
| CN1319171C (en) * | 2001-07-13 | 2007-05-30 | 株式会社理光 | Semiconductor apparatus with improved ESD withstanding voltage |
| US7242062B2 (en) | 2001-07-13 | 2007-07-10 | Ricoh Company, Ltd. | Semiconductor apparatus with improved ESD withstanding voltage |
| US7638848B2 (en) | 2001-07-13 | 2009-12-29 | Ricoh Company, Ltd. | Semiconductor apparatus with improved ESD withstanding voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4207010C2 (en) | 1999-01-14 |
| DE4207010A1 (en) | 1993-03-25 |
| GB9207050D0 (en) | 1992-05-13 |
| JPH077820B2 (en) | 1995-01-30 |
| JPH05129526A (en) | 1993-05-25 |
| GB2259606B (en) | 1996-01-17 |
| KR930006902A (en) | 1993-04-22 |
| KR940009605B1 (en) | 1994-10-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20100331 |