GB2258947A - Semiconductor circuit protection device - Google Patents
Semiconductor circuit protection device Download PDFInfo
- Publication number
- GB2258947A GB2258947A GB9217737A GB9217737A GB2258947A GB 2258947 A GB2258947 A GB 2258947A GB 9217737 A GB9217737 A GB 9217737A GB 9217737 A GB9217737 A GB 9217737A GB 2258947 A GB2258947 A GB 2258947A
- Authority
- GB
- United Kingdom
- Prior art keywords
- voltage
- line
- semiconductor device
- ground voltage
- source line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000009792 diffusion process Methods 0.000 claims description 15
- 230000015556 catabolic process Effects 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
_) -) -,.3 -) 4 -7 " 1) 1 SEMICONDUCTOR DEVICE The present invention
relates to semiconductor devices and protecting them from an excess voltage, such as an electrostatic voltage.
In one arrangement, when an electrostatic voltage is applied through a voltage source line to a semiconductor device with a pin grounded, an electrically floated P-well is forwardly biased, dropping the voltage. Consequently, the electrostatic voltage is discharged owing to the reverse breakdown between the P-well and an n-type diffusion region forming the source and drain of an NMOS transistor. Thus, as the leakage current is increased between the voltage source line and ground voltage line, it is impossible for the semiconductor device to work.
Referring to Figure 1 of the accompanying diagrammatic drawings, a conventional semiconductor device has a voltage source line 1 and a ground voltage line 3 which extend in parallel with each other. When an electrostatic voltage supplied through the voltage source line 1 is increased rapidly, since there is no passage for discharging the electrostatic voltage loaded on the 20 voltage source line 1, the semiconductor device may be destroyed.
Preferred embodiments of the present invention aim to provide a semiconductor device with means for protection against an electrostatic voltage.
According to an aspect of the present invention, there is provided an MOS transistor for guiding an electrostatic voltage between a voltage source line and a ground voltage line of a semiconductor device.
According to another aspect of the present invention, there is provided a semiconductor device having an internal circuit connected between a voltage source line and a ground voltage line, said semiconductor device further comprising an electrostatic voltage protection means which is connected between said voltage source line and said ground voltage line in parallel with said internal circuit, and is arranged to operate faster than said internal circuit when a voltage higher than a given voltage is supplied to said voltage source line, in order to conduct said higher voltage and thereby protect the internal circuit from the higher voltage.
is Preferably, said voltage protection means comprises an NMOS transistor, a channel of said NMOS transistor being connected between said voltage source line and said ground voltage line, and a gate of said NMOS transistor being grounded to the said ground voltage line.
Preferably, said NMOS transistor has a lower breakdown voltage than that of a transistor of said internal circuit.
According to a further aspect of the present invention, there is provided a semiconductor device having an internal circuit connected between a voltage source line and a ground voltage line, said semiconductor device further comprising:
first and second diffusion regions of a given conductive type formed below said voltage source line and said ground voltage line respectively, and contacting said voltage source line and said ground voltage line respectively through at least one contact region formed in each of said voltage source line and said ground voltage line, said voltage source line and said ground voltage line being in parallel with each other in a given direction; and a conductive layer extending over said first and second diffusion regions and said ground voltage line, and contacting said ground voltage line through at least one contact region formed in said ground voltage line.
Preferably, said given conductive type of said diffusion region is an ntype.
Preferably, said conductive layer is made of polycrystalline silicon.
For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, 15 to Figures 2 to 4 of the accompanying diagrammatic drawings, in which:
Figure 2 schematically illustrates the layout of one example of a semiconductor device according to an embodiment of the present invention; Figure 3 schematically illustrates the layout of an example of a semiconductor device according to another embodiment of the present invention; and Figure 4 shows an equivalent circuit of Figures 2 and 3.
Referring to Figure 2, a voltage source line 5 and a ground voltage line 7 extend in parallel with each other in a first direction. Below the voltage source line 5 and ground voltage line 7 there extends in a second direction perpendicular to the first direction an n-type diffusion region 9 which contacts the voltage source line 5 and ground voltage line 7 respectively via first and second contact regions 13 and 15. Further, a polytrystalline silicon line 11 extends over the diffusion region 9 and ground voltage line 7 and contacts the ground voltage line 7 through a third contact region 17. The diffusion region 9 forms the drain and source of an NMOS transistor and the polytrystalline line 11 the gate thereof.
In the other embodiment shown in Figure 3, first and second n-type diffusion regions 25 and 27 respectively are formed below a voltage source line 21 and a ground voltage line 23 which are in parallel with each other in a first direction. The first diffusion region 25 contacts the voltage source line 21 through first and second contact regions 31 and 33, while the second diffusion region 27 contacts the ground voltage line 23 through third and fourth contact regions 35 and 37. A conductive layer 29 is formed over the diffusion regions 25, 27 and ground voltage line 23, and contacts the ground voltage line 23 through a fifth contact region 39. The first and second diffusion regions 25 and 27 respectively form the drain and source of an NMOS transistor, and the conductive layer 29 the gate thereof.
Referring to Figure 4, an equivalent circuit of Figures 2 and 3 includes an internal circuit 41 and an NMOS transistor 45 connected in.parallel with each other between the voltage source line Vcc and ground voltage line Vss. One end of the ground voltage line is also connected to an inputloutput pad 43. The NMOS transistor 45 is designed to perform breakdown operation at a lower voltage than that of a transistor of the internal circuit 41. That is, when a voltage higher than a given voltage is applied to the voltage source line by an electrostatic voltage, the NMOS transistor 45 operates faster than A the transistor of the internal circuit 41 because the breakdown voltage of the NMOS transistor 45 is lower than that of the transistor of the internal circuit 41. Consequently, the electrostatic voltage is discharged via the NMOS transistor 45 to ground, so that the internal circuit is protected from the adverse effect of the electrostatic voltage.
As stated above, the illustrated example devices of the invention employ an NMOS transistor connected between the voltage source line and ground voltage line in parallel with the internal circuit so as to discharge the electrostatic voltage via the NMOS transistor to ground. Consequently, even if the electrostatic voltage is transferred via the voltage source line in operation, the internal circuit is not affected by it, thus securing stable operation of the semiconductor device.
While preferred embodiments of the invention have been particularly shown and described, it will be understood by those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.
The term "ground potentiaP (or like terms such as "ground voltage" or "earth" potential or voltage) is used conveniently in this specification to denote a reference potential. As will be understood by those skilled in the art, although such reference potential may typically be zero potential, it is not essential that it is so, and may be a reference potential other than zero.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and -6 k the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), andlor all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
5.
Claims (7)
1. A semiconductor device having an internal circuit connected between a voltage source line and a ground voltage line, said semiconductor device further comprising an electrostatic voltage protection means which is connected between said voltage source line and said ground voltage line in parallel with said internal circuit, and is arranged to operate faster than said internal circuit when a voltage higher than a given voltage is supplied to said voltage source line, in order to conduct said higher voltage and thereby protect the internal circuit from the higher voltage.
2. A semiconductor device as claimed in claim 1, wherein said voltage protection means comprises an NMOS transistor, a channel of said NMOS transistor being connected between said voltage source line and said ground voltage line, and a gate of said NMOS transistor being grounded to the said ground voltage line.
3. A semiconductor device as claimed in claim 2Y wherein said NMOS transistor has a lower breakdown voltage than that of a transistor of said internal circuit.
4. A semiconductor device having an internal circuit connected between a voltage source line and a ground voltage line, said semiconductor device further comprising:
first and second diffusion regions of a given conductive type formed below said voltage source line and said ground voltage line respectively, and contacting said voltage source line and said ground voltage line respectively through at least one contact region formed in each of said voltage source line and said ground voltage line, said voltage source line and said ground voltage line being in parallel with each other in a given direction; and j! a conductive layer extending over said first and second diffusion regions and said ground voltage line, and contacting said ground voltage line through at least one contact region formed in said ground voltage line.
5. A semiconductor device as claimed in claim 4, wherein said given 10 conductive type of said diffusion region is an n-type.
6. A semiconductor device as claimed in claim 4 or 5, wherein said conductive layer is made of polycrystalline silicon.
7. A semiconductor device substantially as hereinbefore described with reference to Figure 2, 3 or 4 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910014408A KR930005184A (en) | 1991-08-21 | 1991-08-21 | Semiconductor device for preventing electrostatic voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9217737D0 GB9217737D0 (en) | 1992-09-30 |
| GB2258947A true GB2258947A (en) | 1993-02-24 |
Family
ID=19318850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9217737A Withdrawn GB2258947A (en) | 1991-08-21 | 1992-08-20 | Semiconductor circuit protection device |
Country Status (6)
| Country | Link |
|---|---|
| KR (1) | KR930005184A (en) |
| DE (1) | DE4223466A1 (en) |
| FR (1) | FR2680603A1 (en) |
| GB (1) | GB2258947A (en) |
| IT (1) | IT1256405B (en) |
| TW (1) | TW200601B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100471396B1 (en) * | 2001-05-17 | 2005-02-21 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing thin film transistor liquid crystal display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0058557A1 (en) * | 1981-02-17 | 1982-08-25 | Fujitsu Limited | Protection element for a semiconductor device |
| EP0162460A2 (en) * | 1984-05-22 | 1985-11-27 | Nec Corporation | Integrated circuit with an input protective device |
| US4903093A (en) * | 1987-06-05 | 1990-02-20 | Hitachi, Ltd. | Semiconductor integrated circuit device double isolated CMOS input protection resistor |
| US4990984A (en) * | 1987-11-27 | 1991-02-05 | Nec Corporation | Semiconductor device having protective element |
| US5019883A (en) * | 1987-01-28 | 1991-05-28 | Mitsubishi Denki Kabushiki Kaisha | Input protective apparatus of semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010767A (en) * | 1983-06-30 | 1985-01-19 | Fujitsu Ltd | Semiconductor device |
| JPS6143468A (en) * | 1984-08-07 | 1986-03-03 | Mitsubishi Electric Corp | Protective circuit |
| JPS61137359A (en) * | 1984-12-10 | 1986-06-25 | Nec Corp | Protective circuit |
| EP0276850A3 (en) * | 1987-01-28 | 1990-06-27 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with latch up preventing structure |
-
1991
- 1991-08-21 KR KR1019910014408A patent/KR930005184A/en not_active IP Right Cessation
-
1992
- 1992-07-09 TW TW081105428A patent/TW200601B/zh active
- 1992-07-16 DE DE4223466A patent/DE4223466A1/en not_active Withdrawn
- 1992-08-18 IT ITMI922000A patent/IT1256405B/en active IP Right Grant
- 1992-08-20 FR FR9210147A patent/FR2680603A1/en active Pending
- 1992-08-20 GB GB9217737A patent/GB2258947A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0058557A1 (en) * | 1981-02-17 | 1982-08-25 | Fujitsu Limited | Protection element for a semiconductor device |
| EP0162460A2 (en) * | 1984-05-22 | 1985-11-27 | Nec Corporation | Integrated circuit with an input protective device |
| US5019883A (en) * | 1987-01-28 | 1991-05-28 | Mitsubishi Denki Kabushiki Kaisha | Input protective apparatus of semiconductor device |
| US4903093A (en) * | 1987-06-05 | 1990-02-20 | Hitachi, Ltd. | Semiconductor integrated circuit device double isolated CMOS input protection resistor |
| US4990984A (en) * | 1987-11-27 | 1991-02-05 | Nec Corporation | Semiconductor device having protective element |
Also Published As
| Publication number | Publication date |
|---|---|
| ITMI922000A0 (en) | 1992-08-18 |
| DE4223466A1 (en) | 1993-02-25 |
| GB9217737D0 (en) | 1992-09-30 |
| IT1256405B (en) | 1995-12-05 |
| ITMI922000A1 (en) | 1994-02-18 |
| KR930005184A (en) | 1993-03-23 |
| FR2680603A1 (en) | 1993-02-26 |
| TW200601B (en) | 1993-02-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |